src/kernel/linux/v4.19/include/dt-bindings/clock/mt6880-clk.h

/*  SPDX-License-Identifier: GPL-2.0 */  

/*

 * Copyright (c) 2019 MediaTek Inc.

 */
#ifndef _DT_BINDINGS_CLK_MT6880_H
#define _DT_BINDINGS_CLK_MT6880_H

/* TOPCKGEN */

#define CLK_TOP_ARMPLL_LL_CK_VRPOC	0
#define CLK_TOP_CCIPLL_CK_VRPOC_CCI	1
#define CLK_TOP_MFGPLL			2
#define CLK_TOP_MAINPLL			3
#define CLK_TOP_MAINPLL_D3		4
#define CLK_TOP_MAINPLL_D4		5
#define CLK_TOP_MAINPLL_D4_D2		6
#define CLK_TOP_MAINPLL_D4_D4		7
#define CLK_TOP_MAINPLL_D4_D8		8
#define CLK_TOP_MAINPLL_D4_D16		9
#define CLK_TOP_MAINPLL_D5		10
#define CLK_TOP_MAINPLL_D5_D2		11
#define CLK_TOP_MAINPLL_D5_D4		12
#define CLK_TOP_MAINPLL_D5_D8		13
#define CLK_TOP_MAINPLL_D6		14
#define CLK_TOP_MAINPLL_D6_D2		15
#define CLK_TOP_MAINPLL_D6_D4		16
#define CLK_TOP_MAINPLL_D6_D8		17
#define CLK_TOP_MAINPLL_D7		18
#define CLK_TOP_MAINPLL_D7_D2		19
#define CLK_TOP_MAINPLL_D7_D4		20
#define CLK_TOP_MAINPLL_D7_D8		21
#define CLK_TOP_MAINPLL_D8		22
#define CLK_TOP_MAINPLL_D9		23
#define CLK_TOP_UNIVPLL			24
#define CLK_TOP_UNIVPLL_D2		25
#define CLK_TOP_UNIVPLL_D3		26
#define CLK_TOP_UNIVPLL_D4		27
#define CLK_TOP_UNIVPLL_D4_D2		28
#define CLK_TOP_UNIVPLL_D4_D4		29
#define CLK_TOP_UNIVPLL_D4_D8		30
#define CLK_TOP_UNIVPLL_D5		31
#define CLK_TOP_UNIVPLL_D5_D2		32
#define CLK_TOP_UNIVPLL_D5_D4		33
#define CLK_TOP_UNIVPLL_D5_D8		34
#define CLK_TOP_UNIVPLL_D5_D16		35
#define CLK_TOP_UNIVPLL_D6		36
#define CLK_TOP_UNIVPLL_D6_D2		37
#define CLK_TOP_UNIVPLL_D6_D4		38
#define CLK_TOP_UNIVPLL_D6_D8		39
#define CLK_TOP_UNIVPLL_D6_D16		40
#define CLK_TOP_UNIVPLL_D7		41
#define CLK_TOP_UNIVPLL_D7_D2		42
#define CLK_TOP_UNIVPLL_192M		43
#define CLK_TOP_UNIVPLL_192M_D2		44
#define CLK_TOP_UNIVPLL_192M_D4		45
#define CLK_TOP_UNIVPLL_192M_D8		46
#define CLK_TOP_UNIVPLL_192M_D16	47
#define CLK_TOP_UNIVPLL_192M_D32	48
#define CLK_TOP_USB20_192M		49
#define CLK_TOP_USB20_PLL_D2		50
#define CLK_TOP_USB20_PLL_D4		51
#define CLK_TOP_APLL1			52
#define CLK_TOP_APLL1_D2		53
#define CLK_TOP_APLL1_D4		54
#define CLK_TOP_APLL1_D8		55
#define CLK_TOP_APLL2			56
#define CLK_TOP_APLL2_D2		57
#define CLK_TOP_APLL2_D4		58
#define CLK_TOP_APLL2_D8		59
#define CLK_TOP_MMPLL			60
#define CLK_TOP_MMPLL_D3		61
#define CLK_TOP_MMPLL_D4		62
#define CLK_TOP_MMPLL_D4_D2		63
#define CLK_TOP_MMPLL_D4_D4		64
#define CLK_TOP_MMPLL_D5		65
#define CLK_TOP_MMPLL_D5_D2		66
#define CLK_TOP_MMPLL_D5_D4		67
#define CLK_TOP_MMPLL_D6		68
#define CLK_TOP_MMPLL_D6_D2		69
#define CLK_TOP_MMPLL_D7		70
#define CLK_TOP_MMPLL_D9		71
#define CLK_TOP_TVDPLL			72
#define CLK_TOP_TVDPLL_D2		73
#define CLK_TOP_TVDPLL_D4		74
#define CLK_TOP_TVDPLL_D8		75
#define CLK_TOP_TVDPLL_D16		76
#define CLK_TOP_MSDCPLL			77
#define CLK_TOP_MSDCPLL_D2		78
#define CLK_TOP_MSDCPLL_D4		79
#define CLK_TOP_MSDCPLL_D8		80
#define CLK_TOP_MSDCPLL_D16		81
#define CLK_TOP_CLKRTC			82
#define CLK_TOP_TCK_26M_MX8		83
#define CLK_TOP_TCK_26M_MX9		84
#define CLK_TOP_TCK_26M_MX10		85
#define CLK_TOP_TCK_26M_MX11		86
#define CLK_TOP_TCK_26M_MX12		87
#define CLK_TOP_CSW_FAXI		88
#define CLK_TOP_CSW_F26M_CK_D52		89
#define CLK_TOP_CSW_F26M_CK_D2		90
#define CLK_TOP_OSC			91
#define CLK_TOP_OSC_D2			92
#define CLK_TOP_OSC_D4			93
#define CLK_TOP_OSC_D8			94
#define CLK_TOP_OSC_D16			95
#define CLK_TOP_OSC_D10			96
#define CLK_TOP_OSC_D20			97
#define CLK_TOP_TVDPLL_D5		98
#define CLK_TOP_TVDPLL_D10		99
#define CLK_TOP_TVDPLL_D25		100
#define CLK_TOP_TVDPLL_D50		101
#define CLK_TOP_NET2PLL			102
#define CLK_TOP_WEDMCUPLL		103
#define CLK_TOP_MEDMCUPLL		104
#define CLK_TOP_SGMIIPLL		105
#define CLK_TOP_F26M			106
#define CLK_TOP_FRTC			107
#define CLK_TOP_AXI			108
#define CLK_TOP_SPM			109
#define CLK_TOP_BUS			110
#define CLK_TOP_MM			111
#define CLK_TOP_MFG_REF			112
#define CLK_TOP_MFG			113
#define CLK_TOP_FUART			114
#define CLK_TOP_MSDC50_0_HCLK		115
#define CLK_TOP_MSDC50_0		116
#define CLK_TOP_MSDC30_1		117
#define CLK_TOP_AUDIO			118
#define CLK_TOP_AUD_INTBUS		119
#define CLK_TOP_AUD_ENGEN1		120
#define CLK_TOP_AUD_ENGEN2		121
#define CLK_TOP_AUD_1			122
#define CLK_TOP_AUD_2			123
#define CLK_TOP_FPWRAP_ULPOSC		124
#define CLK_TOP_ATB			125
#define CLK_TOP_PWRMCU			126
#define CLK_TOP_DBI			127
#define CLK_TOP_FDISP_PWM		128
#define CLK_TOP_FUSB_TOP		129
#define CLK_TOP_FSSUSB_XHCI		130
#define CLK_TOP_I2C			131
#define CLK_TOP_TL			132
#define CLK_TOP_DPMAIF_MAIN		133
#define CLK_TOP_PWM			134
#define CLK_TOP_SPMI_M_MST		135
#define CLK_TOP_SPMI_P_MST		136
#define CLK_TOP_DVFSRC			137
#define CLK_TOP_MCUPM			138
#define CLK_TOP_SFLASH			139
#define CLK_TOP_GCPU			140
#define CLK_TOP_SPI			141
#define CLK_TOP_SPIS			142
#define CLK_TOP_ECC			143
#define CLK_TOP_NFI1X			144
#define CLK_TOP_SPINFI_BCLK		145
#define CLK_TOP_NETSYS			146
#define CLK_TOP_MEDSYS			147
#define CLK_TOP_HSM_CRYPTO		148
#define CLK_TOP_HSM_ARC			149
#define CLK_TOP_EIP97			150
#define CLK_TOP_SNPS_ETH_312P5M		151
#define CLK_TOP_SNPS_ETH_250M		152
#define CLK_TOP_SNPS_ETH_62P4M_PTP	153
#define CLK_TOP_SNPS_ETH_50M_RMII	154
#define CLK_TOP_NETSYS_500M		155
#define CLK_TOP_NETSYS_MED_MCU		156
#define CLK_TOP_NETSYS_WED_MCU		157
#define CLK_TOP_NETSYS_2X		158
#define CLK_TOP_SGMII			159
#define CLK_TOP_SGMII_SBUS		160
#define CLK_TOP_SYS_26M			161
#define CLK_TOP_F_UFS_MP_SAP_CFG	162
#define CLK_TOP_F_UFS_TICK1US		163
#define CLK_TOP_AXI_SEL			164
#define CLK_TOP_SPM_SEL			165
#define CLK_TOP_BUS_AXIMEM_SEL		166
#define CLK_TOP_MM_SEL			167
#define CLK_TOP_MFG_REF_SEL		168
#define CLK_TOP_MFG_SEL			169
#define CLK_TOP_UART_SEL		170
#define CLK_TOP_MSDC50_0_HCLK_SEL	171
#define CLK_TOP_MSDC50_0_SEL		172
#define CLK_TOP_MSDC30_1_SEL		173
#define CLK_TOP_AUDIO_SEL		174
#define CLK_TOP_AUD_INTBUS_SEL		175
#define CLK_TOP_AUD_ENGEN1_SEL		176
#define CLK_TOP_AUD_ENGEN2_SEL		177
#define CLK_TOP_AUD_1_SEL		178
#define CLK_TOP_AUD_2_SEL		179
#define CLK_TOP_PWRAP_ULPOSC_SEL	180
#define CLK_TOP_ATB_SEL			181
#define CLK_TOP_PWRMCU_SEL		182
#define CLK_TOP_DBI_SEL			183
#define CLK_TOP_DISP_PWM_SEL		184
#define CLK_TOP_USB_TOP_SEL		185
#define CLK_TOP_SSUSB_XHCI_SEL		186
#define CLK_TOP_I2C_SEL			187
#define CLK_TOP_TL_SEL			188
#define CLK_TOP_DPMAIF_MAIN_SEL		189
#define CLK_TOP_PWM_SEL			190
#define CLK_TOP_SPMI_M_MST_SEL		191
#define CLK_TOP_SPMI_P_MST_SEL		192
#define CLK_TOP_DVFSRC_SEL		193
#define CLK_TOP_MCUPM_SEL		194
#define CLK_TOP_SFLASH_SEL		195
#define CLK_TOP_GCPU_SEL		196
#define CLK_TOP_SPI_SEL			197
#define CLK_TOP_SPIS_SEL		198
#define CLK_TOP_ECC_SEL			199
#define CLK_TOP_NFI1X_SEL		200
#define CLK_TOP_SPINFI_BCLK_SEL		201
#define CLK_TOP_NETSYS_SEL		202
#define CLK_TOP_MEDSYS_SEL		203
#define CLK_TOP_HSM_CRYPTO_SEL		204
#define CLK_TOP_HSM_ARC_SEL		205
#define CLK_TOP_EIP97_SEL		206
#define CLK_TOP_SNPS_ETH_312P5M_SEL	207
#define CLK_TOP_SNPS_ETH_250M_SEL	208
#define CLK_TOP_SNPS_ETH_62P4M_PTP_SEL	209
#define CLK_TOP_SNPS_ETH_50M_RMII_SEL	210
#define CLK_TOP_NETSYS_500M_SEL		211
#define CLK_TOP_NETSYS_MED_MCU_SEL	212
#define CLK_TOP_NETSYS_WED_MCU_SEL	213
#define CLK_TOP_NETSYS_2X_SEL		214
#define CLK_TOP_SGMII_SEL		215
#define CLK_TOP_SGMII_SBUS_SEL		216
#define CLK_TOP_APLL_I2S0_MCK_SEL	217
#define CLK_TOP_APLL_I2S1_MCK_SEL	218
#define CLK_TOP_APLL_I2S2_MCK_SEL	219
#define CLK_TOP_APLL_I2S4_MCK_SEL	220
#define CLK_TOP_APLL_TDMOUT_MCK_SEL	221
#define CLK_TOP_APLL_I2S5_MCK_SEL	222
#define CLK_TOP_APLL_I2S6_MCK_SEL	223
#define CLK_TOP_APLL12_CK_DIV0		224
#define CLK_TOP_APLL12_CK_DIV1		225
#define CLK_TOP_APLL12_CK_DIV2		226
#define CLK_TOP_APLL12_CK_DIV4		227
#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M	228
#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B	229
#define CLK_TOP_APLL12_CK_DIV5		230
#define CLK_TOP_APLL12_CK_DIV6		231
#define CLK_TOP_NR_CLK			232

/* DBGSYS_DEM */

#define CLK_DBGSYS_DEM_ATB_EN		0
#define CLK_DBGSYS_DEM_BUSCLK_EN	1
#define CLK_DBGSYS_DEM_SYSCLK_EN	2
#define CLK_DBGSYS_DEM_NR_CLK		3

/* INFRACFG_AO */

#define CLK_IFRAO_INFRA_DCM_RG_FORCE	0
#define CLK_IFRAO_PMIC_TMR_SET		1
#define CLK_IFRAO_PMIC_AP_SET		2
#define CLK_IFRAO_PMIC_MD_SET		3
#define CLK_IFRAO_PMIC_CONN_SET		4
#define CLK_IFRAO_SCPSYS		5
#define CLK_IFRAO_SEJ			6
#define CLK_IFRAO_APXGPT		7
#define CLK_IFRAO_MCUPM			8
#define CLK_IFRAO_GCE			9
#define CLK_IFRAO_GCE2			10
#define CLK_IFRAO_THERM			11
#define CLK_IFRAO_I2C0			12
#define CLK_IFRAO_I2C1			13
#define CLK_IFRAO_I2C2			14
#define CLK_IFRAO_I2C3			15
#define CLK_IFRAO_PWM_HCLK		16
#define CLK_IFRAO_PWM1			17
#define CLK_IFRAO_PWM2			18
#define CLK_IFRAO_PWM3			19
#define CLK_IFRAO_PWM4			20
#define CLK_IFRAO_PWM5			21
#define CLK_IFRAO_PWM			22
#define CLK_IFRAO_UART0			23
#define CLK_IFRAO_UART1			24
#define CLK_IFRAO_UART2			25
#define CLK_IFRAO_UART3			26
#define CLK_IFRAO_GCE_26M_SET		27
#define CLK_IFRAO_CQ_DMA_FPC		28
#define CLK_IFRAO_SPI0			29
#define CLK_IFRAO_MSDC0			30
#define CLK_IFRAO_MSDC1			31
#define CLK_IFRAO_GCPU			32
#define CLK_IFRAO_TRNG			33
#define CLK_IFRAO_AUXADC		34
#define CLK_IFRAO_CPUM			35
#define CLK_IFRAO_CCIF1_AP		36
#define CLK_IFRAO_CCIF1_MD		37
#define CLK_IFRAO_AUXADC_MD		38
#define CLK_IFRAO_PCIE_TL_26M		39
#define CLK_IFRAO_MSDC1_SRC_CLK		40
#define CLK_IFRAO_PCIE_TL_96M		41
#define CLK_IFRAO_PCIE_PL_PCLK_250M	42
#define CLK_IFRAO_DEVICE_APC		43
#define CLK_IFRAO_CCIF_AP		44
#define CLK_IFRAO_DEBUGSYS		45
#define CLK_IFRAO_AUDIO			46
#define CLK_IFRAO_CCIF_MD		47
#define CLK_IFRAO_DBG_TRACE		48
#define CLK_IFRAO_DEVMPU_BCLK		49
#define CLK_IFRAO_DRAMC_F26M		50
#define CLK_IFRAO_DISP_PWM		51
#define CLK_IFRAO_CLDMA_BCLK		52
#define CLK_IFRAO_AUDIO_26M_BCLK	53
#define CLK_IFRAO_MODEM_TEMP_SHARE	54
#define CLK_IFRAO_SPI1			55
#define CLK_IFRAO_I2C4			56
#define CLK_IFRAO_SPI2			57
#define CLK_IFRAO_SPI3			58
#define CLK_IFRAO_UNIPRO_TICK		59
#define CLK_IFRAO_UFS_MP_SAP_BCLK	60
#define CLK_IFRAO_MD32_BCLK		61
#define CLK_IFRAO_FPWRMCU		62
#define CLK_IFRAO_UNIPRO_MBIST		63
#define CLK_IFRAO_PWRMCU_BUS_HCLK	64
#define CLK_IFRAO_PWM6			65
#define CLK_IFRAO_PWM7			66
#define CLK_IFRAO_I2C_SLAVE		67
#define CLK_IFRAO_I2C1_ARBITER		68
#define CLK_IFRAO_I2C1_IMM		69
#define CLK_IFRAO_I2C2_ARBITER		70
#define CLK_IFRAO_I2C2_IMM		71
#define CLK_IFRAO_CQ_DMA		72
#define CLK_IFRAO_SSUSB_XHCI		73
#define CLK_IFRAO_MSDC0_SELF		74
#define CLK_IFRAO_MSDC1_SELF		75
#define CLK_IFRAO_MSDC2_SELF		76
#define CLK_IFRAO_SSPM_26M_SELF		77
#define CLK_IFRAO_SSPM_32K_SELF		78
#define CLK_IFRAO_I2C6			79
#define CLK_IFRAO_AP_MSDC0		80
#define CLK_IFRAO_MD_MSDC0		81
#define CLK_IFRAO_CCIF5_AP		82
#define CLK_IFRAO_CCIF5_MD		83
#define CLK_IFRAO_PCIE_TOP_HCLK_133M	84
#define CLK_IFRAO_SPIS_HCLK_66M		85
#define CLK_IFRAO_PCIE_PERI_26M		86
#define CLK_IFRAO_CCIF2_AP		87
#define CLK_IFRAO_CCIF2_MD		88
#define CLK_IFRAO_CCIF3_AP		89
#define CLK_IFRAO_CCIF3_MD		90
#define CLK_IFRAO_SEJ_F13M		91
#define CLK_IFRAO_AES			92
#define CLK_IFRAO_I2C7			93
#define CLK_IFRAO_I2C8			94
#define CLK_IFRAO_FBIST2FPC		95
#define CLK_IFRAO_DEVICE_APC_SYNC	96
#define CLK_IFRAO_DPMAIF_MAIN		97
#define CLK_IFRAO_PCIE_TL_32K		98
#define CLK_IFRAO_CCIF4_AP		99
#define CLK_IFRAO_CCIF4_MD		100
#define CLK_IFRAO_133M_MCLK_CK		101
#define CLK_IFRAO_66M_MCLK_CK		102
#define CLK_IFRAO_66M_PERI_BUS_MCLK_CK	103
#define CLK_IFRAO_INFRA_FREE_DCM_133M	104
#define CLK_IFRAO_INFRA_FREE_DCM_66M	105
#define CLK_IFRAO_PERU_BUS_DCM_133M	106
#define CLK_IFRAO_PERU_BUS_DCM_66M	107
#define CLK_IFRAO_RG_133M_CLDMA_TOP	108
#define CLK_IFRAO_RG_ECC_TOP		109
#define CLK_IFRAO_RG_66M_GCPU		110
#define CLK_IFRAO_RG_133M_DWC_ETHER	111
#define CLK_IFRAO_RG_133M_FLASHIF	112
#define CLK_IFRAO_RG_133M_PCIE_P0	113
#define CLK_IFRAO_RG_133M_PCIE_P1	114
#define CLK_IFRAO_RG_133M_PCIE_P2	115
#define CLK_IFRAO_RG_133M_PCIE_P3	116
#define CLK_IFRAO_RG_MMW_DPMAIF_TOP_CK	117
#define CLK_IFRAO_RG_NFI		118
#define CLK_IFRAO_RG_FPINFI_BCLK_CK	119
#define CLK_IFRAO_RG_66M_NFI_HCLK_CK	120
#define CLK_IFRAO_RG_FSPIS_CK		121
#define CLK_IFRAO_RG_PCIE_P1_PCLK_250M	122
#define CLK_IFRAO_RG_PCIE_P2_PCLK_250M	123
#define CLK_IFRAO_RG_PCIE_P3_PCLK_250M	124
#define CLK_IFRAO_RG_PCIE_PERI_26M_P1	125
#define CLK_IFRAO_RG_PCIE_PERI_26M_P2	126
#define CLK_IFRAO_RG_PCIE_PERI_26M_P3	127
#define CLK_IFRAO_RG_FLASHIF_PERI_26M	128
#define CLK_IFRAO_RG_FLASHIF_SFLASH	129
#define CLK_IFRAO_PERI_DCM_RG_FORCE	130

#define CLK_IFRAO_MSDC0_SRC_CLK		131
#define CLK_IFRAO_SSUSB			132
#define CLK_IFRAO_NR_CLK                133


/* PERICFG */

#define CLK_PERIAXI_DISABLE		0
#define CLK_PERI_NR_CLK			1

/* APMIXEDSYS */

#define CLK_APMIXED_ARMPLL_LL		0
#define CLK_APMIXED_CCIPLL		1
#define CLK_APMIXED_MPLL		2
#define CLK_APMIXED_MAINPLL		3
#define CLK_APMIXED_UNIVPLL		4
#define CLK_APMIXED_MSDCPLL		5
#define CLK_APMIXED_MMPLL		6
#define CLK_APMIXED_MFGPLL		7
#define CLK_APMIXED_APLL1		8
#define CLK_APMIXED_APLL2		9
#define CLK_APMIXED_NET1PLL		10
#define CLK_APMIXED_NET2PLL		11
#define CLK_APMIXED_WEDMCUPLL		12
#define CLK_APMIXED_MEDMCUPLL		13
#define CLK_APMIXED_SGMIIPLL		14
#define CLK_APMIXED_NR_CLK		15

/* GCE */

#define CLK_GCE_0			0
#define CLK_GCE_NR_CLK			1

/* AUDSYS */

#define CLK_AUDSYS_AFE			0
#define CLK_AUDSYS_22M			1
#define CLK_AUDSYS_24M			2
#define CLK_AUDSYS_APLL2_TUNER		3
#define CLK_AUDSYS_APLL_TUNER		4
#define CLK_AUDSYS_TDM			5
#define CLK_AUDSYS_ADC			6
#define CLK_AUDSYS_DAC			7
#define CLK_AUDSYS_DAC_PREDIS		8
#define CLK_AUDSYS_TML			9
#define CLK_AUDSYS_I2S0_BCLK		10
#define CLK_AUDSYS_I2S1_BCLK		11
#define CLK_AUDSYS_I2S2_BCLK		12
#define CLK_AUDSYS_I2S4_BCLK		13
#define CLK_AUDSYS_I2S5_BCLK		14
#define CLK_AUDSYS_I2S6_BCLK		15
#define CLK_AUDSYS_GENERAL1_ASRC	16
#define CLK_AUDSYS_GENERAL2_ASRC	17
#define CLK_AUDSYS_ADDA6_ADC		18
#define CLK_AUDSYS_CONNSYS_I2S_ASRC	19
#define CLK_AUDSYS_AFE_SRC_PCM_TX	20
#define CLK_AUDSYS_AFE_SRC_PCM_TX2	21
#define CLK_AUDSYS_AFE_SRC_PCM_TX3	22
#define CLK_AUDSYS_AFE_SRC_PCM_RX	23
#define CLK_AUDSYS_AFE_SRC_I2SIN	24
#define CLK_AUDSYS_AFE_SRC_I2SOUT	25
#define CLK_AUDSYS_NR_CLK		26

/* IMP_IIC_WRAP_E */

#define CLK_IMPE_AP_CLOCK_I2C0_RO	0
#define CLK_IMPE_AP_CLOCK_I2C1_RO	1
#define CLK_IMPE_AP_CLOCK_I2C2_RO	2
#define CLK_IMPE_AP_CLOCK_I2C3_RO	3
#define CLK_IMPE_AP_CLOCK_I2C4_RO	4
#define CLK_IMPE_AP_CLOCK_I2C5_RO	5
#define CLK_IMPE_NR_CLK			6

/* MFGSYS */

#define CLK_MFGCFG_BG3D			0
#define CLK_MFGCFG_NR_CLK		1

/* MMSYS_CONFIG */
#define CLK_MMSYS_MUTEX0		0
#define CLK_MMSYS_APB_BUS		1
#define CLK_MM_MDP_RSZ0			2
#define CLK_MM_DISP_GAMMA0		3
#define CLK_MM_MDP_WROT0		4
#define CLK_MM_DISP_COLOR0		5
#define CLK_MM_DISP_CCORR0		6
#define CLK_MM_DISP_AAL0		7
#define CLK_MM_DISP_RDMA0		8
#define CLK_MM_MDP_RDMA0		9
#define CLK_MMSYS_FAKE_ENG0		10
#define CLK_MM_DISP_DITHER0		11
#define CLK_MM_DISP_WDMA0		12
#define CLK_MM_MDP_TDSHP0		13
#define CLK_MM_DISP_OVL0		14
#define CLK_MM_DBPI0			15
#define CLK_MM_DISP_DSI0		16
#define CLK_MMSYS_SMI_COMMON		17
#define CLK_MM_NR_CLK			18

#endif /* _DT_BINDINGS_CLK_MT6880_H */