| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Atmel SFR (Special Function Registers) register offsets and bit definitions. |
| 3 | * |
| 4 | * Copyright (C) 2016 Atmel |
| 5 | * |
| 6 | * Author: Ludovic Desroches <ludovic.desroches@atmel.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H |
| 14 | #define _LINUX_MFD_SYSCON_ATMEL_SFR_H |
| 15 | |
| 16 | #define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ |
| 17 | /* 0x08 ~ 0x0c: Reserved */ |
| 18 | #define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ |
| 19 | #define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ |
| 20 | #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ |
| 21 | #define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ |
| 22 | |
| 23 | /* Field definitions */ |
| 24 | #define AT91_OHCIICR_SUSPEND_A BIT(8) |
| 25 | #define AT91_OHCIICR_SUSPEND_B BIT(9) |
| 26 | #define AT91_OHCIICR_SUSPEND_C BIT(10) |
| 27 | |
| 28 | #define AT91_OHCIICR_USB_SUSPEND (AT91_OHCIICR_SUSPEND_A | \ |
| 29 | AT91_OHCIICR_SUSPEND_B | \ |
| 30 | AT91_OHCIICR_SUSPEND_C) |
| 31 | |
| 32 | #define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) |
| 33 | |
| 34 | #endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */ |