blob: 462346233b1b5c96dc54629cdd42e2b5b8f5d5fc [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +08001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 */
5
6#ifndef _CPU_PMU_H_
7#define _CPU_PMU_H_
8
9#include <linux/device.h>
10#include <linux/perf_event.h>
11
12#define MODE_DISABLED 0
13#define MODE_INTERRUPT 1
14#define MODE_POLLING 2
15
16#define MXSIZE_PMU_DESC 32
17#define MXNR_CPU NR_CPUS
18
19#define MXNR_PMU_EVENTS 8 /* max number of pmu counter for armv8 is 6+1 */
20struct met_pmu {
21 unsigned char mode;
22 unsigned short event;
23 unsigned long freq;
24 struct kobject *kobj_cpu_pmu;
25};
26
27struct cpu_pmu_hw {
28 const char *name;
29 const char *cpu_name;
30 int nr_cnt;
31 int (*get_event_desc)(int idx, int event, char *event_desc);
32 int (*check_event)(struct met_pmu *pmu, int idx, int event);
33 void (*start)(struct met_pmu *pmu, int count);
34 void (*stop)(int count);
35 unsigned int (*polling)(struct met_pmu *pmu, int count, unsigned int *pmu_value);
36 unsigned long (*perf_event_get_evttype)(struct perf_event *ev);
37 u32 (*pmu_read_clear_overflow_flag)(void);
38 struct met_pmu *pmu[MXNR_CPU];
39 int event_count[MXNR_CPU];
40 /*
41 * used for compensation of pmu counter loss
42 * between end of polling and start of cpu pm
43 */
44 unsigned int cpu_pm_unpolled_loss[MXNR_CPU][MXNR_PMU_EVENTS];
45};
46
47struct pmu_desc {
48 unsigned int event;
49 char name[MXSIZE_PMU_DESC];
50};
51
52typedef enum {
53 SET_PMU_EVT_CNT = 0x0,
54 SET_PMU_CYCCNT_ENABLE = 0x1,
55 SET_PMU_BASE_OFFSET = 0x02
56} PMU_IPI_Type;
57
58struct cpu_pmu_hw *cpu_pmu_hw_init(void);
59
60extern struct cpu_pmu_hw *cpu_pmu;
61extern noinline void mp_cpu(unsigned char cnt, unsigned int *value);
62
63extern int met_perf_cpupmu_status;
64extern void met_perf_cpupmu_polling(unsigned long long stamp, int cpu);
65
66#endif /* _CPU_PMU_H_ */