blob: 8d63b7a933d88127c075a3693df15aaa205117bf [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs venc_cg_regs = {
16 .set_ofs = 0x0004,
17 .clr_ofs = 0x0008,
18 .sta_ofs = 0x0000,
19};
20
21#define GATE_VENC(_id, _name, _parent, _shift) \
22 GATE_VENC_FLAGS(_id, _name, _parent, _shift, 0)
23
24#define GATE_VENC_FLAGS(_id, _name, _parent, _shift, _flags) { \
25 .id = _id, \
26 .name = _name, \
27 .parent_name = _parent, \
28 .regs = &venc_cg_regs, \
29 .shift = _shift, \
30 .ops = &mtk_clk_gate_ops_setclr_inv, \
31 }
32
33static const struct mtk_gate venc_clks[] = {
34 GATE_VENC(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
35 GATE_VENC(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
36 GATE_VENC(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
37 GATE_VENC(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
38};
39
40static const struct of_device_id of_match_clk_mt6779_venc[] = {
41 { .compatible = "mediatek,mt6779-vencsys", },
42 {}
43};
44
45static int clk_mt6779_venc_probe(struct platform_device *pdev)
46{
47 struct clk_onecell_data *clk_data;
48 struct device_node *node = pdev->dev.of_node;
49
50 clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
51
52 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
53 clk_data);
54
55 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56}
57
58static struct platform_driver clk_mt6779_venc_drv = {
59 .probe = clk_mt6779_venc_probe,
60 .driver = {
61 .name = "clk-mt6779-venc",
62 .of_match_table = of_match_clk_mt6779_venc,
63 },
64};
65
66builtin_platform_driver(clk_mt6779_venc_drv);