| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 | 
|  | 2 |  | 
|  | 3 | /* | 
|  | 4 |  | 
|  | 5 | * Copyright (c) 2019 MediaTek Inc. | 
|  | 6 |  | 
|  | 7 | */ | 
|  | 8 |  | 
|  | 9 | #include <linux/clk-provider.h> | 
|  | 10 | #include <linux/platform_device.h> | 
|  | 11 |  | 
|  | 12 | #include "clk-mtk.h" | 
|  | 13 | #include "clk-gate.h" | 
|  | 14 |  | 
|  | 15 | #include <dt-bindings/clock/mt6880-clk.h> | 
|  | 16 |  | 
|  | 17 | #define MT_CLKMGR_MODULE_INIT	0 | 
|  | 18 |  | 
|  | 19 | #define MT_CCF_BRINGUP		1 | 
|  | 20 |  | 
|  | 21 | #define INV_OFS			-1 | 
|  | 22 |  | 
|  | 23 |  | 
|  | 24 |  | 
|  | 25 | static const struct mtk_gate_regs impe_cg_regs = { | 
|  | 26 | .set_ofs = 0xe00, | 
|  | 27 | .clr_ofs = 0xe00, | 
|  | 28 | .sta_ofs = 0xe00, | 
|  | 29 | }; | 
|  | 30 |  | 
|  | 31 | #define GATE_IMPE(_id, _name, _parent, _shift) {	\ | 
|  | 32 | .id = _id,				\ | 
|  | 33 | .name = _name,				\ | 
|  | 34 | .parent_name = _parent,			\ | 
|  | 35 | .regs = &impe_cg_regs,			\ | 
|  | 36 | .shift = _shift,			\ | 
|  | 37 | .ops = &mtk_clk_gate_ops_no_setclr,	\ | 
|  | 38 | } | 
|  | 39 |  | 
|  | 40 | static const struct mtk_gate impe_clks[] = { | 
|  | 41 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C0_RO, "impe_i2c0_ro", | 
|  | 42 | "i2c_ck"/* parent */, 0), | 
|  | 43 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C1_RO, "impe_i2c1_ro", | 
|  | 44 | "i2c_ck"/* parent */, 1), | 
|  | 45 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C2_RO, "impe_i2c2_ro", | 
|  | 46 | "i2c_ck"/* parent */, 2), | 
|  | 47 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C3_RO, "impe_i2c3_ro", | 
|  | 48 | "i2c_ck"/* parent */, 3), | 
|  | 49 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C4_RO, "impe_i2c4_ro", | 
|  | 50 | "i2c_ck"/* parent */, 4), | 
|  | 51 | GATE_IMPE(CLK_IMPE_AP_CLOCK_I2C5_RO, "impe_i2c5_ro", | 
|  | 52 | "i2c_ck"/* parent */, 5), | 
|  | 53 | }; | 
|  | 54 |  | 
|  | 55 | static int clk_mt6880_impe_probe(struct platform_device *pdev) | 
|  | 56 | { | 
|  | 57 | struct clk_onecell_data *clk_data; | 
|  | 58 | int r; | 
|  | 59 | struct device_node *node = pdev->dev.of_node; | 
|  | 60 |  | 
|  | 61 | #if MT_CCF_BRINGUP | 
|  | 62 | pr_notice("%s init begin\n", __func__); | 
|  | 63 | #endif | 
|  | 64 |  | 
|  | 65 | clk_data = mtk_alloc_clk_data(CLK_IMPE_NR_CLK); | 
|  | 66 |  | 
|  | 67 | mtk_clk_register_gates(node, impe_clks, ARRAY_SIZE(impe_clks), | 
|  | 68 | clk_data); | 
|  | 69 |  | 
|  | 70 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | 
|  | 71 |  | 
|  | 72 | if (r) | 
|  | 73 | pr_err("%s(): could not register clock provider: %d\n", | 
|  | 74 | __func__, r); | 
|  | 75 |  | 
|  | 76 | #if MT_CCF_BRINGUP | 
|  | 77 | pr_notice("%s init end\n", __func__); | 
|  | 78 | #endif | 
|  | 79 |  | 
|  | 80 | return r; | 
|  | 81 | } | 
|  | 82 |  | 
|  | 83 | static const struct of_device_id of_match_clk_mt6880_impe[] = { | 
|  | 84 | { .compatible = "mediatek,mt6880-imp_iic_wrap_e", }, | 
|  | 85 | {} | 
|  | 86 | }; | 
|  | 87 |  | 
|  | 88 | #if MT_CLKMGR_MODULE_INIT | 
|  | 89 |  | 
|  | 90 | static struct platform_driver clk_mt6880_impe_drv = { | 
|  | 91 | .probe = clk_mt6880_impe_probe, | 
|  | 92 | .driver = { | 
|  | 93 | .name = "clk-mt6880-impe", | 
|  | 94 | .of_match_table = of_match_clk_mt6880_impe, | 
|  | 95 | }, | 
|  | 96 | }; | 
|  | 97 |  | 
|  | 98 | builtin_platform_driver(clk_mt6880_impe_drv); | 
|  | 99 |  | 
|  | 100 | #else | 
|  | 101 |  | 
|  | 102 | static struct platform_driver clk_mt6880_impe_drv = { | 
|  | 103 | .probe = clk_mt6880_impe_probe, | 
|  | 104 | .driver = { | 
|  | 105 | .name = "clk-mt6880-impe", | 
|  | 106 | .of_match_table = of_match_clk_mt6880_impe, | 
|  | 107 | }, | 
|  | 108 | }; | 
|  | 109 | static int __init clk_mt6880_impe_platform_init(void) | 
|  | 110 | { | 
|  | 111 | return platform_driver_register(&clk_mt6880_impe_drv); | 
|  | 112 | } | 
|  | 113 | arch_initcall(clk_mt6880_impe_platform_init); | 
|  | 114 |  | 
|  | 115 | #endif	/* MT_CLKMGR_MODULE_INIT */ |