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192.168.1.100 / T800 / b04a402ae4328aad41335d93cebd3484973ab7c2 / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clkchk-mt2712.c
blob: e4976d52e3a7cd477635ea6f06bae056f45d4ef6 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 */
6
7#include <linux/module.h>
8#include "clkchk.h"
9
10static const char * const off_pll_names[] = {
11 "vcodecpll",
12 "vencpll",
13 "apll1",
14 "apll2",
15 "lvdspll",
16 "lvdspll2",
17 "msdcpll",
18 "msdcpll2",
19 "tvdpll",
20 "mmpll",
21 "armca72pll",
22 "etherpll",
23 NULL
24};
25
26static const char * const all_clk_names[] = {
27 /* plls */
28 "vcodecpll",
29 "vencpll",
30 "apll1",
31 "apll2",
32 "lvdspll",
33 "lvdspll2",
34 "msdcpll",
35 "msdcpll2",
36 "tvdpll",
37 "mmpll",
38 "armca72pll",
39 "etherpll",
40 "cvbspll",
41 /* topckgen */
42 "armca35pll_600m",
43 "armca35pll_400m",
44 "armca72pll_ck",
45 "syspll1_d4",
46 "syspll1_d8",
47 "syspll1_d16",
48 "syspll_d3",
49 "syspll2_d2",
50 "syspll2_d4",
51 "syspll_d5",
52 "syspll3_d2",
53 "syspll3_d4",
54 "syspll_d7",
55 "syspll4_d2",
56 "syspll4_d4",
57 "univpll_d7",
58 "univpll_d26",
59 "univpll_d52",
60 "univpll_d104",
61 "univpll_d208",
62 "univpll1_d2",
63 "univpll1_d4",
64 "univpll1_d8",
65 "univpll_d3",
66 "univpll2_d2",
67 "univpll2_d4",
68 "univpll2_d8",
69 "univpll_d5",
70 "univpll3_d2",
71 "univpll3_d4",
72 "univpll3_d8",
73 "f_mp0_pll1_ck",
74 "f_mp0_pll2_ck",
75 "f_big_pll1_ck",
76 "f_big_pll2_ck",
77 "f_bus_pll1_ck",
78 "f_bus_pll2_ck",
79 "apll1_ck",
80 "apll1_d2",
81 "apll1_d3",
82 "apll1_d4",
83 "apll1_d8",
84 "apll1_d16",
85 "apll2_ck",
86 "apll2_d2",
87 "apll2_d4",
88 "apll2_d8",
89 "apll2_d16",
90 "lvdspll_ck",
91 "lvdspll_d2",
92 "lvdspll_d4",
93 "lvdspll_d8",
94 "lvdspll2_ck",
95 "lvdspll2_d2",
96 "lvdspll2_d4",
97 "lvdspll2_d8",
98 "etherpll_125m",
99 "etherpll_50m",
100 "cvbs",
101 "cvbs_d2",
102 "sys_26m",
103 "mmpll_ck",
104 "mmpll_d2",
105 "vencpll_ck",
106 "vencpll_d2",
107 "vcodecpll_ck",
108 "vcodecpll_d2",
109 "tvdpll_ck",
110 "tvdpll_d2",
111 "tvdpll_d4",
112 "tvdpll_d8",
113 "tvdpll_429m",
114 "tvdpll_429m_d2",
115 "tvdpll_429m_d4",
116 "msdcpll_ck",
117 "msdcpll_d2",
118 "msdcpll_d4",
119 "msdcpll2_ck",
120 "msdcpll2_d2",
121 "msdcpll2_d4",
122 "clk26m_d2",
123 "d2a_ulclk_6p5m",
124 "vpll3_dpix",
125 "vpll_dpix",
126 "ltepll_fs26m",
127 "dmpll_ck",
128 "dsi0_lntc",
129 "dsi1_lntc",
130 "lvdstx3",
131 "lvdstx",
132 "clkrtc_ext",
133 "clkrtc_int",
134 "csi0",
135 "apll_div0",
136 "apll_div1",
137 "apll_div2",
138 "apll_div3",
139 "apll_div4",
140 "apll_div5",
141 "apll_div6",
142 "apll_div7",
143 "apll_div_pdn0",
144 "apll_div_pdn1",
145 "apll_div_pdn2",
146 "apll_div_pdn3",
147 "apll_div_pdn4",
148 "apll_div_pdn5",
149 "apll_div_pdn6",
150 "apll_div_pdn7",
151 "nfi2x_en",
152 "nfiecc_en",
153 "nfi1x_ck_en",
154 "mm_sel",
155 "pwm_sel",
156 "vdec_sel",
157 "venc_sel",
158 "mfg_sel",
159 "camtg_sel",
160 "spi_sel",
161 "usb20_sel",
162 "usb30_sel",
163 "msdc50_0_h_sel",
164 "msdc50_0_sel",
165 "msdc30_1_sel",
166 "msdc30_2_sel",
167 "msdc30_3_sel",
168 "audio_sel",
169 "aud_intbus_sel",
170 "pmicspi_sel",
171 "dpilvds1_sel",
172 "atb_sel",
173 "nr_sel",
174 "nfi2x_sel",
175 "irda_sel",
176 "aud_1_sel",
177 "aud_2_sel",
178 "mem_mfg_sel",
179 "axi_mfg_sel",
180 "scam_sel",
181 "nfiecc_sel",
182 "pe2_mac_p0_sel",
183 "pe2_mac_p1_sel",
184 "dpilvds_sel",
185 "msdc50_3_h_sel",
186 "hdcp_sel",
187 "hdcp_24m_sel",
188 "spinor_sel",
189 "apll_sel",
190 "apll2_sel",
191 "a1sys_hp_sel",
192 "a2sys_hp_sel",
193 "asm_l_sel",
194 "asm_m_sel",
195 "asm_h_sel",
196 "i2so1_sel",
197 "i2so2_sel",
198 "i2so3_sel",
199 "tdmo0_sel",
200 "tdmo1_sel",
201 "i2si1_sel",
202 "i2si2_sel",
203 "i2si3_sel",
204 "ether_125m_sel",
205 "ether_50m_sel",
206 "jpgdec_sel",
207 "spislv_sel",
208 "ether_sel",
209 "cam2tg_sel",
210 "di_sel",
211 "tvd_sel",
212 "i2c_sel",
213 "pwm_infra_sel",
214 "msdc0p_aes_sel",
215 "cmsys_sel",
216 "gcpu_sel",
217 "aud_apll1_sel",
218 "aud_apll2_sel",
219 "apll1_ref_sel",
220 "apll2_ref_sel",
221 "audull_vtx_sel",
222 /* bdpsys */
223 "bdp_bridge_b",
224 "bdp_bridge_d",
225 "bdp_larb_d",
226 "bdp_vdi_pxl",
227 "bdp_vdi_d",
228 "bdp_vdi_b",
229 "bdp_fmt_b",
230 "bdp_27m",
231 "bdp_27m_vdout",
232 "bdp_27_74_74",
233 "bdp_2fs",
234 "bdp_2fs74_148",
235 "bdp_b",
236 "bdp_vdo_d",
237 "bdp_vdo_2fs",
238 "bdp_vdo_b",
239 "bdp_di_pxl",
240 "bdp_di_d",
241 "bdp_di_b",
242 "bdp_nr_agent",
243 "bdp_nr_d",
244 "bdp_nr_b",
245 "bdp_bridge_rt_b",
246 "bdp_bridge_rt_d",
247 "bdp_larb_rt_d",
248 "bdp_tvd_tdc",
249 "bdp_tvd_clk_54",
250 "bdp_tvd_cbus",
251 /* infracfg */
252 "infra_dbgclk",
253 "infra_gce",
254 "infra_m4u",
255 "infra_kp",
256 "infra_ao_spi0",
257 "infra_ao_spi1",
258 "infra_ao_uart5",
259 /* imgsys */
260 "img_smi_larb2",
261 "img_scam_en",
262 "img_cam_en",
263 "img_cam_sv_en",
264 "img_cam_sv1_en",
265 "img_cam_sv2_en",
266 /* jpgdecsys */
267 "jpgdec_jpgdec1",
268 "jpgdec_jpgdec",
269 /* mfgcfg */
270 "mfg_bg3d",
271 /* mmsys */
272 "mm_smi_common",
273 "mm_smi_larb0",
274 "mm_cam_mdp",
275 "mm_mdp_rdma0",
276 "mm_mdp_rdma1",
277 "mm_mdp_rsz0",
278 "mm_mdp_rsz1",
279 "mm_mdp_rsz2",
280 "mm_mdp_tdshp0",
281 "mm_mdp_tdshp1",
282 "mm_mdp_crop",
283 "mm_mdp_wdma",
284 "mm_mdp_wrot0",
285 "mm_mdp_wrot1",
286 "mm_fake_eng",
287 "mm_mutex_32k",
288 "mm_disp_ovl0",
289 "mm_disp_ovl1",
290 "mm_disp_rdma0",
291 "mm_disp_rdma1",
292 "mm_disp_rdma2",
293 "mm_disp_wdma0",
294 "mm_disp_wdma1",
295 "mm_disp_color0",
296 "mm_disp_color1",
297 "mm_disp_aal",
298 "mm_disp_gamma",
299 "mm_disp_ufoe",
300 "mm_disp_split0",
301 "mm_disp_od",
302 "mm_pwm0_mm",
303 "mm_pwm0_26m",
304 "mm_pwm1_mm",
305 "mm_pwm1_26m",
306 "mm_dsi0_engine",
307 "mm_dsi0_digital",
308 "mm_dsi1_engine",
309 "mm_dsi1_digital",
310 "mm_dpi_pixel",
311 "mm_dpi_engine",
312 "mm_dpi1_pixel",
313 "mm_dpi1_engine",
314 "mm_lvds_pixel",
315 "mm_lvds_cts",
316 "mm_smi_larb4",
317 "mm_smi_common1",
318 "mm_smi_larb5",
319 "mm_mdp_rdma2",
320 "mm_mdp_tdshp2",
321 "mm_disp_ovl2",
322 "mm_disp_wdma2",
323 "mm_disp_color2",
324 "mm_disp_aal1",
325 "mm_disp_od1",
326 "mm_lvds1_pixel",
327 "mm_lvds1_cts",
328 "mm_smi_larb7",
329 "mm_mdp_rdma3",
330 "mm_mdp_wrot2",
331 "mm_dsi2",
332 "mm_dsi2_digital",
333 "mm_dsi3",
334 "mm_dsi3_digital",
335 /* pericfg */
336 "per_nfi",
337 "per_therm",
338 "per_pwm0",
339 "per_pwm1",
340 "per_pwm2",
341 "per_pwm3",
342 "per_pwm4",
343 "per_pwm5",
344 "per_pwm6",
345 "per_pwm7",
346 "per_pwm",
347 "per_ap_dma",
348 "per_msdc30_0",
349 "per_msdc30_1",
350 "per_msdc30_2",
351 "per_msdc30_3",
352 "per_uart1",
353 "per_uart2",
354 "per_uart3",
355 "per_i2c0",
356 "per_i2c1",
357 "per_i2c2",
358 "per_i2c3",
359 "per_i2c4",
360 "per_auxadc",
361 "per_spi0",
362 "per_spi",
363 "per_i2c5",
364 "per_spi2",
365 "per_spi3",
366 "per_spi5",
367 "per_uart4",
368 "per_sflash",
369 "per_gmac",
370 "per_pcie0",
371 "per_pcie1",
372 "per_gmac_pclk",
373 "per_msdc50_0_en",
374 "per_msdc30_1_en",
375 "per_msdc30_2_en",
376 "per_msdc30_3_en",
377 "per_msdc50_0_h",
378 "per_msdc50_3_h",
379 "per_msdc30_0_q",
380 "per_msdc30_3_q",
381 /* vdecsys */
382 "vdec_cken",
383 "vdec_larb1_cken",
384 "vdec_imgrz_cken",
385 /* vencsys */
386 "venc_smi",
387 "venc_venc",
388 "venc_smi_larb6",
389 /* end */
390 NULL
391};
392
393static const char * const compatible[] = {"mediatek,mt2712", NULL};
394
395static struct clkchk_cfg_t cfg = {
396 .aee_excp_on_fail = false,
397 .warn_on_fail = true,
398 .compatible = compatible,
399 .off_pll_names = off_pll_names,
400 .all_clk_names = all_clk_names,
401};
402
403static int __init clkchk_platform_init(void)
404{
405 return clkchk_init(&cfg);
406}
407subsys_initcall(clkchk_platform_init);