| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | /* |
| 4 | |
| 5 | * Copyright (c) 2019 MediaTek Inc. |
| 6 | |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk-provider.h> |
| 10 | |
| 11 | #include <dt-bindings/power/mt6890-power.h> |
| 12 | |
| 13 | #define TAG "[scpchk] " |
| 14 | #define BUG_ON_CHK_ENABLE 0 |
| 15 | |
| 16 | /* |
| 17 | * The clk names in Mediatek CCF. |
| 18 | */ |
| 19 | /* audiosys */ |
| 20 | struct scpsys_check_swcg audiosys_swcgs[] = { |
| 21 | SWCG("aud_afe"), |
| 22 | SWCG("aud_22m"), |
| 23 | SWCG("aud_24m"), |
| 24 | SWCG("aud_apll2_tuner"), |
| 25 | SWCG("aud_apll_tuner"), |
| 26 | SWCG("aud_tdm_ck"), |
| 27 | SWCG("aud_adc"), |
| 28 | SWCG("aud_dac"), |
| 29 | SWCG("aud_dac_predis"), |
| 30 | SWCG("aud_tml"), |
| 31 | SWCG("aud_i2s0_bclk"), |
| 32 | SWCG("aud_i2s1_bclk"), |
| 33 | SWCG("aud_i2s2_bclk"), |
| 34 | SWCG("aud_i2s4_bclk"), |
| 35 | SWCG("aud_i2s5_bclk"), |
| 36 | SWCG("aud_i2s6_bclk"), |
| 37 | SWCG("aud_general1_asrc"), |
| 38 | SWCG("aud_general2_asrc"), |
| 39 | SWCG("aud_adda6_adc"), |
| 40 | SWCG("aud_connsys_i2s_asrc"), |
| 41 | SWCG("aud_afe_src_pcm_tx"), |
| 42 | SWCG("aud_afe_src_pcm_tx2"), |
| 43 | SWCG("aud_afe_src_pcm_tx3"), |
| 44 | SWCG("aud_afe_src_pcm_rx"), |
| 45 | SWCG("aud_afe_src_i2sin"), |
| 46 | SWCG("aud_afe_src_i2sout"), |
| 47 | SWCG(NULL), |
| 48 | }; |
| 49 | /* mfgsys */ |
| 50 | struct scpsys_check_swcg mfgsys_swcgs[] = { |
| 51 | SWCG("mfgcfg_bg3d"), |
| 52 | SWCG(NULL), |
| 53 | }; |
| 54 | |
| 55 | struct subsys_cgs_check mtk_subsys_check[] = { |
| 56 | {MT6890_POWER_DOMAIN_AUDIO, audiosys_swcgs}, |
| 57 | }; |
| 58 | |
| 59 | static unsigned int check_cg_state(struct scpsys_check_swcg *swcg) |
| 60 | { |
| 61 | int enable_count = 0; |
| 62 | |
| 63 | if (!swcg) |
| 64 | return 0; |
| 65 | |
| 66 | while (swcg->name) { |
| 67 | if (!IS_ERR_OR_NULL(swcg->c)) { |
| 68 | if (__clk_get_enable_count(swcg->c) > 0) { |
| 69 | pr_notice("%s[%-17s: %3d]\n", |
| 70 | __func__, |
| 71 | __clk_get_name(swcg->c), |
| 72 | __clk_get_enable_count(swcg->c)); |
| 73 | enable_count++; |
| 74 | } |
| 75 | } |
| 76 | swcg++; |
| 77 | } |
| 78 | |
| 79 | return enable_count; |
| 80 | } |
| 81 | |
| 82 | void mtk_check_subsys_swcg(enum subsys_id id) |
| 83 | { |
| 84 | int i; |
| 85 | unsigned int ret = 0; |
| 86 | |
| 87 | for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++) { |
| 88 | if (mtk_subsys_check[i].id != id) |
| 89 | continue; |
| 90 | |
| 91 | /* check if Subsys CGs are still on */ |
| 92 | ret = check_cg_state(mtk_subsys_check[i].swcgs); |
| 93 | if (ret) |
| 94 | pr_notice("%s:(%d) warning!\n", __func__, id); |
| 95 | } |
| 96 | |
| 97 | if (ret) { |
| 98 | pr_err("%s(%d): %d\n", __func__, id, ret); |
| 99 | #if BUG_ON_CHK_ENABLE |
| 100 | BUG_ON(1); |
| 101 | #endif |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | static void __init scpsys_check_swcg_init_common(struct scpsys_check_swcg *swcg) |
| 106 | { |
| 107 | if (!swcg) |
| 108 | return; |
| 109 | |
| 110 | while (swcg->name) { |
| 111 | struct clk *c = __clk_lookup(swcg->name); |
| 112 | |
| 113 | if (IS_ERR_OR_NULL(c)) |
| 114 | pr_notice("[%17s: NULL]\n", swcg->name); |
| 115 | else |
| 116 | swcg->c = c; |
| 117 | swcg++; |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | static int __init scpchk_init(void) |
| 122 | { |
| 123 | /* fill the 'struct clk *' ptr of every CGs*/ |
| 124 | int i; |
| 125 | |
| 126 | if (!of_machine_is_compatible("mediatek,MT6890")) |
| 127 | return -ENODEV; |
| 128 | |
| 129 | for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++) |
| 130 | scpsys_check_swcg_init_common(mtk_subsys_check[i].swcgs); |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | subsys_initcall(scpchk_init); |