| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 | 
|  | 2 | /* | 
|  | 3 | * Renesas R-Car V3H System Controller | 
|  | 4 | * | 
|  | 5 | * Copyright (C) 2018 Renesas Electronics Corp. | 
|  | 6 | * Copyright (C) 2018 Cogent Embedded, Inc. | 
|  | 7 | */ | 
|  | 8 |  | 
|  | 9 | #include <linux/bug.h> | 
|  | 10 | #include <linux/kernel.h> | 
|  | 11 |  | 
|  | 12 | #include <dt-bindings/power/r8a77980-sysc.h> | 
|  | 13 |  | 
|  | 14 | #include "rcar-sysc.h" | 
|  | 15 |  | 
|  | 16 | static const struct rcar_sysc_area r8a77980_areas[] __initconst = { | 
|  | 17 | { "always-on",	    0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON }, | 
|  | 18 | { "ca53-scu",	0x140, 0, R8A77980_PD_CA53_SCU,	R8A77980_PD_ALWAYS_ON, | 
|  | 19 | PD_SCU }, | 
|  | 20 | { "ca53-cpu0",	0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU, | 
|  | 21 | PD_CPU_NOCR }, | 
|  | 22 | { "ca53-cpu1",	0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU, | 
|  | 23 | PD_CPU_NOCR }, | 
|  | 24 | { "ca53-cpu2",	0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU, | 
|  | 25 | PD_CPU_NOCR }, | 
|  | 26 | { "ca53-cpu3",	0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU, | 
|  | 27 | PD_CPU_NOCR }, | 
|  | 28 | { "cr7",	0x240, 0, R8A77980_PD_CR7,	R8A77980_PD_ALWAYS_ON }, | 
|  | 29 | { "a3ir",	0x180, 0, R8A77980_PD_A3IR,	R8A77980_PD_ALWAYS_ON }, | 
|  | 30 | { "a2ir0",	0x400, 0, R8A77980_PD_A2IR0,	R8A77980_PD_A3IR }, | 
|  | 31 | { "a2ir1",	0x400, 1, R8A77980_PD_A2IR1,	R8A77980_PD_A3IR }, | 
|  | 32 | { "a2ir2",	0x400, 2, R8A77980_PD_A2IR2,	R8A77980_PD_A3IR }, | 
|  | 33 | { "a2ir3",	0x400, 3, R8A77980_PD_A2IR3,	R8A77980_PD_A3IR }, | 
|  | 34 | { "a2ir4",	0x400, 4, R8A77980_PD_A2IR4,	R8A77980_PD_A3IR }, | 
|  | 35 | { "a2ir5",	0x400, 5, R8A77980_PD_A2IR5,	R8A77980_PD_A3IR }, | 
|  | 36 | { "a2sc0",	0x400, 6, R8A77980_PD_A2SC0,	R8A77980_PD_A3IR }, | 
|  | 37 | { "a2sc1",	0x400, 7, R8A77980_PD_A2SC1,	R8A77980_PD_A3IR }, | 
|  | 38 | { "a2sc2",	0x400, 8, R8A77980_PD_A2SC2,	R8A77980_PD_A3IR }, | 
|  | 39 | { "a2sc3",	0x400, 9, R8A77980_PD_A2SC3,	R8A77980_PD_A3IR }, | 
|  | 40 | { "a2sc4",	0x400, 10, R8A77980_PD_A2SC4,	R8A77980_PD_A3IR }, | 
|  | 41 | { "a2dp0",	0x400, 11, R8A77980_PD_A2DP0,	R8A77980_PD_A3IR }, | 
|  | 42 | { "a2dp1",	0x400, 12, R8A77980_PD_A2DP1,	R8A77980_PD_A3IR }, | 
|  | 43 | { "a2cn",	0x400, 13, R8A77980_PD_A2CN,	R8A77980_PD_A3IR }, | 
|  | 44 | { "a3vip0",	0x2c0, 0, R8A77980_PD_A3VIP0,	R8A77980_PD_ALWAYS_ON }, | 
|  | 45 | { "a3vip1",	0x300, 0, R8A77980_PD_A3VIP1,	R8A77980_PD_ALWAYS_ON }, | 
|  | 46 | { "a3vip2",	0x280, 0, R8A77980_PD_A3VIP2,	R8A77980_PD_ALWAYS_ON }, | 
|  | 47 | }; | 
|  | 48 |  | 
|  | 49 | const struct rcar_sysc_info r8a77980_sysc_info __initconst = { | 
|  | 50 | .areas = r8a77980_areas, | 
|  | 51 | .num_areas = ARRAY_SIZE(r8a77980_areas), | 
|  | 52 | }; |