| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 BayLibre, SAS. |
| 4 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _MESON_AXG_FIFO_H |
| 8 | #define _MESON_AXG_FIFO_H |
| 9 | |
| 10 | struct clk; |
| 11 | struct platform_device; |
| 12 | struct regmap; |
| 13 | struct reset_control; |
| 14 | |
| 15 | struct snd_soc_component_driver; |
| 16 | struct snd_soc_dai; |
| 17 | struct snd_soc_dai_driver; |
| 18 | struct snd_pcm_ops; |
| 19 | struct snd_soc_pcm_runtime; |
| 20 | |
| 21 | #define AXG_FIFO_CH_MAX 128 |
| 22 | #define AXG_FIFO_RATES (SNDRV_PCM_RATE_5512 | \ |
| 23 | SNDRV_PCM_RATE_8000_192000) |
| 24 | #define AXG_FIFO_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ |
| 25 | SNDRV_PCM_FMTBIT_S16_LE | \ |
| 26 | SNDRV_PCM_FMTBIT_S20_LE | \ |
| 27 | SNDRV_PCM_FMTBIT_S24_LE | \ |
| 28 | SNDRV_PCM_FMTBIT_S32_LE) |
| 29 | |
| 30 | #define AXG_FIFO_BURST 8 |
| 31 | #define AXG_FIFO_MIN_CNT 64 |
| 32 | #define AXG_FIFO_MIN_DEPTH (AXG_FIFO_BURST * AXG_FIFO_MIN_CNT) |
| 33 | |
| 34 | #define FIFO_INT_ADDR_FINISH BIT(0) |
| 35 | #define FIFO_INT_ADDR_INT BIT(1) |
| 36 | #define FIFO_INT_COUNT_REPEAT BIT(2) |
| 37 | #define FIFO_INT_COUNT_ONCE BIT(3) |
| 38 | #define FIFO_INT_FIFO_ZERO BIT(4) |
| 39 | #define FIFO_INT_FIFO_DEPTH BIT(5) |
| 40 | #define FIFO_INT_MASK GENMASK(7, 0) |
| 41 | |
| 42 | #define FIFO_CTRL0 0x00 |
| 43 | #define CTRL0_DMA_EN BIT(31) |
| 44 | #define CTRL0_INT_EN(x) ((x) << 16) |
| 45 | #define CTRL0_SEL_MASK GENMASK(2, 0) |
| 46 | #define CTRL0_SEL_SHIFT 0 |
| 47 | #define FIFO_CTRL1 0x04 |
| 48 | #define CTRL1_INT_CLR(x) ((x) << 0) |
| 49 | #define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8) |
| 50 | #define CTRL1_STATUS2_SEL(x) ((x) << 8) |
| 51 | #define STATUS2_SEL_DDR_READ 0 |
| 52 | #define CTRL1_THRESHOLD_MASK GENMASK(23, 16) |
| 53 | #define CTRL1_THRESHOLD(x) ((x) << 16) |
| 54 | #define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24) |
| 55 | #define CTRL1_FRDDR_DEPTH(x) ((x) << 24) |
| 56 | #define FIFO_START_ADDR 0x08 |
| 57 | #define FIFO_FINISH_ADDR 0x0c |
| 58 | #define FIFO_INT_ADDR 0x10 |
| 59 | #define FIFO_STATUS1 0x14 |
| 60 | #define STATUS1_INT_STS(x) ((x) << 0) |
| 61 | #define FIFO_STATUS2 0x18 |
| 62 | |
| 63 | struct axg_fifo { |
| 64 | struct regmap *map; |
| 65 | struct clk *pclk; |
| 66 | struct reset_control *arb; |
| 67 | int irq; |
| 68 | }; |
| 69 | |
| 70 | struct axg_fifo_match_data { |
| 71 | const struct snd_soc_component_driver *component_drv; |
| 72 | struct snd_soc_dai_driver *dai_drv; |
| 73 | }; |
| 74 | |
| 75 | extern const struct snd_pcm_ops axg_fifo_pcm_ops; |
| 76 | |
| 77 | int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type); |
| 78 | int axg_fifo_probe(struct platform_device *pdev); |
| 79 | |
| 80 | #endif /* _MESON_AXG_FIFO_H */ |