| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Common address map definitions |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_MACH_ADDR_MAP_H |
| 10 | #define __ASM_MACH_ADDR_MAP_H |
| 11 | |
| 12 | /* APB - Application Subsystem Peripheral Bus |
| 13 | * |
| 14 | * NOTE: the DMA controller registers are actually on the AXI fabric #1 |
| 15 | * slave port to AHB/APB bridge, due to its close relationship to those |
| 16 | * peripherals on APB, let's count it into the ABP mapping area. |
| 17 | */ |
| 18 | #define APB_PHYS_BASE 0xd4000000 |
| 19 | #define APB_VIRT_BASE IOMEM(0xfe000000) |
| 20 | #define APB_PHYS_SIZE 0x00200000 |
| 21 | |
| 22 | #define AXI_PHYS_BASE 0xd4200000 |
| 23 | #define AXI_VIRT_BASE IOMEM(0xfe200000) |
| 24 | #define AXI_PHYS_SIZE 0x00200000 |
| 25 | |
| 26 | /* Static Memory Controller - Chip Select 0 and 1 */ |
| 27 | #define SMC_CS0_PHYS_BASE 0x80000000 |
| 28 | #define SMC_CS0_PHYS_SIZE 0x10000000 |
| 29 | #define SMC_CS1_PHYS_BASE 0x90000000 |
| 30 | #define SMC_CS1_PHYS_SIZE 0x10000000 |
| 31 | |
| 32 | #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) |
| 33 | #define APMU_REG(x) (APMU_VIRT_BASE + (x)) |
| 34 | |
| 35 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) |
| 36 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) |
| 37 | |
| 38 | #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) |
| 39 | #define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) |
| 40 | |
| 41 | #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) |
| 42 | #define CIU_REG(x) (CIU_VIRT_BASE + (x)) |
| 43 | |
| 44 | #endif /* __ASM_MACH_ADDR_MAP_H */ |