| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ |
| 5 | * |
| 6 | * S5PV210 - Clock register definitions |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_ARCH_REGS_CLOCK_H |
| 10 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ |
| 11 | |
| 12 | #include <plat/map-base.h> |
| 13 | |
| 14 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) |
| 15 | |
| 16 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) |
| 17 | #define S5P_MPLL_LOCK S5P_CLKREG(0x08) |
| 18 | #define S5P_EPLL_LOCK S5P_CLKREG(0x10) |
| 19 | #define S5P_VPLL_LOCK S5P_CLKREG(0x20) |
| 20 | |
| 21 | #define S5P_APLL_CON S5P_CLKREG(0x100) |
| 22 | #define S5P_MPLL_CON S5P_CLKREG(0x108) |
| 23 | #define S5P_EPLL_CON S5P_CLKREG(0x110) |
| 24 | #define S5P_EPLL_CON1 S5P_CLKREG(0x114) |
| 25 | #define S5P_VPLL_CON S5P_CLKREG(0x120) |
| 26 | |
| 27 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) |
| 28 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) |
| 29 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) |
| 30 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) |
| 31 | #define S5P_CLK_SRC4 S5P_CLKREG(0x210) |
| 32 | #define S5P_CLK_SRC5 S5P_CLKREG(0x214) |
| 33 | #define S5P_CLK_SRC6 S5P_CLKREG(0x218) |
| 34 | |
| 35 | #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) |
| 36 | #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) |
| 37 | |
| 38 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) |
| 39 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) |
| 40 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) |
| 41 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) |
| 42 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) |
| 43 | #define S5P_CLK_DIV5 S5P_CLKREG(0x314) |
| 44 | #define S5P_CLK_DIV6 S5P_CLKREG(0x318) |
| 45 | #define S5P_CLK_DIV7 S5P_CLKREG(0x31C) |
| 46 | |
| 47 | #define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400) |
| 48 | #define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404) |
| 49 | #define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408) |
| 50 | |
| 51 | #define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420) |
| 52 | #define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424) |
| 53 | |
| 54 | #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440) |
| 55 | #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444) |
| 56 | #define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) |
| 57 | #define S5P_CLKGATE_IP1 S5P_CLKREG(0x464) |
| 58 | #define S5P_CLKGATE_IP2 S5P_CLKREG(0x468) |
| 59 | #define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) |
| 60 | #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) |
| 61 | |
| 62 | #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) |
| 63 | #define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) |
| 64 | #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) |
| 65 | #define S5P_CLK_OUT S5P_CLKREG(0x500) |
| 66 | |
| 67 | /* DIV/MUX STATUS */ |
| 68 | #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) |
| 69 | #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) |
| 70 | #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) |
| 71 | #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) |
| 72 | |
| 73 | /* CLKSRC0 */ |
| 74 | #define S5P_CLKSRC0_MUX200_SHIFT (16) |
| 75 | #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) |
| 76 | #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) |
| 77 | #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) |
| 78 | |
| 79 | /* CLKSRC2 */ |
| 80 | #define S5P_CLKSRC2_G3D_SHIFT (0) |
| 81 | #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) |
| 82 | #define S5P_CLKSRC2_MFC_SHIFT (4) |
| 83 | #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) |
| 84 | |
| 85 | /* CLKSRC6*/ |
| 86 | #define S5P_CLKSRC6_ONEDRAM_SHIFT (24) |
| 87 | #define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) |
| 88 | |
| 89 | /* CLKDIV0 */ |
| 90 | #define S5P_CLKDIV0_APLL_SHIFT (0) |
| 91 | #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) |
| 92 | #define S5P_CLKDIV0_A2M_SHIFT (4) |
| 93 | #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) |
| 94 | #define S5P_CLKDIV0_HCLK200_SHIFT (8) |
| 95 | #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) |
| 96 | #define S5P_CLKDIV0_PCLK100_SHIFT (12) |
| 97 | #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) |
| 98 | #define S5P_CLKDIV0_HCLK166_SHIFT (16) |
| 99 | #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) |
| 100 | #define S5P_CLKDIV0_PCLK83_SHIFT (20) |
| 101 | #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) |
| 102 | #define S5P_CLKDIV0_HCLK133_SHIFT (24) |
| 103 | #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) |
| 104 | #define S5P_CLKDIV0_PCLK66_SHIFT (28) |
| 105 | #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) |
| 106 | |
| 107 | /* CLKDIV2 */ |
| 108 | #define S5P_CLKDIV2_G3D_SHIFT (0) |
| 109 | #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) |
| 110 | #define S5P_CLKDIV2_MFC_SHIFT (4) |
| 111 | #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) |
| 112 | |
| 113 | /* CLKDIV6 */ |
| 114 | #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) |
| 115 | #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) |
| 116 | |
| 117 | #define S5P_SWRESET S5P_CLKREG(0x2000) |
| 118 | |
| 119 | #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) |
| 120 | |
| 121 | /* Registers related to power management */ |
| 122 | #define S5P_PWR_CFG S5P_CLKREG(0xC000) |
| 123 | #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) |
| 124 | #define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) |
| 125 | #define S5P_PWR_MODE S5P_CLKREG(0xC00C) |
| 126 | #define S5P_NORMAL_CFG S5P_CLKREG(0xC010) |
| 127 | #define S5P_IDLE_CFG S5P_CLKREG(0xC020) |
| 128 | #define S5P_STOP_CFG S5P_CLKREG(0xC030) |
| 129 | #define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034) |
| 130 | #define S5P_SLEEP_CFG S5P_CLKREG(0xC040) |
| 131 | |
| 132 | #define S5P_OSC_FREQ S5P_CLKREG(0xC100) |
| 133 | #define S5P_OSC_STABLE S5P_CLKREG(0xC104) |
| 134 | #define S5P_PWR_STABLE S5P_CLKREG(0xC108) |
| 135 | #define S5P_MTC_STABLE S5P_CLKREG(0xC110) |
| 136 | #define S5P_CLAMP_STABLE S5P_CLKREG(0xC114) |
| 137 | |
| 138 | #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) |
| 139 | #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) |
| 140 | |
| 141 | #define S5P_OTHERS S5P_CLKREG(0xE000) |
| 142 | #define S5P_OM_STAT S5P_CLKREG(0xE100) |
| 143 | #define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) |
| 144 | #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) |
| 145 | #define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) |
| 146 | |
| 147 | #define S5P_INFORM0 S5P_CLKREG(0xF000) |
| 148 | #define S5P_INFORM1 S5P_CLKREG(0xF004) |
| 149 | #define S5P_INFORM2 S5P_CLKREG(0xF008) |
| 150 | #define S5P_INFORM3 S5P_CLKREG(0xF00C) |
| 151 | #define S5P_INFORM4 S5P_CLKREG(0xF010) |
| 152 | #define S5P_INFORM5 S5P_CLKREG(0xF014) |
| 153 | #define S5P_INFORM6 S5P_CLKREG(0xF018) |
| 154 | #define S5P_INFORM7 S5P_CLKREG(0xF01C) |
| 155 | |
| 156 | #define S5P_RST_STAT S5P_CLKREG(0xA000) |
| 157 | #define S5P_OSC_CON S5P_CLKREG(0x8000) |
| 158 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) |
| 159 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) |
| 160 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) |
| 161 | |
| 162 | #define S5P_IDLE_CFG_TL_MASK (3 << 30) |
| 163 | #define S5P_IDLE_CFG_TM_MASK (3 << 28) |
| 164 | #define S5P_IDLE_CFG_TL_ON (2 << 30) |
| 165 | #define S5P_IDLE_CFG_TM_ON (2 << 28) |
| 166 | #define S5P_IDLE_CFG_DIDLE (1 << 0) |
| 167 | |
| 168 | #define S5P_CFG_WFI_CLEAN (~(3 << 8)) |
| 169 | #define S5P_CFG_WFI_IDLE (1 << 8) |
| 170 | #define S5P_CFG_WFI_STOP (2 << 8) |
| 171 | #define S5P_CFG_WFI_SLEEP (3 << 8) |
| 172 | |
| 173 | #define S5P_OTHER_SYS_INT 24 |
| 174 | #define S5P_OTHER_STA_TYPE 23 |
| 175 | #define S5P_OTHER_SYSC_INTOFF (1 << 0) |
| 176 | #define STA_TYPE_EXPON 0 |
| 177 | #define STA_TYPE_SFR 1 |
| 178 | |
| 179 | #define S5P_PWR_STA_EXP_SCALE 0 |
| 180 | #define S5P_PWR_STA_CNT 4 |
| 181 | |
| 182 | #define S5P_PWR_STABLE_COUNT 85500 |
| 183 | |
| 184 | #define S5P_SLEEP_CFG_OSC_EN (1 << 0) |
| 185 | #define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) |
| 186 | |
| 187 | /* OTHERS Resgister */ |
| 188 | #define S5P_OTHERS_USB_SIG_MASK (1 << 16) |
| 189 | |
| 190 | /* S5P_DAC_CONTROL */ |
| 191 | #define S5P_DAC_ENABLE (1) |
| 192 | #define S5P_DAC_DISABLE (0) |
| 193 | |
| 194 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |