Gitiles
Code Review Sign In
192.168.1.100 / T800 / b29aec358f22d21c6e54decdbdc53c0e8aa7c76b / . / src / kernel / linux / v4.19 / arch / mips / ralink / rt305x.c
blob: 93d472c60ce467cfc4da3c8d72cef8a7fd9bc45d [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <john@phrozen.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/bug.h>
16
17#include <asm/io.h>
18#include <asm/mipsregs.h>
19#include <asm/mach-ralink/ralink_regs.h>
20#include <asm/mach-ralink/rt305x.h>
21#include <asm/mach-ralink/pinmux.h>
22
23#include "common.h"
24
25static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
26static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
27static struct rt2880_pmx_func uartf_func[] = {
28 FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
29 FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
30 FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
31 FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
32 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
33 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
34 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
35};
36static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
37static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
38static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
39static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
40static struct rt2880_pmx_func rt5350_cs1_func[] = {
41 FUNC("spi_cs1", 0, 27, 1),
42 FUNC("wdg_cs1", 1, 27, 1),
43};
44static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
45static struct rt2880_pmx_func rt3352_rgmii_func[] = {
46 FUNC("rgmii", 0, 24, 12)
47};
48static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
49static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
50static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
51static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
52
53static struct rt2880_pmx_group rt3050_pinmux_data[] = {
54 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
55 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
56 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
57 RT305X_GPIO_MODE_UART0_SHIFT),
58 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
59 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
60 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
61 GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
62 GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
63 { 0 }
64};
65
66static struct rt2880_pmx_group rt3352_pinmux_data[] = {
67 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
68 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
69 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
70 RT305X_GPIO_MODE_UART0_SHIFT),
71 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
72 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
73 GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
74 GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
75 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
76 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
77 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
78 { 0 }
79};
80
81static struct rt2880_pmx_group rt5350_pinmux_data[] = {
82 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
83 GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
84 GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
85 RT305X_GPIO_MODE_UART0_SHIFT),
86 GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
87 GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
88 GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
89 GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
90 { 0 }
91};
92
93static unsigned long rt5350_get_mem_size(void)
94{
95 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
96 unsigned long ret;
97 u32 t;
98
99 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
100 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
101 RT5350_SYSCFG0_DRAM_SIZE_MASK;
102
103 switch (t) {
104 case RT5350_SYSCFG0_DRAM_SIZE_2M:
105 ret = 2;
106 break;
107 case RT5350_SYSCFG0_DRAM_SIZE_8M:
108 ret = 8;
109 break;
110 case RT5350_SYSCFG0_DRAM_SIZE_16M:
111 ret = 16;
112 break;
113 case RT5350_SYSCFG0_DRAM_SIZE_32M:
114 ret = 32;
115 break;
116 case RT5350_SYSCFG0_DRAM_SIZE_64M:
117 ret = 64;
118 break;
119 default:
120 panic("rt5350: invalid DRAM size: %u", t);
121 break;
122 }
123
124 return ret;
125}
126
127void __init ralink_clk_init(void)
128{
129 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
130 unsigned long wmac_rate = 40000000;
131
132 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
133
134 if (soc_is_rt305x() || soc_is_rt3350()) {
135 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
136 RT305X_SYSCFG_CPUCLK_MASK;
137 switch (t) {
138 case RT305X_SYSCFG_CPUCLK_LOW:
139 cpu_rate = 320000000;
140 break;
141 case RT305X_SYSCFG_CPUCLK_HIGH:
142 cpu_rate = 384000000;
143 break;
144 }
145 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
146 } else if (soc_is_rt3352()) {
147 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
148 RT3352_SYSCFG0_CPUCLK_MASK;
149 switch (t) {
150 case RT3352_SYSCFG0_CPUCLK_LOW:
151 cpu_rate = 384000000;
152 break;
153 case RT3352_SYSCFG0_CPUCLK_HIGH:
154 cpu_rate = 400000000;
155 break;
156 }
157 sys_rate = wdt_rate = cpu_rate / 3;
158 uart_rate = 40000000;
159 } else if (soc_is_rt5350()) {
160 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
161 RT5350_SYSCFG0_CPUCLK_MASK;
162 switch (t) {
163 case RT5350_SYSCFG0_CPUCLK_360:
164 cpu_rate = 360000000;
165 sys_rate = cpu_rate / 3;
166 break;
167 case RT5350_SYSCFG0_CPUCLK_320:
168 cpu_rate = 320000000;
169 sys_rate = cpu_rate / 4;
170 break;
171 case RT5350_SYSCFG0_CPUCLK_300:
172 cpu_rate = 300000000;
173 sys_rate = cpu_rate / 3;
174 break;
175 default:
176 BUG();
177 }
178 uart_rate = 40000000;
179 wdt_rate = sys_rate;
180 } else {
181 BUG();
182 }
183
184 if (soc_is_rt3352() || soc_is_rt5350()) {
185 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
186
187 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
188 wmac_rate = 20000000;
189 }
190
191 ralink_clk_add("cpu", cpu_rate);
192 ralink_clk_add("sys", sys_rate);
193 ralink_clk_add("10000900.i2c", uart_rate);
194 ralink_clk_add("10000a00.i2s", uart_rate);
195 ralink_clk_add("10000b00.spi", sys_rate);
196 ralink_clk_add("10000b40.spi", sys_rate);
197 ralink_clk_add("10000100.timer", wdt_rate);
198 ralink_clk_add("10000120.watchdog", wdt_rate);
199 ralink_clk_add("10000500.uart", uart_rate);
200 ralink_clk_add("10000c00.uartlite", uart_rate);
201 ralink_clk_add("10100000.ethernet", sys_rate);
202 ralink_clk_add("10180000.wmac", wmac_rate);
203}
204
205void __init ralink_of_remap(void)
206{
207 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
208 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
209
210 if (!rt_sysc_membase || !rt_memc_membase)
211 panic("Failed to remap core resources");
212}
213
214void prom_soc_init(struct ralink_soc_info *soc_info)
215{
216 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
217 unsigned char *name;
218 u32 n0;
219 u32 n1;
220 u32 id;
221
222 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
223 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
224
225 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
226 unsigned long icache_sets;
227
228 icache_sets = (read_c0_config1() >> 22) & 7;
229 if (icache_sets == 1) {
230 ralink_soc = RT305X_SOC_RT3050;
231 name = "RT3050";
232 soc_info->compatible = "ralink,rt3050-soc";
233 } else {
234 ralink_soc = RT305X_SOC_RT3052;
235 name = "RT3052";
236 soc_info->compatible = "ralink,rt3052-soc";
237 }
238 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
239 ralink_soc = RT305X_SOC_RT3350;
240 name = "RT3350";
241 soc_info->compatible = "ralink,rt3350-soc";
242 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
243 ralink_soc = RT305X_SOC_RT3352;
244 name = "RT3352";
245 soc_info->compatible = "ralink,rt3352-soc";
246 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
247 ralink_soc = RT305X_SOC_RT5350;
248 name = "RT5350";
249 soc_info->compatible = "ralink,rt5350-soc";
250 } else {
251 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
252 }
253
254 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
255
256 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
257 "Ralink %s id:%u rev:%u",
258 name,
259 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
260 (id & CHIP_ID_REV_MASK));
261
262 soc_info->mem_base = RT305X_SDRAM_BASE;
263 if (soc_is_rt5350()) {
264 soc_info->mem_size = rt5350_get_mem_size();
265 rt2880_pinmux_data = rt5350_pinmux_data;
266 } else if (soc_is_rt305x() || soc_is_rt3350()) {
267 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
268 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
269 rt2880_pinmux_data = rt3050_pinmux_data;
270 } else if (soc_is_rt3352()) {
271 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
272 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
273 rt2880_pinmux_data = rt3352_pinmux_data;
274 }
275}