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192.168.1.100 / T800 / b29aec358f22d21c6e54decdbdc53c0e8aa7c76b / . / src / kernel / linux / v4.19 / drivers / i2c / busses / i2c-mt65xx.c
blob: 975e6d9885a05656ef0fa3dedd79864e712967ba [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/err.h>
21#include <linux/errno.h>
22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/of_address.h>
30#include <linux/of_device.h>
31#include <linux/of_irq.h>
32#include <linux/pinctrl/consumer.h>
33#include <linux/platform_device.h>
34#include <linux/scatterlist.h>
35#include <linux/sched.h>
36#include <linux/slab.h>
37
38#define I2C_RS_TRANSFER (1 << 4)
39#define I2C_ARB_LOST (1 << 3)
40#define I2C_HS_NACKERR (1 << 2)
41#define I2C_ACKERR (1 << 1)
42#define I2C_TRANSAC_COMP (1 << 0)
43#define I2C_TRANSAC_START (1 << 0)
44#define I2C_RS_MUL_CNFG (1 << 15)
45#define I2C_RS_MUL_TRIG (1 << 14)
46#define I2C_DCM_DISABLE 0x0000
47#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
48#define I2C_IO_CONFIG_PUSH_PULL 0x0000
49#define I2C_SOFT_RST 0x0001
50#define I2C_FIFO_ADDR_CLR 0x0001
51#define I2C_DELAY_LEN 0x0002
52#define I2C_ST_START_CON 0x8001
53#define I2C_FS_START_CON 0x1800
54#define I2C_TIME_CLR_VALUE 0x0000
55#define I2C_TIME_DEFAULT_VALUE 0x0003
56#define I2C_WRRD_TRANAC_VALUE 0x0002
57#define I2C_RD_TRANAC_VALUE 0x0001
58
59#define I2C_DMA_CON_TX 0x0000
60#define I2C_DMA_CON_RX 0x0001
61#define I2C_DMA_START_EN 0x0001
62#define I2C_DMA_INT_FLAG_NONE 0x0000
63#define I2C_DMA_CLR_FLAG 0x0000
64#define I2C_DMA_HARD_RST 0x0002
65
66#define I2C_DEFAULT_CLK_DIV 5
67#define I2C_DEFAULT_SPEED 100000 /* hz */
68#define MAX_FS_MODE_SPEED 400000
69#define MAX_HS_MODE_SPEED 3400000
70#define MAX_SAMPLE_CNT_DIV 8
71#define MAX_STEP_CNT_DIV 64
72#define MAX_HS_STEP_CNT_DIV 8
73
74#define I2C_CONTROL_RS (0x1 << 1)
75#define I2C_CONTROL_DMA_EN (0x1 << 2)
76#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
77#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
78#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
79#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
80#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
81#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
82#define I2C_CONTROL_WRAPPER (0x1 << 0)
83
84#define I2C_DRV_NAME "i2c-mt65xx"
85
86enum DMA_REGS_OFFSET {
87 OFFSET_INT_FLAG = 0x0,
88 OFFSET_INT_EN = 0x04,
89 OFFSET_EN = 0x08,
90 OFFSET_RST = 0x0c,
91 OFFSET_CON = 0x18,
92 OFFSET_TX_MEM_ADDR = 0x1c,
93 OFFSET_RX_MEM_ADDR = 0x20,
94 OFFSET_TX_LEN = 0x24,
95 OFFSET_RX_LEN = 0x28,
96 OFFSET_TX_4G_MODE = 0x54,
97 OFFSET_RX_4G_MODE = 0x58,
98};
99
100enum i2c_trans_st_rs {
101 I2C_TRANS_STOP = 0,
102 I2C_TRANS_REPEATED_START,
103};
104
105enum mtk_trans_op {
106 I2C_MASTER_WR = 1,
107 I2C_MASTER_RD,
108 I2C_MASTER_WRRD,
109};
110
111enum I2C_REGS_OFFSET {
112 OFFSET_DATA_PORT,
113 OFFSET_SLAVE_ADDR,
114 OFFSET_INTR_MASK,
115 OFFSET_INTR_STAT,
116 OFFSET_CONTROL,
117 OFFSET_TRANSFER_LEN,
118 OFFSET_TRANSAC_LEN,
119 OFFSET_DELAY_LEN,
120 OFFSET_TIMING,
121 OFFSET_START,
122 OFFSET_EXT_CONF,
123 OFFSET_FIFO_STAT,
124 OFFSET_FIFO_THRESH,
125 OFFSET_FIFO_ADDR_CLR,
126 OFFSET_IO_CONFIG,
127 OFFSET_RSV_DEBUG,
128 OFFSET_HS,
129 OFFSET_SOFTRESET,
130 OFFSET_DCM_EN,
131 OFFSET_PATH_DIR,
132 OFFSET_DEBUGSTAT,
133 OFFSET_DEBUGCTRL,
134 OFFSET_TRANSFER_LEN_AUX,
135 OFFSET_CLOCK_DIV,
136 OFFSET_LTIMING,
137};
138
139static const u16 mt_i2c_regs_v1[] = {
140 [OFFSET_DATA_PORT] = 0x0,
141 [OFFSET_SLAVE_ADDR] = 0x4,
142 [OFFSET_INTR_MASK] = 0x8,
143 [OFFSET_INTR_STAT] = 0xc,
144 [OFFSET_CONTROL] = 0x10,
145 [OFFSET_TRANSFER_LEN] = 0x14,
146 [OFFSET_TRANSAC_LEN] = 0x18,
147 [OFFSET_DELAY_LEN] = 0x1c,
148 [OFFSET_TIMING] = 0x20,
149 [OFFSET_START] = 0x24,
150 [OFFSET_EXT_CONF] = 0x28,
151 [OFFSET_FIFO_STAT] = 0x30,
152 [OFFSET_FIFO_THRESH] = 0x34,
153 [OFFSET_FIFO_ADDR_CLR] = 0x38,
154 [OFFSET_IO_CONFIG] = 0x40,
155 [OFFSET_RSV_DEBUG] = 0x44,
156 [OFFSET_HS] = 0x48,
157 [OFFSET_SOFTRESET] = 0x50,
158 [OFFSET_DCM_EN] = 0x54,
159 [OFFSET_PATH_DIR] = 0x60,
160 [OFFSET_DEBUGSTAT] = 0x64,
161 [OFFSET_DEBUGCTRL] = 0x68,
162 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
163 [OFFSET_CLOCK_DIV] = 0x70,
164};
165
166static const u16 mt_i2c_regs_v2[] = {
167 [OFFSET_DATA_PORT] = 0x0,
168 [OFFSET_SLAVE_ADDR] = 0x4,
169 [OFFSET_INTR_MASK] = 0x8,
170 [OFFSET_INTR_STAT] = 0xc,
171 [OFFSET_CONTROL] = 0x10,
172 [OFFSET_TRANSFER_LEN] = 0x14,
173 [OFFSET_TRANSAC_LEN] = 0x18,
174 [OFFSET_DELAY_LEN] = 0x1c,
175 [OFFSET_TIMING] = 0x20,
176 [OFFSET_START] = 0x24,
177 [OFFSET_EXT_CONF] = 0x28,
178 [OFFSET_LTIMING] = 0x2c,
179 [OFFSET_HS] = 0x30,
180 [OFFSET_IO_CONFIG] = 0x34,
181 [OFFSET_FIFO_ADDR_CLR] = 0x38,
182 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
183 [OFFSET_CLOCK_DIV] = 0x48,
184 [OFFSET_SOFTRESET] = 0x50,
185 [OFFSET_DEBUGSTAT] = 0xe0,
186 [OFFSET_DEBUGCTRL] = 0xe8,
187 [OFFSET_FIFO_STAT] = 0xf4,
188 [OFFSET_FIFO_THRESH] = 0xf8,
189 [OFFSET_DCM_EN] = 0xf88,
190};
191
192struct mtk_i2c_compatible {
193 const struct i2c_adapter_quirks *quirks;
194 const u16 *regs;
195 unsigned char pmic_i2c: 1;
196 unsigned char dcm: 1;
197 unsigned char auto_restart: 1;
198 unsigned char aux_len_reg: 1;
199 unsigned char timing_adjust: 1;
200 unsigned char dma_sync: 1;
201 unsigned char ltiming_adjust: 1;
202 unsigned int max_dma_support;
203};
204
205struct mtk_i2c {
206 struct i2c_adapter adap; /* i2c host adapter */
207 struct device *dev;
208 struct completion msg_complete;
209
210 /* set in i2c probe */
211 void __iomem *base; /* i2c base addr */
212 void __iomem *pdmabase; /* dma base address*/
213 struct clk *clk_main; /* main clock for i2c bus */
214 struct clk *clk_dma; /* DMA clock for i2c via DMA */
215 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
216 struct clk *clk_arb; /* Arbitrator clock for i2c */
217 bool have_pmic; /* can use i2c pins from PMIC */
218 bool use_push_pull; /* IO config push-pull mode */
219
220 u16 irq_stat; /* interrupt status */
221 unsigned int clk_src_div;
222 unsigned int speed_hz; /* The speed in transfer */
223 enum mtk_trans_op op;
224 u16 timing_reg;
225 u16 high_speed_reg;
226 u16 ltiming_reg;
227 unsigned char auto_restart;
228 bool ignore_restart_irq;
229 const struct mtk_i2c_compatible *dev_comp;
230};
231
232static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
233 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
234 .max_num_msgs = 1,
235 .max_write_len = 255,
236 .max_read_len = 255,
237 .max_comb_1st_msg_len = 255,
238 .max_comb_2nd_msg_len = 31,
239};
240
241static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
242 .max_num_msgs = 255,
243};
244
245static const struct mtk_i2c_compatible mt2712_compat = {
246 .regs = mt_i2c_regs_v1,
247 .pmic_i2c = 0,
248 .dcm = 1,
249 .auto_restart = 1,
250 .aux_len_reg = 1,
251 .timing_adjust = 1,
252 .dma_sync = 0,
253 .ltiming_adjust = 0,
254 .max_dma_support = 33,
255};
256
257static const struct mtk_i2c_compatible mt6577_compat = {
258 .quirks = &mt6577_i2c_quirks,
259 .regs = mt_i2c_regs_v1,
260 .pmic_i2c = 0,
261 .dcm = 1,
262 .auto_restart = 0,
263 .aux_len_reg = 0,
264 .timing_adjust = 0,
265 .dma_sync = 0,
266 .ltiming_adjust = 0,
267 .max_dma_support = 32,
268};
269
270static const struct mtk_i2c_compatible mt6589_compat = {
271 .quirks = &mt6577_i2c_quirks,
272 .regs = mt_i2c_regs_v1,
273 .pmic_i2c = 1,
274 .dcm = 0,
275 .auto_restart = 0,
276 .aux_len_reg = 0,
277 .timing_adjust = 0,
278 .dma_sync = 0,
279 .ltiming_adjust = 0,
280 .max_dma_support = 32,
281};
282
283static const struct mtk_i2c_compatible mt7622_compat = {
284 .quirks = &mt7622_i2c_quirks,
285 .regs = mt_i2c_regs_v1,
286 .pmic_i2c = 0,
287 .dcm = 1,
288 .auto_restart = 1,
289 .aux_len_reg = 1,
290 .timing_adjust = 0,
291 .dma_sync = 0,
292 .ltiming_adjust = 0,
293 .max_dma_support = 32,
294};
295
296static const struct mtk_i2c_compatible mt8173_compat = {
297 .regs = mt_i2c_regs_v1,
298 .pmic_i2c = 0,
299 .dcm = 1,
300 .auto_restart = 1,
301 .aux_len_reg = 1,
302 .timing_adjust = 0,
303 .dma_sync = 0,
304 .ltiming_adjust = 0,
305 .max_dma_support = 33,
306};
307
308static const struct mtk_i2c_compatible mt8183_compat = {
309 .regs = mt_i2c_regs_v2,
310 .pmic_i2c = 0,
311 .dcm = 0,
312 .auto_restart = 1,
313 .aux_len_reg = 1,
314 .timing_adjust = 1,
315 .dma_sync = 1,
316 .ltiming_adjust = 1,
317 .max_dma_support = 36,
318};
319
320static const struct of_device_id mtk_i2c_of_match[] = {
321 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
322 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
323 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
324 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
325 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
326 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
327 {}
328};
329MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
330
331static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
332{
333 return readw(i2c->base + i2c->dev_comp->regs[reg]);
334}
335
336static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
337 enum I2C_REGS_OFFSET reg)
338{
339 writew(val, i2c->base + i2c->dev_comp->regs[reg]);
340}
341
342static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
343{
344 int ret;
345
346 ret = clk_prepare_enable(i2c->clk_dma);
347 if (ret)
348 return ret;
349
350 ret = clk_prepare_enable(i2c->clk_main);
351 if (ret)
352 goto err_main;
353
354 if (i2c->have_pmic) {
355 ret = clk_prepare_enable(i2c->clk_pmic);
356 if (ret)
357 goto err_pmic;
358 }
359
360 if (i2c->clk_arb) {
361 ret = clk_prepare_enable(i2c->clk_arb);
362 if (ret)
363 goto err_arb;
364 }
365
366 return 0;
367
368err_arb:
369 if (i2c->have_pmic)
370 clk_disable_unprepare(i2c->clk_pmic);
371err_pmic:
372 clk_disable_unprepare(i2c->clk_main);
373err_main:
374 clk_disable_unprepare(i2c->clk_dma);
375
376 return ret;
377}
378
379static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
380{
381 if (i2c->clk_arb)
382 clk_disable_unprepare(i2c->clk_arb);
383
384 if (i2c->have_pmic)
385 clk_disable_unprepare(i2c->clk_pmic);
386
387 clk_disable_unprepare(i2c->clk_main);
388 clk_disable_unprepare(i2c->clk_dma);
389}
390
391static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
392{
393 u16 control_reg;
394
395 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
396
397 /* Set ioconfig */
398 if (i2c->use_push_pull)
399 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
400 else
401 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
402
403 if (i2c->dev_comp->dcm)
404 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
405
406 if (i2c->dev_comp->timing_adjust)
407 mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
408
409 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
410 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
411 if (i2c->dev_comp->ltiming_adjust)
412 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
413
414 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
415 if (i2c->have_pmic)
416 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
417
418 control_reg = I2C_CONTROL_ACKERR_DET_EN |
419 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
420 if (i2c->dev_comp->dma_sync)
421 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
422
423 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
424 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
425
426 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
427 udelay(50);
428 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
429}
430
431/*
432 * Calculate i2c port speed
433 *
434 * Hardware design:
435 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
436 * clock_div: fixed in hardware, but may be various in different SoCs
437 *
438 * The calculation want to pick the highest bus frequency that is still
439 * less than or equal to i2c->speed_hz. The calculation try to get
440 * sample_cnt and step_cn
441 */
442static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
443 unsigned int target_speed,
444 unsigned int *timing_step_cnt,
445 unsigned int *timing_sample_cnt)
446{
447 unsigned int step_cnt;
448 unsigned int sample_cnt;
449 unsigned int max_step_cnt;
450 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
451 unsigned int base_step_cnt;
452 unsigned int opt_div;
453 unsigned int best_mul;
454 unsigned int cnt_mul;
455
456 if (target_speed > MAX_HS_MODE_SPEED)
457 target_speed = MAX_HS_MODE_SPEED;
458
459 if (target_speed > MAX_FS_MODE_SPEED)
460 max_step_cnt = MAX_HS_STEP_CNT_DIV;
461 else
462 max_step_cnt = MAX_STEP_CNT_DIV;
463
464 base_step_cnt = max_step_cnt;
465 /* Find the best combination */
466 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
467 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
468
469 /* Search for the best pair (sample_cnt, step_cnt) with
470 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
471 * 0 < step_cnt < max_step_cnt
472 * sample_cnt * step_cnt >= opt_div
473 * optimizing for sample_cnt * step_cnt being minimal
474 */
475 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
476 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
477 cnt_mul = step_cnt * sample_cnt;
478 if (step_cnt > max_step_cnt)
479 continue;
480
481 if (cnt_mul < best_mul) {
482 best_mul = cnt_mul;
483 base_sample_cnt = sample_cnt;
484 base_step_cnt = step_cnt;
485 if (best_mul == opt_div)
486 break;
487 }
488 }
489
490 sample_cnt = base_sample_cnt;
491 step_cnt = base_step_cnt;
492
493 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
494 /* In this case, hardware can't support such
495 * low i2c_bus_freq
496 */
497 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
498 return -EINVAL;
499 }
500
501 *timing_step_cnt = step_cnt - 1;
502 *timing_sample_cnt = sample_cnt - 1;
503
504 return 0;
505}
506
507static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
508{
509 unsigned int clk_src;
510 unsigned int step_cnt;
511 unsigned int sample_cnt;
512 unsigned int l_step_cnt;
513 unsigned int l_sample_cnt;
514 unsigned int target_speed;
515 int ret;
516
517 clk_src = parent_clk / i2c->clk_src_div;
518 target_speed = i2c->speed_hz;
519
520 if (target_speed > MAX_FS_MODE_SPEED) {
521 /* Set master code speed register */
522 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
523 &l_step_cnt, &l_sample_cnt);
524 if (ret < 0)
525 return ret;
526
527 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
528
529 /* Set the high speed mode register */
530 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
531 &step_cnt, &sample_cnt);
532 if (ret < 0)
533 return ret;
534
535 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
536 (sample_cnt << 12) | (step_cnt << 8);
537
538 if (i2c->dev_comp->ltiming_adjust)
539 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
540 (sample_cnt << 12) | (step_cnt << 9);
541 } else {
542 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
543 &step_cnt, &sample_cnt);
544 if (ret < 0)
545 return ret;
546
547 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
548
549 /* Disable the high speed transaction */
550 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
551
552 if (i2c->dev_comp->ltiming_adjust)
553 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
554 }
555
556 return 0;
557}
558
559static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
560 int num, int left_num)
561{
562 u16 addr_reg;
563 u16 start_reg;
564 u16 control_reg;
565 u16 restart_flag = 0;
566 u32 reg_4g_mode;
567 u8 *dma_rd_buf = NULL;
568 u8 *dma_wr_buf = NULL;
569 dma_addr_t rpaddr = 0;
570 dma_addr_t wpaddr = 0;
571 int ret;
572
573 i2c->irq_stat = 0;
574
575 if (i2c->auto_restart)
576 restart_flag = I2C_RS_TRANSFER;
577
578 reinit_completion(&i2c->msg_complete);
579
580 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
581 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
582 if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
583 control_reg |= I2C_CONTROL_RS;
584
585 if (i2c->op == I2C_MASTER_WRRD)
586 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
587
588 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
589
590 /* set start condition */
591 if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
592 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
593 else
594 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
595
596 addr_reg = i2c_8bit_addr_from_msg(msgs);
597 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
598
599 /* Clear interrupt status */
600 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
601 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
602
603 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
604
605 /* Enable interrupt */
606 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
607 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
608
609 /* Set transfer and transaction len */
610 if (i2c->op == I2C_MASTER_WRRD) {
611 if (i2c->dev_comp->aux_len_reg) {
612 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
613 mtk_i2c_writew(i2c, (msgs + 1)->len,
614 OFFSET_TRANSFER_LEN_AUX);
615 } else {
616 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
617 OFFSET_TRANSFER_LEN);
618 }
619 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
620 } else {
621 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
622 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
623 }
624
625 /* Prepare buffer data to start transfer */
626 if (i2c->op == I2C_MASTER_RD) {
627 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
628 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
629
630 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
631 if (!dma_rd_buf)
632 return -ENOMEM;
633
634 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
635 msgs->len, DMA_FROM_DEVICE);
636 if (dma_mapping_error(i2c->dev, rpaddr)) {
637 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
638
639 return -ENOMEM;
640 }
641
642 if (i2c->dev_comp->max_dma_support > 32) {
643 reg_4g_mode = upper_32_bits(rpaddr);
644 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
645 }
646
647 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
648 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
649 } else if (i2c->op == I2C_MASTER_WR) {
650 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
651 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
652
653 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
654 if (!dma_wr_buf)
655 return -ENOMEM;
656
657 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
658 msgs->len, DMA_TO_DEVICE);
659 if (dma_mapping_error(i2c->dev, wpaddr)) {
660 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
661
662 return -ENOMEM;
663 }
664
665 if (i2c->dev_comp->max_dma_support > 32) {
666 reg_4g_mode = upper_32_bits(wpaddr);
667 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
668 }
669
670 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
671 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
672 } else {
673 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
674 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
675
676 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
677 if (!dma_wr_buf)
678 return -ENOMEM;
679
680 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
681 msgs->len, DMA_TO_DEVICE);
682 if (dma_mapping_error(i2c->dev, wpaddr)) {
683 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
684
685 return -ENOMEM;
686 }
687
688 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
689 if (!dma_rd_buf) {
690 dma_unmap_single(i2c->dev, wpaddr,
691 msgs->len, DMA_TO_DEVICE);
692
693 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
694
695 return -ENOMEM;
696 }
697
698 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
699 (msgs + 1)->len,
700 DMA_FROM_DEVICE);
701 if (dma_mapping_error(i2c->dev, rpaddr)) {
702 dma_unmap_single(i2c->dev, wpaddr,
703 msgs->len, DMA_TO_DEVICE);
704
705 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
706 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
707
708 return -ENOMEM;
709 }
710
711 if (i2c->dev_comp->max_dma_support > 32) {
712 reg_4g_mode = upper_32_bits(wpaddr);
713 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
714
715 reg_4g_mode = upper_32_bits(rpaddr);
716 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
717 }
718
719 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
720 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
721 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
722 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
723 }
724
725 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
726
727 if (!i2c->auto_restart) {
728 start_reg = I2C_TRANSAC_START;
729 } else {
730 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
731 if (left_num >= 1)
732 start_reg |= I2C_RS_MUL_CNFG;
733 }
734 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
735
736 ret = wait_for_completion_timeout(&i2c->msg_complete,
737 i2c->adap.timeout);
738
739 /* Clear interrupt mask */
740 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
741 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
742
743 if (i2c->op == I2C_MASTER_WR) {
744 dma_unmap_single(i2c->dev, wpaddr,
745 msgs->len, DMA_TO_DEVICE);
746
747 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
748 } else if (i2c->op == I2C_MASTER_RD) {
749 dma_unmap_single(i2c->dev, rpaddr,
750 msgs->len, DMA_FROM_DEVICE);
751
752 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
753 } else {
754 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
755 DMA_TO_DEVICE);
756 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
757 DMA_FROM_DEVICE);
758
759 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
760 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
761 }
762
763 if (ret == 0) {
764 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
765 mtk_i2c_init_hw(i2c);
766 return -ETIMEDOUT;
767 }
768
769 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
770 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
771 mtk_i2c_init_hw(i2c);
772 return -ENXIO;
773 }
774
775 return 0;
776}
777
778static int mtk_i2c_transfer(struct i2c_adapter *adap,
779 struct i2c_msg msgs[], int num)
780{
781 int ret;
782 int left_num = num;
783 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
784
785 ret = mtk_i2c_clock_enable(i2c);
786 if (ret)
787 return ret;
788
789 i2c->auto_restart = i2c->dev_comp->auto_restart;
790
791 /* checking if we can skip restart and optimize using WRRD mode */
792 if (i2c->auto_restart && num == 2) {
793 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
794 msgs[0].addr == msgs[1].addr) {
795 i2c->auto_restart = 0;
796 }
797 }
798
799 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
800 /* ignore the first restart irq after the master code,
801 * otherwise the first transfer will be discarded.
802 */
803 i2c->ignore_restart_irq = true;
804 else
805 i2c->ignore_restart_irq = false;
806
807 while (left_num--) {
808 if (!msgs->buf) {
809 dev_dbg(i2c->dev, "data buffer is NULL.\n");
810 ret = -EINVAL;
811 goto err_exit;
812 }
813
814 if (msgs->flags & I2C_M_RD)
815 i2c->op = I2C_MASTER_RD;
816 else
817 i2c->op = I2C_MASTER_WR;
818
819 if (!i2c->auto_restart) {
820 if (num > 1) {
821 /* combined two messages into one transaction */
822 i2c->op = I2C_MASTER_WRRD;
823 left_num--;
824 }
825 }
826
827 /* always use DMA mode. */
828 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
829 if (ret < 0)
830 goto err_exit;
831
832 msgs++;
833 }
834 /* the return value is number of executed messages */
835 ret = num;
836
837err_exit:
838 mtk_i2c_clock_disable(i2c);
839 return ret;
840}
841
842static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
843{
844 struct mtk_i2c *i2c = dev_id;
845 u16 restart_flag = 0;
846 u16 intr_stat;
847
848 if (i2c->auto_restart)
849 restart_flag = I2C_RS_TRANSFER;
850
851 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
852 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
853
854 /*
855 * when occurs ack error, i2c controller generate two interrupts
856 * first is the ack error interrupt, then the complete interrupt
857 * i2c->irq_stat need keep the two interrupt value.
858 */
859 i2c->irq_stat |= intr_stat;
860
861 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
862 i2c->ignore_restart_irq = false;
863 i2c->irq_stat = 0;
864 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
865 I2C_TRANSAC_START, OFFSET_START);
866 } else {
867 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
868 complete(&i2c->msg_complete);
869 }
870
871 return IRQ_HANDLED;
872}
873
874static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
875{
876 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
877}
878
879static const struct i2c_algorithm mtk_i2c_algorithm = {
880 .master_xfer = mtk_i2c_transfer,
881 .functionality = mtk_i2c_functionality,
882};
883
884static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
885{
886 int ret;
887
888 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
889 if (ret < 0)
890 i2c->speed_hz = I2C_DEFAULT_SPEED;
891
892 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
893 if (ret < 0)
894 return ret;
895
896 if (i2c->clk_src_div == 0)
897 return -EINVAL;
898
899 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
900 i2c->use_push_pull =
901 of_property_read_bool(np, "mediatek,use-push-pull");
902
903 return 0;
904}
905
906static int mtk_i2c_probe(struct platform_device *pdev)
907{
908 int ret = 0;
909 struct mtk_i2c *i2c;
910 struct clk *clk;
911 struct resource *res;
912 int irq;
913
914 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
915 if (!i2c)
916 return -ENOMEM;
917
918 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
919 i2c->base = devm_ioremap_resource(&pdev->dev, res);
920 if (IS_ERR(i2c->base))
921 return PTR_ERR(i2c->base);
922
923 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
924 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
925 if (IS_ERR(i2c->pdmabase))
926 return PTR_ERR(i2c->pdmabase);
927
928 irq = platform_get_irq(pdev, 0);
929 if (irq <= 0)
930 return irq;
931
932 init_completion(&i2c->msg_complete);
933
934 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
935 i2c->adap.dev.of_node = pdev->dev.of_node;
936 i2c->dev = &pdev->dev;
937 i2c->adap.dev.parent = &pdev->dev;
938 i2c->adap.owner = THIS_MODULE;
939 i2c->adap.algo = &mtk_i2c_algorithm;
940 i2c->adap.quirks = i2c->dev_comp->quirks;
941 i2c->adap.timeout = 2 * HZ;
942 i2c->adap.retries = 1;
943
944 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
945 if (ret)
946 return -EINVAL;
947
948 if (i2c->dev_comp->timing_adjust)
949 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
950
951 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
952 return -EINVAL;
953
954 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
955 if (IS_ERR(i2c->clk_main)) {
956 dev_err(&pdev->dev, "cannot get main clock\n");
957 return PTR_ERR(i2c->clk_main);
958 }
959
960 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
961 if (IS_ERR(i2c->clk_dma)) {
962 dev_err(&pdev->dev, "cannot get dma clock\n");
963 return PTR_ERR(i2c->clk_dma);
964 }
965
966 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
967 if (IS_ERR(i2c->clk_arb))
968 i2c->clk_arb = NULL;
969
970 clk = i2c->clk_main;
971 if (i2c->have_pmic) {
972 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
973 if (IS_ERR(i2c->clk_pmic)) {
974 dev_err(&pdev->dev, "cannot get pmic clock\n");
975 return PTR_ERR(i2c->clk_pmic);
976 }
977 clk = i2c->clk_pmic;
978 }
979
980 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
981
982 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
983 if (ret) {
984 dev_err(&pdev->dev, "Failed to set the speed.\n");
985 return -EINVAL;
986 }
987
988 if (i2c->dev_comp->max_dma_support > 32) {
989 ret = dma_set_mask(&pdev->dev,
990 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
991 if (ret) {
992 dev_err(&pdev->dev, "dma_set_mask return error.\n");
993 return ret;
994 }
995 }
996
997 ret = mtk_i2c_clock_enable(i2c);
998 if (ret) {
999 dev_err(&pdev->dev, "clock enable failed!\n");
1000 return ret;
1001 }
1002 mtk_i2c_init_hw(i2c);
1003 mtk_i2c_clock_disable(i2c);
1004
1005 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1006 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
1007 if (ret < 0) {
1008 dev_err(&pdev->dev,
1009 "Request I2C IRQ %d fail\n", irq);
1010 return ret;
1011 }
1012
1013 i2c_set_adapdata(&i2c->adap, i2c);
1014 ret = i2c_add_adapter(&i2c->adap);
1015 if (ret)
1016 return ret;
1017
1018 platform_set_drvdata(pdev, i2c);
1019
1020 return 0;
1021}
1022
1023static int mtk_i2c_remove(struct platform_device *pdev)
1024{
1025 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1026
1027 i2c_del_adapter(&i2c->adap);
1028
1029 return 0;
1030}
1031
1032#ifdef CONFIG_PM_SLEEP
1033static int mtk_i2c_resume(struct device *dev)
1034{
1035 int ret;
1036 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1037
1038 ret = pinctrl_pm_select_default_state(dev);
1039 if (ret < 0)
1040 dev_notice(dev, "failed to set pin default_state (%d)\n", ret);
1041
1042 /* enable i2c clock to sync i2c register configuration */
1043 ret = mtk_i2c_clock_enable(i2c);
1044 if (ret) {
1045 dev_err(dev, "clock enable failed!\n");
1046 return ret;
1047 }
1048
1049 mtk_i2c_init_hw(i2c);
1050
1051 mtk_i2c_clock_disable(i2c);
1052
1053 return 0;
1054}
1055
1056static int mtk_i2c_suspend(struct device *dev)
1057{
1058 int ret = 0;
1059
1060 ret = pinctrl_pm_select_sleep_state(dev);
1061 if (ret < 0)
1062 dev_notice(dev, "failed to set pin sleep_state (%d)\n", ret);
1063
1064 return ret;
1065}
1066
1067static const struct dev_pm_ops mtk_i2c_pm = {
1068 SET_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend, mtk_i2c_resume)
1069};
1070#endif
1071
1072static struct platform_driver mtk_i2c_driver = {
1073 .probe = mtk_i2c_probe,
1074 .remove = mtk_i2c_remove,
1075 .driver = {
1076 .name = I2C_DRV_NAME,
1077#ifdef CONFIG_PM_SLEEP
1078 .pm = &mtk_i2c_pm,
1079#endif
1080 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1081 },
1082};
1083
1084module_platform_driver(mtk_i2c_driver);
1085
1086MODULE_LICENSE("GPL v2");
1087MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1088MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");