| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | # Intel pin control drivers |
| 3 | |
| 4 | if (X86 || COMPILE_TEST) |
| 5 | |
| 6 | config PINCTRL_BAYTRAIL |
| 7 | bool "Intel Baytrail GPIO pin control" |
| 8 | depends on ACPI |
| 9 | select GPIOLIB |
| 10 | select GPIOLIB_IRQCHIP |
| 11 | select PINMUX |
| 12 | select PINCONF |
| 13 | select GENERIC_PINCONF |
| 14 | help |
| 15 | driver for memory mapped GPIO functionality on Intel Baytrail |
| 16 | platforms. Supports 3 banks with 102, 28 and 44 gpios. |
| 17 | Most pins are usually muxed to some other functionality by firmware, |
| 18 | so only a small amount is available for gpio use. |
| 19 | |
| 20 | Requires ACPI device enumeration code to set up a platform device. |
| 21 | |
| 22 | config PINCTRL_CHERRYVIEW |
| 23 | tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" |
| 24 | depends on ACPI |
| 25 | select PINMUX |
| 26 | select PINCONF |
| 27 | select GENERIC_PINCONF |
| 28 | select GPIOLIB |
| 29 | select GPIOLIB_IRQCHIP |
| 30 | help |
| 31 | Cherryview/Braswell pinctrl driver provides an interface that |
| 32 | allows configuring of SoC pins and using them as GPIOs. |
| 33 | |
| 34 | config PINCTRL_MERRIFIELD |
| 35 | tristate "Intel Merrifield pinctrl driver" |
| 36 | depends on X86_INTEL_MID |
| 37 | select PINMUX |
| 38 | select PINCONF |
| 39 | select GENERIC_PINCONF |
| 40 | help |
| 41 | Merrifield Family-Level Interface Shim (FLIS) driver provides an |
| 42 | interface that allows configuring of SoC pins and using them as |
| 43 | GPIOs. |
| 44 | |
| 45 | config PINCTRL_INTEL |
| 46 | tristate |
| 47 | select PINMUX |
| 48 | select PINCONF |
| 49 | select GENERIC_PINCONF |
| 50 | select GPIOLIB |
| 51 | select GPIOLIB_IRQCHIP |
| 52 | |
| 53 | config PINCTRL_BROXTON |
| 54 | tristate "Intel Broxton pinctrl and GPIO driver" |
| 55 | depends on ACPI |
| 56 | select PINCTRL_INTEL |
| 57 | help |
| 58 | Broxton pinctrl driver provides an interface that allows |
| 59 | configuring of SoC pins and using them as GPIOs. |
| 60 | |
| 61 | config PINCTRL_CANNONLAKE |
| 62 | tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" |
| 63 | depends on ACPI |
| 64 | select PINCTRL_INTEL |
| 65 | help |
| 66 | This pinctrl driver provides an interface that allows configuring |
| 67 | of Intel Cannon Lake PCH pins and using them as GPIOs. |
| 68 | |
| 69 | config PINCTRL_CEDARFORK |
| 70 | tristate "Intel Cedar Fork pinctrl and GPIO driver" |
| 71 | depends on ACPI |
| 72 | select PINCTRL_INTEL |
| 73 | help |
| 74 | This pinctrl driver provides an interface that allows configuring |
| 75 | of Intel Cedar Fork PCH pins and using them as GPIOs. |
| 76 | |
| 77 | config PINCTRL_DENVERTON |
| 78 | tristate "Intel Denverton pinctrl and GPIO driver" |
| 79 | depends on ACPI |
| 80 | select PINCTRL_INTEL |
| 81 | help |
| 82 | This pinctrl driver provides an interface that allows configuring |
| 83 | of Intel Denverton SoC pins and using them as GPIOs. |
| 84 | |
| 85 | config PINCTRL_GEMINILAKE |
| 86 | tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" |
| 87 | depends on ACPI |
| 88 | select PINCTRL_INTEL |
| 89 | help |
| 90 | This pinctrl driver provides an interface that allows configuring |
| 91 | of Intel Gemini Lake SoC pins and using them as GPIOs. |
| 92 | |
| 93 | config PINCTRL_ICELAKE |
| 94 | tristate "Intel Ice Lake PCH pinctrl and GPIO driver" |
| 95 | depends on ACPI |
| 96 | select PINCTRL_INTEL |
| 97 | help |
| 98 | This pinctrl driver provides an interface that allows configuring |
| 99 | of Intel Ice Lake PCH pins and using them as GPIOs. |
| 100 | |
| 101 | config PINCTRL_LEWISBURG |
| 102 | tristate "Intel Lewisburg pinctrl and GPIO driver" |
| 103 | depends on ACPI |
| 104 | select PINCTRL_INTEL |
| 105 | help |
| 106 | This pinctrl driver provides an interface that allows configuring |
| 107 | of Intel Lewisburg pins and using them as GPIOs. |
| 108 | |
| 109 | config PINCTRL_SUNRISEPOINT |
| 110 | tristate "Intel Sunrisepoint pinctrl and GPIO driver" |
| 111 | depends on ACPI |
| 112 | select PINCTRL_INTEL |
| 113 | help |
| 114 | Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver |
| 115 | provides an interface that allows configuring of PCH pins and |
| 116 | using them as GPIOs. |
| 117 | |
| 118 | endif |