| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * TI DaVinci serial driver |
| 3 | * |
| 4 | * Copyright (C) 2006 Texas Instruments. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | * |
| 20 | */ |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/serial_8250.h> |
| 25 | #include <linux/serial_reg.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/clk.h> |
| 29 | #include <linux/io.h> |
| 30 | |
| 31 | #include <mach/serial.h> |
| 32 | #include <mach/cputype.h> |
| 33 | |
| 34 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, |
| 35 | int value) |
| 36 | { |
| 37 | offset <<= p->regshift; |
| 38 | |
| 39 | WARN_ONCE(!p->membase, "unmapped write: uart[%d]\n", offset); |
| 40 | |
| 41 | __raw_writel(value, p->membase + offset); |
| 42 | } |
| 43 | |
| 44 | static void __init davinci_serial_reset(struct plat_serial8250_port *p) |
| 45 | { |
| 46 | unsigned int pwremu = 0; |
| 47 | |
| 48 | serial_write_reg(p, UART_IER, 0); /* disable all interrupts */ |
| 49 | |
| 50 | /* reset both transmitter and receiver: bits 14,13 = UTRST, URRST */ |
| 51 | serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); |
| 52 | mdelay(10); |
| 53 | |
| 54 | pwremu |= (0x3 << 13); |
| 55 | pwremu |= 0x1; |
| 56 | serial_write_reg(p, UART_DAVINCI_PWREMU, pwremu); |
| 57 | |
| 58 | if (cpu_is_davinci_dm646x()) |
| 59 | serial_write_reg(p, UART_DM646X_SCR, |
| 60 | UART_DM646X_SCR_TX_WATERMARK); |
| 61 | } |
| 62 | |
| 63 | int __init davinci_serial_init(struct platform_device *serial_dev) |
| 64 | { |
| 65 | int i, ret = 0; |
| 66 | struct device *dev; |
| 67 | struct plat_serial8250_port *p; |
| 68 | struct clk *clk; |
| 69 | |
| 70 | /* |
| 71 | * Make sure the serial ports are muxed on at this point. |
| 72 | * You have to mux them off in device drivers later on if not needed. |
| 73 | */ |
| 74 | for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) { |
| 75 | dev = &serial_dev[i].dev; |
| 76 | p = dev->platform_data; |
| 77 | |
| 78 | ret = platform_device_register(&serial_dev[i]); |
| 79 | if (ret) |
| 80 | continue; |
| 81 | |
| 82 | clk = clk_get(dev, NULL); |
| 83 | if (IS_ERR(clk)) { |
| 84 | pr_err("%s:%d: failed to get UART%d clock\n", |
| 85 | __func__, __LINE__, i); |
| 86 | continue; |
| 87 | } |
| 88 | |
| 89 | clk_prepare_enable(clk); |
| 90 | |
| 91 | p->uartclk = clk_get_rate(clk); |
| 92 | |
| 93 | if (!p->membase && p->mapbase) { |
| 94 | p->membase = ioremap(p->mapbase, SZ_4K); |
| 95 | |
| 96 | if (p->membase) |
| 97 | p->flags &= ~UPF_IOREMAP; |
| 98 | else |
| 99 | pr_err("uart regs ioremap failed\n"); |
| 100 | } |
| 101 | |
| 102 | if (p->membase && p->type != PORT_AR7) |
| 103 | davinci_serial_reset(p); |
| 104 | } |
| 105 | return ret; |
| 106 | } |