| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | menuconfig ARCH_VEXPRESS |
| 3 | bool "ARM Ltd. Versatile Express family" |
| 4 | depends on ARCH_MULTI_V7 |
| 5 | select ARCH_SUPPORTS_BIG_ENDIAN |
| 6 | select ARM_AMBA |
| 7 | select ARM_GIC |
| 8 | select ARM_GLOBAL_TIMER |
| 9 | select ARM_TIMER_SP804 |
| 10 | select COMMON_CLK_VERSATILE |
| 11 | select GPIOLIB |
| 12 | select HAVE_ARM_SCU if SMP |
| 13 | select HAVE_ARM_TWD if SMP |
| 14 | select HAVE_PATA_PLATFORM |
| 15 | select ICST |
| 16 | select NO_IOPORT_MAP |
| 17 | select PLAT_VERSATILE |
| 18 | select POWER_RESET |
| 19 | select POWER_RESET_VEXPRESS |
| 20 | select POWER_SUPPLY |
| 21 | select REGULATOR if MMC_ARMMMCI |
| 22 | select REGULATOR_FIXED_VOLTAGE if REGULATOR |
| 23 | select VEXPRESS_CONFIG |
| 24 | select VEXPRESS_SYSCFG |
| 25 | select MFD_VEXPRESS_SYSREG |
| 26 | help |
| 27 | This option enables support for systems using Cortex processor based |
| 28 | ARM core and logic (FPGA) tiles on the Versatile Express motherboard, |
| 29 | for example: |
| 30 | |
| 31 | - CoreTile Express A5x2 (V2P-CA5s) |
| 32 | - CoreTile Express A9x4 (V2P-CA9) |
| 33 | - CoreTile Express A15x2 (V2P-CA15) |
| 34 | - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs |
| 35 | (Soft Macrocell Models) |
| 36 | - Versatile Express RTSMs (Models) |
| 37 | |
| 38 | You must boot using a Flattened Device Tree in order to use these |
| 39 | platforms. The traditional (ATAGs) boot method is not usable on |
| 40 | these boards with this option. |
| 41 | |
| 42 | if ARCH_VEXPRESS |
| 43 | |
| 44 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA |
| 45 | bool "Enable A5 and A9 only errata work-arounds" |
| 46 | default y |
| 47 | select ARM_ERRATA_643719 if SMP |
| 48 | select ARM_ERRATA_720789 |
| 49 | select PL310_ERRATA_753970 if CACHE_L2X0 |
| 50 | help |
| 51 | Provides common dependencies for Versatile Express platforms |
| 52 | based on Cortex-A5 and Cortex-A9 processors. In order to |
| 53 | build a working kernel, you must also enable relevant core |
| 54 | tile support or Flattened Device Tree based support options. |
| 55 | |
| 56 | config ARCH_VEXPRESS_DCSCB |
| 57 | bool "Dual Cluster System Control Block (DCSCB) support" |
| 58 | depends on MCPM |
| 59 | select ARM_CCI400_PORT_CTRL |
| 60 | help |
| 61 | Support for the Dual Cluster System Configuration Block (DCSCB). |
| 62 | This is needed to provide CPU and cluster power management |
| 63 | on RTSM implementing big.LITTLE. |
| 64 | |
| 65 | config ARCH_VEXPRESS_SPC |
| 66 | bool "Versatile Express Serial Power Controller (SPC)" |
| 67 | select PM_OPP |
| 68 | help |
| 69 | The TC2 (A15x2 A7x3) versatile express core tile integrates a logic |
| 70 | block called Serial Power Controller (SPC) that provides the interface |
| 71 | between the dual cluster test-chip and the M3 microcontroller that |
| 72 | carries out power management. |
| 73 | |
| 74 | config ARCH_VEXPRESS_TC2_PM |
| 75 | bool "Versatile Express TC2 power management" |
| 76 | depends on MCPM |
| 77 | select ARM_CCI400_PORT_CTRL |
| 78 | select ARCH_VEXPRESS_SPC |
| 79 | select ARM_CPU_SUSPEND |
| 80 | help |
| 81 | Support for CPU and cluster power management on Versatile Express |
| 82 | with a TC2 (A15x2 A7x3) big.LITTLE core tile. |
| 83 | |
| 84 | endif |