| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2018 Baylibre SAS. |
| 4 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __AXG_AUDIO_CLKC_BINDINGS_H |
| 8 | #define __AXG_AUDIO_CLKC_BINDINGS_H |
| 9 | |
| 10 | #define AUD_CLKID_SLV_SCLK0 9 |
| 11 | #define AUD_CLKID_SLV_SCLK1 10 |
| 12 | #define AUD_CLKID_SLV_SCLK2 11 |
| 13 | #define AUD_CLKID_SLV_SCLK3 12 |
| 14 | #define AUD_CLKID_SLV_SCLK4 13 |
| 15 | #define AUD_CLKID_SLV_SCLK5 14 |
| 16 | #define AUD_CLKID_SLV_SCLK6 15 |
| 17 | #define AUD_CLKID_SLV_SCLK7 16 |
| 18 | #define AUD_CLKID_SLV_SCLK8 17 |
| 19 | #define AUD_CLKID_SLV_SCLK9 18 |
| 20 | #define AUD_CLKID_SLV_LRCLK0 19 |
| 21 | #define AUD_CLKID_SLV_LRCLK1 20 |
| 22 | #define AUD_CLKID_SLV_LRCLK2 21 |
| 23 | #define AUD_CLKID_SLV_LRCLK3 22 |
| 24 | #define AUD_CLKID_SLV_LRCLK4 23 |
| 25 | #define AUD_CLKID_SLV_LRCLK5 24 |
| 26 | #define AUD_CLKID_SLV_LRCLK6 25 |
| 27 | #define AUD_CLKID_SLV_LRCLK7 26 |
| 28 | #define AUD_CLKID_SLV_LRCLK8 27 |
| 29 | #define AUD_CLKID_SLV_LRCLK9 28 |
| 30 | #define AUD_CLKID_DDR_ARB 29 |
| 31 | #define AUD_CLKID_PDM 30 |
| 32 | #define AUD_CLKID_TDMIN_A 31 |
| 33 | #define AUD_CLKID_TDMIN_B 32 |
| 34 | #define AUD_CLKID_TDMIN_C 33 |
| 35 | #define AUD_CLKID_TDMIN_LB 34 |
| 36 | #define AUD_CLKID_TDMOUT_A 35 |
| 37 | #define AUD_CLKID_TDMOUT_B 36 |
| 38 | #define AUD_CLKID_TDMOUT_C 37 |
| 39 | #define AUD_CLKID_FRDDR_A 38 |
| 40 | #define AUD_CLKID_FRDDR_B 39 |
| 41 | #define AUD_CLKID_FRDDR_C 40 |
| 42 | #define AUD_CLKID_TODDR_A 41 |
| 43 | #define AUD_CLKID_TODDR_B 42 |
| 44 | #define AUD_CLKID_TODDR_C 43 |
| 45 | #define AUD_CLKID_LOOPBACK 44 |
| 46 | #define AUD_CLKID_SPDIFIN 45 |
| 47 | #define AUD_CLKID_SPDIFOUT 46 |
| 48 | #define AUD_CLKID_RESAMPLE 47 |
| 49 | #define AUD_CLKID_POWER_DETECT 48 |
| 50 | #define AUD_CLKID_MST_A_MCLK 49 |
| 51 | #define AUD_CLKID_MST_B_MCLK 50 |
| 52 | #define AUD_CLKID_MST_C_MCLK 51 |
| 53 | #define AUD_CLKID_MST_D_MCLK 52 |
| 54 | #define AUD_CLKID_MST_E_MCLK 53 |
| 55 | #define AUD_CLKID_MST_F_MCLK 54 |
| 56 | #define AUD_CLKID_SPDIFOUT_CLK 55 |
| 57 | #define AUD_CLKID_SPDIFIN_CLK 56 |
| 58 | #define AUD_CLKID_PDM_DCLK 57 |
| 59 | #define AUD_CLKID_PDM_SYSCLK 58 |
| 60 | #define AUD_CLKID_MST_A_SCLK 79 |
| 61 | #define AUD_CLKID_MST_B_SCLK 80 |
| 62 | #define AUD_CLKID_MST_C_SCLK 81 |
| 63 | #define AUD_CLKID_MST_D_SCLK 82 |
| 64 | #define AUD_CLKID_MST_E_SCLK 83 |
| 65 | #define AUD_CLKID_MST_F_SCLK 84 |
| 66 | #define AUD_CLKID_MST_A_LRCLK 86 |
| 67 | #define AUD_CLKID_MST_B_LRCLK 87 |
| 68 | #define AUD_CLKID_MST_C_LRCLK 88 |
| 69 | #define AUD_CLKID_MST_D_LRCLK 89 |
| 70 | #define AUD_CLKID_MST_E_LRCLK 90 |
| 71 | #define AUD_CLKID_MST_F_LRCLK 91 |
| 72 | #define AUD_CLKID_TDMIN_A_SCLK_SEL 116 |
| 73 | #define AUD_CLKID_TDMIN_B_SCLK_SEL 117 |
| 74 | #define AUD_CLKID_TDMIN_C_SCLK_SEL 118 |
| 75 | #define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 |
| 76 | #define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 |
| 77 | #define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 |
| 78 | #define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 |
| 79 | #define AUD_CLKID_TDMIN_A_SCLK 123 |
| 80 | #define AUD_CLKID_TDMIN_B_SCLK 124 |
| 81 | #define AUD_CLKID_TDMIN_C_SCLK 125 |
| 82 | #define AUD_CLKID_TDMIN_LB_SCLK 126 |
| 83 | #define AUD_CLKID_TDMOUT_A_SCLK 127 |
| 84 | #define AUD_CLKID_TDMOUT_B_SCLK 128 |
| 85 | #define AUD_CLKID_TDMOUT_C_SCLK 129 |
| 86 | #define AUD_CLKID_TDMIN_A_LRCLK 130 |
| 87 | #define AUD_CLKID_TDMIN_B_LRCLK 131 |
| 88 | #define AUD_CLKID_TDMIN_C_LRCLK 132 |
| 89 | #define AUD_CLKID_TDMIN_LB_LRCLK 133 |
| 90 | #define AUD_CLKID_TDMOUT_A_LRCLK 134 |
| 91 | #define AUD_CLKID_TDMOUT_B_LRCLK 135 |
| 92 | #define AUD_CLKID_TDMOUT_C_LRCLK 136 |
| 93 | |
| 94 | #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ |