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192.168.1.100 / T800 / b6cf1b20733a87e65d3ee75f05eb8b5fa01baa6e / . / src / kernel / linux / v4.19 / drivers / spmi / mtk-pmif.c
blob: 062cbe43c02e1f439c9c55caf3f00887d4984be2 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Argus Lin <argus.lin@mediatek.com>
5 */
6/* #define DEBUG */
7
8#include <dt-bindings/spmi/spmi.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irqdomain.h>
15#include <linux/kernel.h>
16#include <linux/kthread.h>
17#include <linux/module.h>
18#include <linux/mutex.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/of_address.h>
22#include <linux/platform_device.h>
23#include <linux/pm_wakeup.h>
24#include <linux/pmif.h>
25#include <linux/regmap.h>
26#include <linux/reset.h>
27#include <linux/sched/clock.h>
28#include <linux/slab.h>
29#include <linux/spmi.h>
30#include <mt-plat/aee.h>
31
32#include "spmi_sw.h"
33
34/*
35 * marco
36 */
37#define PMIF_TIMEOUT 1
38#define PMIF_BRINGUP 0
39
40/* macro for PMIF SWINF FSM */
41#define PMIF_SWINF_FSM_IDLE 0x00
42#define PMIF_SWINF_FSM_REQ 0x02
43#define PMIF_SWINF_FSM_WFDLE 0x04
44#define PMIF_SWINF_FSM_WFVLDCLR 0x06
45#define PMIF_SWINF_INIT_DONE 0x01
46#define PMIF_SWINF_SYS_IDLE 0x00
47#define PMIF_SWINF_SYS_BUSY 0x01
48
49#define PMIF_GET_SWINF_FSM(x) ((x>>1) & 0x00000007)
50
51#define PMIF_CMD_REG_0 0
52#define PMIF_CMD_REG 1
53#define PMIF_CMD_EXT_REG 2
54#define PMIF_CMD_EXT_REG_LONG 3
55/* 0: SPI, 1: SPMI */
56#define PMIF_PMIFID_SPI 0
57#define PMIF_PMIFID_SPMI0 0
58#define PMIF_PMIFID_SPMI1 1
59#define PMIF_PMIFID_SPMI2 2
60#define PMIF_PMIFID_SPMI3 3
61
62enum pmif_regs {
63 PMIF_INIT_DONE,
64 PMIF_INF_EN,
65 PMIF_ARB_EN,
66 PMIF_CMDISSUE_EN,
67 PMIF_TIMER_CTRL,
68 PMIF_SPI_MODE_CTRL,
69 PMIF_IRQ_EVENT_EN_0,
70 PMIF_IRQ_FLAG_0,
71 PMIF_IRQ_CLR_0,
72 PMIF_IRQ_EVENT_EN_1,
73 PMIF_IRQ_FLAG_1,
74 PMIF_IRQ_CLR_1,
75 PMIF_IRQ_EVENT_EN_2,
76 PMIF_IRQ_FLAG_2,
77 PMIF_IRQ_CLR_2,
78 PMIF_IRQ_EVENT_EN_3,
79 PMIF_IRQ_FLAG_3,
80 PMIF_IRQ_CLR_3,
81 PMIF_IRQ_EVENT_EN_4,
82 PMIF_IRQ_FLAG_4,
83 PMIF_IRQ_CLR_4,
84 PMIF_WDT_EVENT_EN_0,
85 PMIF_WDT_FLAG_0,
86 PMIF_WDT_EVENT_EN_1,
87 PMIF_WDT_FLAG_1,
88 PMIF_SWINF_0_STA,
89 PMIF_SWINF_0_WDATA_31_0,
90 PMIF_SWINF_0_RDATA_31_0,
91 PMIF_SWINF_0_ACC,
92 PMIF_SWINF_0_VLD_CLR,
93 PMIF_SWINF_1_STA,
94 PMIF_SWINF_1_WDATA_31_0,
95 PMIF_SWINF_1_RDATA_31_0,
96 PMIF_SWINF_1_ACC,
97 PMIF_SWINF_1_VLD_CLR,
98 PMIF_SWINF_2_STA,
99 PMIF_SWINF_2_WDATA_31_0,
100 PMIF_SWINF_2_RDATA_31_0,
101 PMIF_SWINF_2_ACC,
102 PMIF_SWINF_2_VLD_CLR,
103 PMIF_SWINF_3_STA,
104 PMIF_SWINF_3_WDATA_31_0,
105 PMIF_SWINF_3_RDATA_31_0,
106 PMIF_SWINF_3_ACC,
107 PMIF_SWINF_3_VLD_CLR,
108};
109
110static const u32 mt6xxx_regs[] = {
111 [PMIF_INIT_DONE] = 0x0000,
112 [PMIF_INF_EN] = 0x0024,
113 [PMIF_ARB_EN] = 0x0150,
114 [PMIF_CMDISSUE_EN] = 0x03B4,
115 [PMIF_TIMER_CTRL] = 0x03E0,
116 [PMIF_SPI_MODE_CTRL] = 0x0400,
117 [PMIF_IRQ_EVENT_EN_0] = 0x0418,
118 [PMIF_IRQ_FLAG_0] = 0x0420,
119 [PMIF_IRQ_CLR_0] = 0x0424,
120 [PMIF_IRQ_EVENT_EN_1] = 0x0428,
121 [PMIF_IRQ_FLAG_1] = 0x0430,
122 [PMIF_IRQ_CLR_1] = 0x0434,
123 [PMIF_IRQ_EVENT_EN_2] = 0x0438,
124 [PMIF_IRQ_FLAG_2] = 0x0440,
125 [PMIF_IRQ_CLR_2] = 0x0444,
126 [PMIF_IRQ_EVENT_EN_3] = 0x0448,
127 [PMIF_IRQ_FLAG_3] = 0x0450,
128 [PMIF_IRQ_CLR_3] = 0x0454,
129 [PMIF_IRQ_EVENT_EN_4] = 0x0458,
130 [PMIF_IRQ_FLAG_4] = 0x0460,
131 [PMIF_IRQ_CLR_4] = 0x0464,
132 [PMIF_WDT_EVENT_EN_0] = 0x046C,
133 [PMIF_WDT_FLAG_0] = 0x0470,
134 [PMIF_WDT_EVENT_EN_1] = 0x0474,
135 [PMIF_WDT_FLAG_1] = 0x0478,
136 [PMIF_SWINF_0_ACC] = 0x0C00,
137 [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
138 [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
139 [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
140 [PMIF_SWINF_0_STA] = 0x0C28,
141 [PMIF_SWINF_1_ACC] = 0x0C40,
142 [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
143 [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
144 [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
145 [PMIF_SWINF_1_STA] = 0x0C68,
146 [PMIF_SWINF_2_ACC] = 0x0C80,
147 [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
148 [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
149 [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
150 [PMIF_SWINF_2_STA] = 0x0CA8,
151 [PMIF_SWINF_3_ACC] = 0x0CC0,
152 [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
153 [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
154 [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
155 [PMIF_SWINF_3_STA] = 0x0CE8,
156};
157
158static const u32 mt6880_regs[] = {
159 [PMIF_INIT_DONE] = 0x0000,
160 [PMIF_INF_EN] = 0x0024,
161 [PMIF_ARB_EN] = 0x0150,
162 [PMIF_CMDISSUE_EN] = 0x03B8,
163 [PMIF_TIMER_CTRL] = 0x03E4,
164 [PMIF_SPI_MODE_CTRL] = 0x0408,
165 [PMIF_IRQ_EVENT_EN_0] = 0x0420,
166 [PMIF_IRQ_FLAG_0] = 0x0428,
167 [PMIF_IRQ_CLR_0] = 0x042C,
168 [PMIF_IRQ_EVENT_EN_1] = 0x0430,
169 [PMIF_IRQ_FLAG_1] = 0x0438,
170 [PMIF_IRQ_CLR_1] = 0x043C,
171 [PMIF_IRQ_EVENT_EN_2] = 0x0440,
172 [PMIF_IRQ_FLAG_2] = 0x0448,
173 [PMIF_IRQ_CLR_2] = 0x044C,
174 [PMIF_IRQ_EVENT_EN_3] = 0x0450,
175 [PMIF_IRQ_FLAG_3] = 0x0458,
176 [PMIF_IRQ_CLR_3] = 0x045C,
177 [PMIF_IRQ_EVENT_EN_4] = 0x0460,
178 [PMIF_IRQ_FLAG_4] = 0x0468,
179 [PMIF_IRQ_CLR_4] = 0x046C,
180 [PMIF_WDT_EVENT_EN_0] = 0x0474,
181 [PMIF_WDT_FLAG_0] = 0x0478,
182 [PMIF_WDT_EVENT_EN_1] = 0x047C,
183 [PMIF_WDT_FLAG_1] = 0x0480,
184 [PMIF_SWINF_0_ACC] = 0x0800,
185 [PMIF_SWINF_0_WDATA_31_0] = 0x0804,
186 [PMIF_SWINF_0_RDATA_31_0] = 0x0814,
187 [PMIF_SWINF_0_VLD_CLR] = 0x0824,
188 [PMIF_SWINF_0_STA] = 0x0828,
189 [PMIF_SWINF_1_ACC] = 0x0840,
190 [PMIF_SWINF_1_WDATA_31_0] = 0x0844,
191 [PMIF_SWINF_1_RDATA_31_0] = 0x0854,
192 [PMIF_SWINF_1_VLD_CLR] = 0x0864,
193 [PMIF_SWINF_1_STA] = 0x0868,
194 [PMIF_SWINF_2_ACC] = 0x0880,
195 [PMIF_SWINF_2_WDATA_31_0] = 0x0884,
196 [PMIF_SWINF_2_RDATA_31_0] = 0x0894,
197 [PMIF_SWINF_2_VLD_CLR] = 0x08A4,
198 [PMIF_SWINF_2_STA] = 0x08A8,
199 [PMIF_SWINF_3_ACC] = 0x08C0,
200 [PMIF_SWINF_3_WDATA_31_0] = 0x08C4,
201 [PMIF_SWINF_3_RDATA_31_0] = 0x08D4,
202 [PMIF_SWINF_3_VLD_CLR] = 0x08E4,
203 [PMIF_SWINF_3_STA] = 0x08E8,
204};
205
206static const u32 mt6853_regs[] = {
207 [PMIF_INIT_DONE] = 0x0000,
208 [PMIF_INF_EN] = 0x0024,
209 [PMIF_ARB_EN] = 0x0150,
210 [PMIF_CMDISSUE_EN] = 0x03B8,
211 [PMIF_TIMER_CTRL] = 0x03E4,
212 [PMIF_SPI_MODE_CTRL] = 0x0408,
213 [PMIF_IRQ_EVENT_EN_0] = 0x0420,
214 [PMIF_IRQ_FLAG_0] = 0x0428,
215 [PMIF_IRQ_CLR_0] = 0x042C,
216 [PMIF_IRQ_EVENT_EN_1] = 0x0430,
217 [PMIF_IRQ_FLAG_1] = 0x0438,
218 [PMIF_IRQ_CLR_1] = 0x043C,
219 [PMIF_IRQ_EVENT_EN_2] = 0x0440,
220 [PMIF_IRQ_FLAG_2] = 0x0448,
221 [PMIF_IRQ_CLR_2] = 0x044C,
222 [PMIF_IRQ_EVENT_EN_3] = 0x0450,
223 [PMIF_IRQ_FLAG_3] = 0x0458,
224 [PMIF_IRQ_CLR_3] = 0x045C,
225 [PMIF_IRQ_EVENT_EN_4] = 0x0460,
226 [PMIF_IRQ_FLAG_4] = 0x0468,
227 [PMIF_IRQ_CLR_4] = 0x046C,
228 [PMIF_WDT_EVENT_EN_0] = 0x0474,
229 [PMIF_WDT_FLAG_0] = 0x0478,
230 [PMIF_WDT_EVENT_EN_1] = 0x047C,
231 [PMIF_WDT_FLAG_1] = 0x0480,
232 [PMIF_SWINF_0_ACC] = 0x0C00,
233 [PMIF_SWINF_0_WDATA_31_0] = 0x0C04,
234 [PMIF_SWINF_0_RDATA_31_0] = 0x0C14,
235 [PMIF_SWINF_0_VLD_CLR] = 0x0C24,
236 [PMIF_SWINF_0_STA] = 0x0C28,
237 [PMIF_SWINF_1_ACC] = 0x0C40,
238 [PMIF_SWINF_1_WDATA_31_0] = 0x0C44,
239 [PMIF_SWINF_1_RDATA_31_0] = 0x0C54,
240 [PMIF_SWINF_1_VLD_CLR] = 0x0C64,
241 [PMIF_SWINF_1_STA] = 0x0C68,
242 [PMIF_SWINF_2_ACC] = 0x0C80,
243 [PMIF_SWINF_2_WDATA_31_0] = 0x0C84,
244 [PMIF_SWINF_2_RDATA_31_0] = 0x0C94,
245 [PMIF_SWINF_2_VLD_CLR] = 0x0CA4,
246 [PMIF_SWINF_2_STA] = 0x0CA8,
247 [PMIF_SWINF_3_ACC] = 0x0CC0,
248 [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4,
249 [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4,
250 [PMIF_SWINF_3_VLD_CLR] = 0x0CE4,
251 [PMIF_SWINF_3_STA] = 0x0CE8,
252};
253
254static const u32 mt6xxx_spmi_regs[] = {
255 [SPMI_OP_ST_CTRL] = 0x0000,
256 [SPMI_GRP_ID_EN] = 0x0004,
257 [SPMI_OP_ST_STA] = 0x0008,
258 [SPMI_SAMPL_CTRL] = 0x000c,
259 [SPMI_REQ_EN] = 0x0010,
260 [SPMI_REC_CTRL] = 0x0040,
261 [SPMI_REC0] = 0x0044,
262 [SPMI_REC1] = 0x0048,
263 [SPMI_REC2] = 0x004c,
264 [SPMI_REC3] = 0x0050,
265 [SPMI_REC4] = 0x0054,
266 [SPMI_MST_DBG] = 0x00fc,
267};
268
269static const u32 mt6880_spmi_regs[] = {
270 [SPMI_OP_ST_CTRL] = 0x0000,
271 [SPMI_GRP_ID_EN] = 0x0004,
272 [SPMI_OP_ST_STA] = 0x0008,
273 [SPMI_SAMPL_CTRL] = 0x000C,
274 [SPMI_REQ_EN] = 0x0010,
275 [SPMI_RCS_CTRL] = 0x0014,
276 [SPMI_SLV_3_0_EINT] = 0x0020,
277 [SPMI_SLV_7_4_EINT] = 0x0024,
278 [SPMI_SLV_B_8_EINT] = 0x0028,
279 [SPMI_SLV_F_C_EINT] = 0x002C,
280 [SPMI_REC_CTRL] = 0x0040,
281 [SPMI_REC0] = 0x0044,
282 [SPMI_REC1] = 0x0048,
283 [SPMI_REC2] = 0x004C,
284 [SPMI_REC3] = 0x0050,
285 [SPMI_REC4] = 0x0054,
286 [SPMI_REC_CMD_DEC] = 0x005C,
287 [SPMI_DEC_DBG] = 0x00F8,
288 [SPMI_MST_DBG] = 0x00FC,
289};
290
291static const u32 mt6853_spmi_regs[] = {
292 [SPMI_OP_ST_CTRL] = 0x0000,
293 [SPMI_GRP_ID_EN] = 0x0004,
294 [SPMI_OP_ST_STA] = 0x0008,
295 [SPMI_SAMPL_CTRL] = 0x000C,
296 [SPMI_REQ_EN] = 0x0010,
297 [SPMI_RCS_CTRL] = 0x0014,
298 [SPMI_SLV_3_0_EINT] = 0x0020,
299 [SPMI_SLV_7_4_EINT] = 0x0024,
300 [SPMI_SLV_B_8_EINT] = 0x0028,
301 [SPMI_SLV_F_C_EINT] = 0x002C,
302 [SPMI_REC_CTRL] = 0x0040,
303 [SPMI_REC0] = 0x0044,
304 [SPMI_REC1] = 0x0048,
305 [SPMI_REC2] = 0x004C,
306 [SPMI_REC3] = 0x0050,
307 [SPMI_REC4] = 0x0054,
308 [SPMI_REC_CMD_DEC] = 0x005C,
309 [SPMI_DEC_DBG] = 0x00F8,
310 [SPMI_MST_DBG] = 0x00FC,
311};
312
313enum {
314 SPMI_OP_ST_BUSY = 1,
315 SPMI_OP_ST_ACK = 0,
316 SPMI_OP_ST_NACK = 1
317};
318
319enum {
320 SPMI_RCS_SR_BIT,
321 SPMI_RCS_A_BIT
322};
323
324enum {
325 SPMI_RCS_MST_W = 1,
326 SPMI_RCS_SLV_W = 3
327};
328
329enum infra_regs {
330 MODULE_SW_CG_0_SET,
331 MODULE_SW_CG_0_CLR,
332 MODULE_SW_CG_2_SET,
333 MODULE_SW_CG_2_CLR,
334 PMICW_CLOCK_CTRL,
335 INFRA_GLOBALCON_RST2_SET,
336 INFRA_GLOBALCON_RST2_CLR,
337};
338
339static const u32 mt6xxx_infra_regs[] = {
340 [MODULE_SW_CG_0_SET] = 0x0080,
341 [MODULE_SW_CG_0_CLR] = 0x0084,
342 [MODULE_SW_CG_2_SET] = 0x00a4,
343 [MODULE_SW_CG_2_CLR] = 0x00a8,
344 [PMICW_CLOCK_CTRL] = 0x0108,
345 [INFRA_GLOBALCON_RST2_SET] = 0x0140,
346 [INFRA_GLOBALCON_RST2_CLR] = 0x0144,
347};
348
349enum topckgen_regs {
350 CLK_CFG_UPDATE,
351 CLK_CFG_UPDATE1,
352 CLK_CFG_UPDATE2,
353 CLK_CFG_3_CLR,
354 CLK_CFG_6,
355 CLK_CFG_6_SET,
356 CLK_CFG_6_CLR,
357 CLK_CFG_8_CLR,
358 CLK_CFG_15,
359 CLK_CFG_15_CLR,
360 CLK_CFG_16,
361 CLK_CFG_16_CLR,
362};
363
364static const u32 mt6xxx_topckgen_regs[] = {
365 [CLK_CFG_UPDATE] = 0x0004,
366 [CLK_CFG_UPDATE1] = 0x0008,
367 [CLK_CFG_UPDATE2] = 0x000c,
368 [CLK_CFG_3_CLR] = 0x0048,
369 [CLK_CFG_6] = 0x0070,
370 [CLK_CFG_6_SET] = 0x0074,
371 [CLK_CFG_6_CLR] = 0x0078,
372 [CLK_CFG_8_CLR] = 0x0098,
373 [CLK_CFG_15] = 0x0100,
374 [CLK_CFG_15_CLR] = 0x0108,
375 [CLK_CFG_16] = 0x0110,
376 [CLK_CFG_16_CLR] = 0x0118,
377};
378
379enum toprgu_regs {
380 WDT_SWSYSRST2,
381};
382
383static const u32 mt6xxx_toprgu_regs[] = {
384 [WDT_SWSYSRST2] = 0x0090,
385};
386
387enum {
388 /* MT6885/MT6873 series */
389 IRQ_PMIC_CMD_ERR_PARITY_ERR = 17,
390 IRQ_PMIF_ACC_VIO = 20,
391 IRQ_PMIC_ACC_VIO = 21,
392 IRQ_LAT_LIMIT_REACHED = 6,
393 IRQ_HW_MONITOR = 7,
394 IRQ_WDT = 8,
395 /* MT6853/MT6880 series */
396 IRQ_PMIF_ACC_VIO_V2 = 19,
397 IRQ_PMIC_ACC_VIO_V2 = 20,
398 IRQ_HW_MONITOR_V2 = 10,
399 IRQ_WDT_V2 = 11,
400};
401
402struct pmif_irq_desc {
403 const char *name;
404 irq_handler_t irq_handler;
405 int irq;
406};
407
408#define PMIF_IRQDESC(name) { #name, pmif_##name##_irq_handler, -1}
409
410/*
411 * pmif internal API declaration
412 */
413int __attribute__((weak)) spmi_pmif_create_attr(struct device_driver *driver);
414int __attribute__((weak)) spmi_pmif_dbg_init(struct spmi_controller *ctrl);
415void __attribute__((weak)) spmi_dump_spmimst_record_reg(struct pmif *arb);
416static int pmif_timeout_ns(struct spmi_controller *ctrl,
417 unsigned long long start_time_ns, unsigned long long timeout_time_ns);
418static void pmif_enable_soft_reset(struct pmif *arb);
419static void pmif_enable_soft_reset_p_v1(struct pmif *arb);
420static void pmif_spmi_enable_clk_set(struct pmif *arb);
421static void pmif_spmi_enable_clk_set_v2(struct pmif *arb);
422static void pmif_spmi_force_normal_mode(struct pmif *arb);
423static void pmif_spmi_enable_swinf(struct pmif *arb,
424 unsigned int chan_no, unsigned int swinf_no);
425static void pmif_spmi_enable_cmdIssue(struct pmif *arb, bool en);
426static void pmif_spmi_enable(struct pmif *arb);
427static void pmif_spmi_enable_m_v1(struct pmif *arb);
428static void pmif_spmi_enable_p_v1(struct pmif *arb);
429static void pmif_spmi_enable_m_v2(struct pmif *arb);
430static void pmif_spmi_enable_p_v2(struct pmif *arb);
431static int is_pmif_spmi_init_done(struct pmif *arb);
432static int pmif_spmi_read_cmd(struct spmi_controller *ctrl,
433 u8 opc, u8 sid, u16 addr, u8 *buf, size_t len);
434static int pmif_spmi_write_cmd(struct spmi_controller *ctrl,
435 u8 opc, u8 sid, u16 addr, const u8 *buf,
436 size_t len);
437static int mtk_spmi_config_master(struct pmif *arb,
438 unsigned int mstid, bool en);
439static int mtk_spmi_config_master_v2(struct pmif *arb,
440 unsigned int mstid, bool en);
441static int mtk_spmi_config_master_m_v1(struct pmif *arb,
442 unsigned int mstid, bool en);
443static int mtk_spmi_config_master_p_v1(struct pmif *arb,
444 unsigned int mstid, bool en);
445static int mtk_spmi_config_master_m_v2(struct pmif *arb,
446 unsigned int mstid, bool en);
447static int mtk_spmi_config_master_p_v2(struct pmif *arb,
448 unsigned int mstid, bool en);
449static int mtk_spmi_cali_rd_clock_polarity(struct pmif *arb);
450static int mtk_spmi_cali_rd_clock_polarity_m_p_v1(struct pmif *arb);
451static int mtk_spmi_cali_rd_clock_polarity_m_p_v2(struct pmif *arb);
452static int mtk_spmi_ctrl_op_st(struct spmi_controller *ctrl, u8 opc, u8 sid);
453static int mtk_spmi_enable_group_id(struct pmif *arb, u8 grpid);
454
455static struct pmif mt6885_pmif_arb = {
456 .base = 0x0,
457 .regs = mt6xxx_regs,
458 .spmimst_base = 0x0,
459 .spmimst_regs = mt6xxx_spmi_regs,
460 .infra_base = 0x0,
461 .infra_regs = mt6xxx_infra_regs,
462 .topckgen_base = 0x0,
463 .topckgen_regs = mt6xxx_topckgen_regs,
464 .toprgu_base = 0x0,
465 .toprgu_regs = mt6xxx_toprgu_regs,
466 .swinf_ch_start = 0,
467 .ap_swinf_no = 0,
468 .write = 0x0,
469 .mstid = SPMI_MASTER_0,
470 .pmifid = PMIF_PMIFID_SPMI0,
471 .spmic = 0x0,
472 .read_cmd = pmif_spmi_read_cmd,
473 .write_cmd = pmif_spmi_write_cmd,
474 .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
475 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
476 .pmif_enable_swinf = pmif_spmi_enable_swinf,
477 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
478 .pmif_enable = pmif_spmi_enable,
479 .is_pmif_init_done = is_pmif_spmi_init_done,
480 .pmif_enable_reset = pmif_enable_soft_reset,
481 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity,
482 .spmi_config_master = mtk_spmi_config_master,
483};
484
485static struct pmif mt6873_pmif_arb = {
486 .base = 0x0,
487 .regs = mt6xxx_regs,
488 .spmimst_base = 0x0,
489 .spmimst_regs = mt6xxx_spmi_regs,
490 .infra_base = 0x0,
491 .infra_regs = mt6xxx_infra_regs,
492 .topckgen_base = 0x0,
493 .topckgen_regs = mt6xxx_topckgen_regs,
494 .toprgu_base = 0x0,
495 .toprgu_regs = mt6xxx_toprgu_regs,
496 .swinf_ch_start = 0,
497 .ap_swinf_no = 0,
498 .write = 0x0,
499 .mstid = SPMI_MASTER_0,
500 .pmifid = PMIF_PMIFID_SPMI0,
501 .spmic = 0x0,
502 .read_cmd = pmif_spmi_read_cmd,
503 .write_cmd = pmif_spmi_write_cmd,
504 .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
505 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
506 .pmif_enable_swinf = pmif_spmi_enable_swinf,
507 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
508 .pmif_enable = pmif_spmi_enable,
509 .is_pmif_init_done = is_pmif_spmi_init_done,
510 .pmif_enable_reset = pmif_enable_soft_reset,
511 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity,
512 .spmi_config_master = mtk_spmi_config_master_v2,
513};
514
515static struct pmif mt6853_pmif_m_arb = {
516 .base = 0x0,
517 .regs = mt6853_regs,
518 .spmimst_base = 0x0,
519 .spmimst_regs = mt6853_spmi_regs,
520 .infra_base = 0x0,
521 .infra_regs = mt6xxx_infra_regs,
522 .topckgen_base = 0x0,
523 .topckgen_regs = mt6xxx_topckgen_regs,
524 .toprgu_base = 0x0,
525 .toprgu_regs = mt6xxx_toprgu_regs,
526 .swinf_ch_start = 0,
527 .ap_swinf_no = 0,
528 .write = 0x0,
529 .mstid = SPMI_MASTER_1,
530 .pmifid = PMIF_PMIFID_SPMI1,
531 .spmic = 0x0,
532 .read_cmd = pmif_spmi_read_cmd,
533 .write_cmd = pmif_spmi_write_cmd,
534 .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
535 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
536 .pmif_enable_swinf = pmif_spmi_enable_swinf,
537 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
538 .pmif_enable = pmif_spmi_enable_m_v1,
539 .is_pmif_init_done = is_pmif_spmi_init_done,
540 .pmif_enable_reset = pmif_enable_soft_reset,
541 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v1,
542 .spmi_config_master = mtk_spmi_config_master_m_v1,
543};
544
545static struct pmif mt6853_pmif_p_arb = {
546 .base = 0x0,
547 .regs = mt6853_regs,
548 .spmimst_base = 0x0,
549 .spmimst_regs = mt6853_spmi_regs,
550 .infra_base = 0x0,
551 .infra_regs = mt6xxx_infra_regs,
552 .topckgen_base = 0x0,
553 .topckgen_regs = mt6xxx_topckgen_regs,
554 .toprgu_base = 0x0,
555 .toprgu_regs = mt6xxx_toprgu_regs,
556 .swinf_ch_start = 0,
557 .ap_swinf_no = 0,
558 .write = 0x0,
559 .mstid = SPMI_MASTER_1,
560 .pmifid = PMIF_PMIFID_SPMI2,
561 .spmic = 0x0,
562 .read_cmd = pmif_spmi_read_cmd,
563 .write_cmd = pmif_spmi_write_cmd,
564 .pmif_enable_clk_set = pmif_spmi_enable_clk_set,
565 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
566 .pmif_enable_swinf = pmif_spmi_enable_swinf,
567 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
568 .pmif_enable = pmif_spmi_enable_p_v1,
569 .is_pmif_init_done = is_pmif_spmi_init_done,
570 .pmif_enable_reset = pmif_enable_soft_reset_p_v1,
571 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v1,
572 .spmi_config_master = mtk_spmi_config_master_p_v1,
573};
574
575static struct pmif mt6880_pmif_m_arb = {
576 .base = 0x0,
577 .regs = mt6880_regs,
578 .spmimst_base = 0x0,
579 .spmimst_regs = mt6880_spmi_regs,
580 .infra_base = 0x0,
581 .infra_regs = mt6xxx_infra_regs,
582 .topckgen_base = 0x0,
583 .topckgen_regs = mt6xxx_topckgen_regs,
584 .toprgu_base = 0x0,
585 .toprgu_regs = mt6xxx_toprgu_regs,
586 .swinf_ch_start = 0,
587 .ap_swinf_no = 0,
588 .write = 0x0,
589 .mstid = SPMI_MASTER_1,
590 .pmifid = PMIF_PMIFID_SPMI1,
591 .spmic = 0x0,
592 .read_cmd = pmif_spmi_read_cmd,
593 .write_cmd = pmif_spmi_write_cmd,
594 .pmif_enable_clk_set = pmif_spmi_enable_clk_set_v2,
595 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
596 .pmif_enable_swinf = pmif_spmi_enable_swinf,
597 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
598 .pmif_enable = pmif_spmi_enable_m_v2,
599 .is_pmif_init_done = is_pmif_spmi_init_done,
600 .pmif_enable_reset = pmif_enable_soft_reset,
601 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v2,
602 .spmi_config_master = mtk_spmi_config_master_m_v2,
603};
604
605static struct pmif mt6880_pmif_p_arb = {
606 .base = 0x0,
607 .regs = mt6880_regs,
608 .spmimst_base = 0x0,
609 .spmimst_regs = mt6880_spmi_regs,
610 .infra_base = 0x0,
611 .infra_regs = mt6xxx_infra_regs,
612 .topckgen_base = 0x0,
613 .topckgen_regs = mt6xxx_topckgen_regs,
614 .toprgu_base = 0x0,
615 .toprgu_regs = mt6xxx_toprgu_regs,
616 .swinf_ch_start = 0,
617 .ap_swinf_no = 0,
618 .write = 0x0,
619 .mstid = SPMI_MASTER_1,
620 .pmifid = PMIF_PMIFID_SPMI2,
621 .spmic = 0x0,
622 .read_cmd = pmif_spmi_read_cmd,
623 .write_cmd = pmif_spmi_write_cmd,
624 .pmif_enable_clk_set = pmif_spmi_enable_clk_set_v2,
625 .pmif_force_normal_mode = pmif_spmi_force_normal_mode,
626 .pmif_enable_swinf = pmif_spmi_enable_swinf,
627 .pmif_enable_cmdIssue = pmif_spmi_enable_cmdIssue,
628 .pmif_enable = pmif_spmi_enable_p_v2,
629 .is_pmif_init_done = is_pmif_spmi_init_done,
630 .pmif_enable_reset = pmif_enable_soft_reset_p_v1,
631 .pmif_cali_clock = mtk_spmi_cali_rd_clock_polarity_m_p_v2,
632 .spmi_config_master = mtk_spmi_config_master_p_v2,
633};
634
635static const struct of_device_id pmif_match_table[] = {
636 {
637 .compatible = "mediatek,mt6885-pmif",
638 .data = &mt6885_pmif_arb,
639 }, {
640 .compatible = "mediatek,mt6873-pmif",
641 .data = &mt6873_pmif_arb,
642 }, {
643 .compatible = "mediatek,mt6853-pmif-m",
644 .data = &mt6853_pmif_m_arb,
645 }, {
646 .compatible = "mediatek,mt6853-pmif-p",
647 .data = &mt6853_pmif_p_arb,
648 }, {
649 .compatible = "mediatek,mt6880-pmif-m",
650 .data = &mt6880_pmif_m_arb,
651 }, {
652 .compatible = "mediatek,mt6880-pmif-p",
653 .data = &mt6880_pmif_p_arb,
654 }, {
655 /* sentinel */
656 },
657};
658MODULE_DEVICE_TABLE(of, pmif_match_table);
659static struct platform_driver pmif_driver;
660
661/*
662 * pmif timeout
663 */
664#if PMIF_TIMEOUT
665static int pmif_timeout_ns(struct spmi_controller *ctrl,
666 unsigned long long start_time_ns, unsigned long long timeout_time_ns)
667{
668 unsigned long long cur_time = 0;
669 unsigned long long elapse_time = 0;
670
671 /* get current tick */
672 cur_time = sched_clock(); /* ns */
673
674 /* avoid timer over flow exiting in FPGA env */
675 if (cur_time < start_time_ns)
676 start_time_ns = cur_time;
677
678 elapse_time = cur_time - start_time_ns;
679
680 /* check if timeout */
681 if (timeout_time_ns <= elapse_time) {
682 dev_notice(&ctrl->dev,
683 "[PMIF] Timeout start time: %lld\n", start_time_ns);
684 dev_notice(&ctrl->dev,
685 "[PMIF] Timeout cur time: %lld\n", cur_time);
686 dev_notice(&ctrl->dev,
687 "[PMIF] Timeout elapse time: %lld\n", elapse_time);
688 dev_notice(&ctrl->dev,
689 "[PMIF] Timeout set timeout: %lld\n", timeout_time_ns);
690 return 1;
691 }
692 return 0;
693}
694#else
695static int pmif_timeout_ns(struct spmi_controller *ctrl,
696 unsigned long long start_time_ns, unsigned long long timeout_time_ns)
697{
698 return 0;
699}
700
701#endif
702/*
703 * pmif define for FSM
704 */
705static inline bool pmif_is_fsm_idle(struct pmif *arb)
706{
707 u32 offset = 0, reg_rdata = 0;
708
709 offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no);
710 reg_rdata = readl(arb->base + offset);
711 return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_IDLE;
712}
713
714static inline bool pmif_is_fsm_vldclr(struct pmif *arb)
715{
716 u32 offset = 0, reg_rdata = 0;
717
718 offset = arb->regs[PMIF_SWINF_0_STA] + (0x40 * arb->ap_swinf_no);
719 reg_rdata = readl(arb->base + offset);
720 return PMIF_GET_SWINF_FSM(reg_rdata) == PMIF_SWINF_FSM_WFVLDCLR;
721}
722static inline void pmif_leave_fsm_vldclr(struct pmif *arb)
723{
724 u32 offset = 0;
725
726 offset = arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no);
727 if (pmif_is_fsm_vldclr(arb))
728 writel(0x1, arb->base + offset);
729}
730
731static int pmif_wait_for_state(struct spmi_controller *ctrl,
732 bool (*fp)(struct pmif *))
733{
734 struct pmif *arb = spmi_controller_get_drvdata(ctrl);
735 unsigned long long start_time_ns = 0, timeout_ns = 0;
736
737 start_time_ns = sched_clock();
738 timeout_ns = 10000 * 1000; /* 10000us */
739
740 do {
741 if (pmif_timeout_ns(ctrl, start_time_ns, timeout_ns)) {
742 if (fp(arb)) {
743 return 0;
744 } else if (fp(arb) == 0) {
745 dev_notice(&ctrl->dev, "[PMIF] FSM Timeout\n");
746 return -ETIMEDOUT;
747 }
748 }
749 if (fp(arb))
750 return 0;
751 } while (1);
752}
753
754/*
755 * Function : pmif_readl()
756 * Description : mtk pmif controller read api
757 * Parameter :
758 * Return :
759 */
760static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg)
761{
762 return readl(arb->base + arb->regs[reg]);
763}
764
765/*
766 * Function : pmif_writel()
767 * Description : mtk pmif controller write api
768 * Parameter :
769 * Return :
770 */
771static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg)
772{
773 writel(val, arb->base + arb->regs[reg]);
774}
775/*
776 * Function : mtk_spmi_readl()
777 * Description : mtk spmi controller read api
778 * Parameter :
779 * Return :
780 */
781u32 mtk_spmi_readl(struct pmif *arb, enum spmi_regs reg)
782{
783 return readl(arb->spmimst_base + arb->spmimst_regs[reg]);
784}
785
786/*
787 * Function : mtk_spmi_writel()
788 * Description : mtk spmi controller write api
789 * Parameter :
790 * Return :
791 */
792void mtk_spmi_writel(struct pmif *arb, u32 val,
793 enum spmi_regs reg)
794{
795 writel(val, arb->spmimst_base + arb->spmimst_regs[reg]);
796}
797
798static void pmif_enable_soft_reset(struct pmif *arb)
799{
800 writel(0x1 << 14,
801 arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_SET]);
802 writel(0x1 << 14,
803 arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_CLR]);
804}
805
806static void pmif_enable_soft_reset_p_v1(struct pmif *arb)
807{
808 writel(0x1,
809 arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_SET]);
810 writel(0x1,
811 arb->infra_base + arb->infra_regs[INFRA_GLOBALCON_RST2_CLR]);
812}
813
814static void pmif_spmi_enable_clk_set(struct pmif *arb)
815{
816 /* sys_ck cg enable, turn off clock */
817 writel(0x0000000f,
818 arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_SET]);
819
820 writel((0x1 << 15) | (0x1 << 12) | (0x7 << 8),
821 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_8_CLR]);
822 writel(0x1 << 2,
823 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE1]);
824
825 /* toggle SPMI sw reset */
826 arb->pmif_enable_reset(arb);
827
828 /* sys_ck cg enable, turn on clock */
829 writel(0x0000000f,
830 arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_CLR]);
831}
832
833static void pmif_spmi_enable_clk_set_v2(struct pmif *arb)
834{
835 /* sys_ck cg enable, turn off clock */
836 writel(0x0000000f,
837 arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_SET]);
838
839#if !defined(CONFIG_FPGA_EARLY_PORTING)
840 writel((0x1 << 31) | (0x1 << 28) | (0x7 << 24),
841 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_3_CLR]);
842 writel(0x1 << 15,
843 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
844#endif
845
846 /* toggle SPMI sw reset */
847 arb->pmif_enable_reset(arb);
848
849 /* sys_ck cg enable, turn on clock */
850 writel(0x0000000f,
851 arb->infra_base + arb->infra_regs[MODULE_SW_CG_0_CLR]);
852}
853
854static void pmif_spmi_force_normal_mode(struct pmif *arb)
855{
856 /* Force SPMI in normal mode. */
857 pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) & (~(0x3 << 9)),
858 PMIF_SPI_MODE_CTRL);
859 pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) | (0x1 << 9),
860 PMIF_SPI_MODE_CTRL);
861#if defined(CONFIG_FPGA_EARLY_PORTING)
862 pmif_writel(arb, pmif_readl(arb, PMIF_SPI_MODE_CTRL) & (~(0x1 << 13)),
863 PMIF_SPI_MODE_CTRL);
864#endif
865}
866
867static void pmif_spmi_enable_swinf(struct pmif *arb, unsigned int chan_no,
868 unsigned int swinf_no)
869{
870 /* Enable swinf */
871 pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_INF_EN);
872
873 /* Enable arbitration */
874 pmif_writel(arb, 0x1 << (chan_no + swinf_no), PMIF_ARB_EN);
875
876}
877
878static void pmif_spmi_enable_cmdIssue(struct pmif *arb, bool en)
879{
880 /* Enable cmdIssue */
881 pmif_writel(arb, en, PMIF_CMDISSUE_EN);
882
883}
884
885static void pmif_spmi_enable(struct pmif *arb)
886{
887 pmif_writel(arb, 0x2F7, PMIF_INF_EN);
888 pmif_writel(arb, 0x2F7, PMIF_ARB_EN);
889 pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
890 pmif_writel(arb, 0x1, PMIF_INIT_DONE);
891}
892
893static void pmif_spmi_enable_m_v1(struct pmif *arb)
894{
895 pmif_writel(arb, 0x2F6, PMIF_INF_EN);
896 pmif_writel(arb, 0x2F6, PMIF_ARB_EN);
897 pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
898 pmif_writel(arb, 0x1, PMIF_INIT_DONE);
899}
900
901static void pmif_spmi_enable_p_v1(struct pmif *arb)
902{
903 pmif_writel(arb, 0xF1, PMIF_INF_EN);
904 pmif_writel(arb, 0xF1, PMIF_ARB_EN);
905 pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
906 pmif_writel(arb, 0x1, PMIF_INIT_DONE);
907}
908
909static void pmif_spmi_enable_m_v2(struct pmif *arb)
910{
911 pmif_writel(arb, 0x1FFF, PMIF_INF_EN);
912 pmif_writel(arb, 0x1FFF, PMIF_ARB_EN);
913 pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
914 pmif_writel(arb, 0x1, PMIF_INIT_DONE);
915}
916
917static void pmif_spmi_enable_p_v2(struct pmif *arb)
918{
919 pmif_writel(arb, 0x1FFF, PMIF_INF_EN);
920 pmif_writel(arb, 0x1FFF, PMIF_ARB_EN);
921 pmif_writel(arb, 0x3, PMIF_TIMER_CTRL);
922 pmif_writel(arb, 0x1, PMIF_INIT_DONE);
923}
924
925static int mtk_spmi_ctrl_op_st(struct spmi_controller *ctrl,
926 u8 opc, u8 sid)
927{
928 struct pmif *arb = spmi_controller_get_drvdata(ctrl);
929 u32 rdata = 0x0;
930 u8 cmd = 0;
931
932 /* Check the opcode */
933 if (opc == SPMI_CMD_RESET)
934 cmd = 0;
935 else if (opc == SPMI_CMD_SLEEP)
936 cmd = 1;
937 else if (opc == SPMI_CMD_SHUTDOWN)
938 cmd = 2;
939 else if (opc == SPMI_CMD_WAKEUP)
940 cmd = 3;
941
942 mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL);
943
944 rdata = mtk_spmi_readl(arb, SPMI_OP_ST_CTRL);
945 pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata);
946
947 do {
948 rdata = mtk_spmi_readl(arb, SPMI_OP_ST_STA);
949 pr_notice("[SPMIMST]:pmif_ctrl_op_st 0x%x\r\n", rdata);
950
951 if (((rdata >> 0x1) & SPMI_OP_ST_NACK) == SPMI_OP_ST_NACK) {
952 spmi_dump_spmimst_record_reg(arb);
953 break;
954 }
955 } while ((rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY);
956
957 return 0;
958}
959
960/* Non-data command */
961static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
962{
963 return mtk_spmi_ctrl_op_st(ctrl, opc, sid);
964}
965
966static int mtk_spmi_enable_group_id(struct pmif *arb, u8 grpid)
967{
968 mtk_spmi_writel(arb, 0x1 << grpid, SPMI_GRP_ID_EN);
969
970 return 0;
971}
972
973static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
974 u16 addr, u8 *buf, size_t len)
975{
976 struct pmif *arb = spmi_controller_get_drvdata(ctrl);
977 int ret = 0, write = 0x0;
978 u32 offset = 0, data = 0;
979 u8 bc = len - 1;
980 unsigned long flags;
981
982 /* Check for argument validation. */
983 if ((arb->ap_swinf_no & ~(0x3)) != 0x0)
984 return -EINVAL;
985
986 if ((arb->pmifid & ~(0x3)) != 0x0)
987 return -EINVAL;
988
989 if ((sid & ~(0xf)) != 0x0)
990 return -EINVAL;
991
992 /* Check the opcode */
993 if (opc >= 0x60 && opc <= 0x7F)
994 opc = PMIF_CMD_REG;
995 else if (opc >= 0x20 && opc <= 0x2F)
996 opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */
997 else if (opc >= 0x38 && opc <= 0x3F)
998 opc = PMIF_CMD_EXT_REG_LONG;
999 else
1000 return -EINVAL;
1001
1002 raw_spin_lock_irqsave(&arb->lock, flags);
1003 /* Wait for Software Interface FSM state to be IDLE. */
1004 ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle);
1005 if (ret) {
1006 pmif_leave_fsm_vldclr(arb);
1007 raw_spin_unlock_irqrestore(&arb->lock, flags);
1008 return ret;
1009 }
1010 /* Send the command. */
1011 offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no);
1012 writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr,
1013 arb->base + offset);
1014
1015 /* Wait for Software Interface FSM state to be WFVLDCLR,
1016 *
1017 * read the data and clear the valid flag.
1018 */
1019 if (write == 0) {
1020 ret = pmif_wait_for_state(ctrl, pmif_is_fsm_vldclr);
1021 if (ret) {
1022 raw_spin_unlock_irqrestore(&arb->lock, flags);
1023 return ret;
1024 }
1025 offset =
1026 arb->regs[PMIF_SWINF_0_RDATA_31_0] + (0x40 * arb->ap_swinf_no);
1027
1028 data = readl(arb->base + offset);
1029 memcpy(buf, &data, (bc & 3) + 1);
1030 offset =
1031 arb->regs[PMIF_SWINF_0_VLD_CLR] + (0x40 * arb->ap_swinf_no);
1032
1033 writel(0x1, arb->base + offset);
1034 }
1035
1036 raw_spin_unlock_irqrestore(&arb->lock, flags);
1037
1038 return 0x0;
1039}
1040
1041static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
1042 u16 addr, const u8 *buf, size_t len)
1043{
1044 struct pmif *arb = spmi_controller_get_drvdata(ctrl);
1045 int ret = 0, write = 0x1;
1046 u32 offset = 0, data = 0;
1047 u8 bc = len - 1;
1048 unsigned long flags = 0;
1049
1050 /* Check for argument validation. */
1051 if ((arb->ap_swinf_no & ~(0x3)) != 0x0)
1052 return -EINVAL;
1053
1054 if ((arb->pmifid & ~(0x3)) != 0x0)
1055 return -EINVAL;
1056
1057 if ((sid & ~(0xf)) != 0x0)
1058 return -EINVAL;
1059
1060 /* Check the opcode */
1061 if (opc >= 0x40 && opc <= 0x5F)
1062 opc = PMIF_CMD_REG;
1063 else if (opc <= 0x0F)
1064 opc = PMIF_CMD_EXT_REG_LONG; /* wk1 opc = PMIF_CMD_EXT_REG; */
1065 else if (opc >= 0x30 && opc <= 0x37)
1066 opc = PMIF_CMD_EXT_REG_LONG;
1067 else if (opc >= 0x80)
1068 opc = PMIF_CMD_REG_0;
1069 else
1070 return -EINVAL;
1071
1072 raw_spin_lock_irqsave(&arb->lock, flags);
1073
1074 /* Wait for Software Interface FSM state to be IDLE. */
1075 ret = pmif_wait_for_state(ctrl, pmif_is_fsm_idle);
1076 if (ret) {
1077 pmif_leave_fsm_vldclr(arb);
1078 raw_spin_unlock_irqrestore(&arb->lock, flags);
1079 return ret;
1080 }
1081 /* Set the write data. */
1082 offset = arb->regs[PMIF_SWINF_0_WDATA_31_0] + (0x40 * arb->ap_swinf_no);
1083 if (write == 1) {
1084 memcpy(&data, buf, (bc & 3) + 1);
1085 writel(data, arb->base + offset);
1086 }
1087
1088 /* Send the command. */
1089 offset = arb->regs[PMIF_SWINF_0_ACC] + (0x40 * arb->ap_swinf_no);
1090 writel((opc << 30) | (write << 29) | (sid << 24) | (bc << 16) | addr,
1091 arb->base + offset);
1092 raw_spin_unlock_irqrestore(&arb->lock, flags);
1093
1094 return 0x0;
1095}
1096
1097int is_pmif_spmi_init_done(struct pmif *arb)
1098{
1099 return pmif_readl(arb, PMIF_INIT_DONE) & 0x1;
1100}
1101
1102static int mtk_spmi_config_master(struct pmif *arb,
1103 unsigned int mstid, bool en)
1104{
1105 /* Software reset */
1106 writel(0x85 << 24 | 0x1 << 4,
1107 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1108
1109 writel(0x7 | (0x1 << 4) | (0x1 << 7),
1110 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_16_CLR]);
1111 writel(0x1 << 2,
1112 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
1113
1114 /* Software reset */
1115 writel(0x85 << 24,
1116 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1117
1118 /* Enable SPMI */
1119 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1120
1121 return 0;
1122}
1123
1124static int mtk_spmi_config_master_v2(struct pmif *arb,
1125 unsigned int mstid, bool en)
1126{
1127 /* Software reset */
1128 writel(0x85 << 24 | 0x1 << 4,
1129 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1130
1131 writel((0x7 << 8) | (0x1 << 12) | (0x1 << 15),
1132 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15_CLR]);
1133 writel(0x1 << 30,
1134 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
1135
1136 /* Software reset */
1137 writel(0x85 << 24,
1138 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1139
1140 /* Enable SPMI */
1141 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1142
1143 return 0;
1144}
1145
1146static int mtk_spmi_config_master_m_v1(struct pmif *arb,
1147 unsigned int mstid, bool en)
1148{
1149 /* Software reset */
1150 writel(0x85 << 24 | 0x3 << 3,
1151 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1152
1153 writel((0x7 << 8) | (0x1 << 12) | (0x1 << 15),
1154 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15_CLR]);
1155 writel(0x1 << 30,
1156 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE2]);
1157
1158 /* Software reset */
1159 writel(0x85 << 24,
1160 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1161
1162 /* Enable master rcs */
1163 mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
1164 /* Enable SPMI */
1165 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1166
1167 return 0;
1168}
1169
1170static int mtk_spmi_config_master_p_v1(struct pmif *arb,
1171 unsigned int mstid, bool en)
1172{
1173 /* Enable master rcs */
1174 mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
1175 /* Enable SPMI */
1176 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1177
1178 return 0;
1179}
1180
1181static int mtk_spmi_config_master_m_v2(struct pmif *arb,
1182 unsigned int mstid, bool en)
1183{
1184 /* Software reset */
1185 writel(0x85 << 24 | 0x1 << 4,
1186 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1187
1188#if !defined(CONFIG_FPGA_EARLY_PORTING)
1189 writel((0x7 << 16) | (0x1 << 20) | (0x1 << 23),
1190 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_CLR]);
1191 writel(0x3 << 16,
1192 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_SET]);
1193 writel(0x1 << 26,
1194 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
1195#endif
1196
1197 /* Software reset */
1198 writel(0x85 << 24,
1199 arb->toprgu_base + arb->toprgu_regs[WDT_SWSYSRST2]);
1200
1201 /* Enable master rcs */
1202 mtk_spmi_writel(arb, 0x14 | arb->mstid, SPMI_RCS_CTRL);
1203 /* Enable SPMI */
1204 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1205
1206 return 0;
1207}
1208
1209static int mtk_spmi_config_master_p_v2(struct pmif *arb,
1210 unsigned int mstid, bool en)
1211{
1212 /* no need to reset SPMI master again */
1213
1214#if !defined(CONFIG_FPGA_EARLY_PORTING)
1215 writel((0xF << 24) | (0x1 << 28) | (0x1 << 31),
1216 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_CLR]);
1217 writel(0x7 << 24,
1218 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6_SET]);
1219 writel(0x1 << 27,
1220 arb->topckgen_base + arb->topckgen_regs[CLK_CFG_UPDATE]);
1221#endif
1222 /* Enable SPMI */
1223 mtk_spmi_writel(arb, en, SPMI_REQ_EN);
1224
1225 return 0;
1226}
1227
1228static int mtk_spmi_cali_rd_clock_polarity(struct pmif *arb)
1229{
1230#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
1231 unsigned int dly = 0, pol = 0;
1232#else
1233 unsigned int dly = 1, pol = 1;
1234#endif
1235
1236 /* Indicate sampling clock polarity, 1: Positive 0: Negative */
1237 mtk_spmi_writel(arb, (dly << 0x1) | pol, SPMI_SAMPL_CTRL);
1238
1239 return 0;
1240}
1241
1242static int mtk_spmi_cali_rd_clock_polarity_m_p_v1(struct pmif *arb)
1243{
1244#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
1245 unsigned int dly = 0, pol = 0;
1246#else
1247 unsigned int dly = 0, pol = 1;
1248#endif
1249
1250 /* Indicate sampling clock polarity, 1: Positive 0: Negative */
1251 mtk_spmi_writel(arb, ((dly + 1) << 0x4) | (dly << 0x1) | pol,
1252 SPMI_SAMPL_CTRL);
1253
1254 return 0;
1255}
1256
1257static int mtk_spmi_cali_rd_clock_polarity_m_p_v2(struct pmif *arb)
1258{
1259#if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING)
1260 unsigned int dly = 1, pol = 0;
1261#else
1262 unsigned int dly = 0, pol = 1;
1263#endif
1264
1265 /* Indicate sampling clock polarity, 1: Positive 0: Negative */
1266 mtk_spmi_writel(arb, ((dly + 1) << 0x4) | (dly << 0x1) | pol,
1267 SPMI_SAMPL_CTRL);
1268
1269 return 0;
1270}
1271
1272/*
1273 * PMIF Exception IRQ Handler
1274 */
1275static void pmif_cmd_err_parity_err_irq_handler(int irq, void *data)
1276{
1277 spmi_dump_spmimst_all_reg();
1278 spmi_dump_pmif_record_reg();
1279 aee_kernel_warning("PMIF:parity error", "PMIF");
1280}
1281
1282static void pmif_pmif_acc_vio_irq_handler(int irq, void *data)
1283{
1284 spmi_dump_pmif_acc_vio_reg();
1285 aee_kernel_warning("PMIF:pmif_acc_vio", "PMIF");
1286}
1287
1288static void pmif_pmic_acc_vio_irq_handler(int irq, void *data)
1289{
1290 spmi_dump_pmic_acc_vio_reg();
1291 aee_kernel_warning("PMIF:pmic_acc_vio", "PMIF");
1292}
1293
1294static void pmif_lat_limit_reached_irq_handler(int irq, void *data)
1295{
1296 spmi_dump_pmif_busy_reg();
1297 spmi_dump_pmif_record_reg();
1298}
1299
1300static void pmif_hw_monitor_irq_handler(int irq, void *data)
1301{
1302 spmi_dump_pmif_record_reg();
1303 aee_kernel_warning("PMIF:pmif_hw_monitor_match", "PMIF");
1304}
1305
1306static void pmif_wdt_irq_handler(int irq, void *data)
1307{
1308 spmi_dump_pmif_busy_reg();
1309 spmi_dump_pmif_record_reg();
1310 spmi_dump_wdt_reg();
1311}
1312
1313static irqreturn_t pmif_event_0_irq_handler(int irq, void *data)
1314{
1315 struct pmif *arb = data;
1316 int irq_f = 0, idx = 0;
1317
1318 __pm_stay_awake(arb->pmifThread_lock);
1319 mutex_lock(&arb->pmif_mutex);
1320 irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_0);
1321 if (irq_f == 0) {
1322 mutex_unlock(&arb->pmif_mutex);
1323 __pm_relax(arb->pmifThread_lock);
1324 return IRQ_NONE;
1325 }
1326
1327 for (idx = 0; idx < 31; idx++) {
1328 if ((irq_f & (0x1 << idx)) != 0) {
1329 switch (idx) {
1330 default:
1331 pr_notice("%s IRQ[%d] triggered\n",
1332 __func__, idx);
1333 spmi_dump_pmif_record_reg();
1334 break;
1335 }
1336 pmif_writel(arb, irq_f, PMIF_IRQ_CLR_0);
1337 break;
1338 }
1339 }
1340 mutex_unlock(&arb->pmif_mutex);
1341 __pm_relax(arb->pmifThread_lock);
1342
1343 return IRQ_HANDLED;
1344}
1345
1346static irqreturn_t pmif_event_1_irq_handler(int irq, void *data)
1347{
1348 struct pmif *arb = data;
1349 int irq_f = 0, idx = 0;
1350
1351 __pm_stay_awake(arb->pmifThread_lock);
1352 mutex_lock(&arb->pmif_mutex);
1353 irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_1);
1354 if (irq_f == 0) {
1355 mutex_unlock(&arb->pmif_mutex);
1356 __pm_relax(arb->pmifThread_lock);
1357 return IRQ_NONE;
1358 }
1359
1360 for (idx = 0; idx < 31; idx++) {
1361 if ((irq_f & (0x1 << idx)) != 0) {
1362 switch (idx) {
1363 default:
1364 pr_notice("%s IRQ[%d] triggered\n",
1365 __func__, idx);
1366 spmi_dump_pmif_record_reg();
1367 break;
1368 }
1369 pmif_writel(arb, irq_f, PMIF_IRQ_CLR_1);
1370 break;
1371 }
1372 }
1373 mutex_unlock(&arb->pmif_mutex);
1374 __pm_relax(arb->pmifThread_lock);
1375
1376 return IRQ_HANDLED;
1377}
1378
1379static irqreturn_t pmif_event_2_irq_handler(int irq, void *data)
1380{
1381 struct pmif *arb = data;
1382 int irq_f = 0, idx = 0;
1383
1384 __pm_stay_awake(arb->pmifThread_lock);
1385 mutex_lock(&arb->pmif_mutex);
1386 irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_2);
1387 if (irq_f == 0) {
1388 mutex_unlock(&arb->pmif_mutex);
1389 __pm_relax(arb->pmifThread_lock);
1390 return IRQ_NONE;
1391 }
1392
1393 for (idx = 0; idx < 31; idx++) {
1394 if ((irq_f & (0x1 << idx)) != 0) {
1395 switch (idx) {
1396 case IRQ_PMIC_CMD_ERR_PARITY_ERR:
1397 pmif_cmd_err_parity_err_irq_handler(irq, data);
1398 break;
1399 case IRQ_PMIF_ACC_VIO:
1400 pmif_pmif_acc_vio_irq_handler(irq, data);
1401 break;
1402 case IRQ_PMIC_ACC_VIO:
1403 pmif_pmic_acc_vio_irq_handler(irq, data);
1404 break;
1405 default:
1406 pr_notice("%s IRQ[%d] triggered\n",
1407 __func__, idx);
1408 spmi_dump_pmif_record_reg();
1409 break;
1410 }
1411 pmif_writel(arb, irq_f, PMIF_IRQ_CLR_2);
1412 break;
1413 }
1414 }
1415 mutex_unlock(&arb->pmif_mutex);
1416 __pm_relax(arb->pmifThread_lock);
1417
1418 return IRQ_HANDLED;
1419}
1420
1421static irqreturn_t pmif_event_3_irq_handler(int irq, void *data)
1422{
1423 struct pmif *arb = data;
1424 int irq_f = 0, idx = 0;
1425
1426 __pm_stay_awake(arb->pmifThread_lock);
1427 mutex_lock(&arb->pmif_mutex);
1428 irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_3);
1429 if (irq_f == 0) {
1430 mutex_unlock(&arb->pmif_mutex);
1431 __pm_relax(arb->pmifThread_lock);
1432 return IRQ_NONE;
1433 }
1434
1435 for (idx = 0; idx < 31; idx++) {
1436 if ((irq_f & (0x1 << idx)) != 0) {
1437 switch (idx) {
1438 case IRQ_LAT_LIMIT_REACHED:
1439 pmif_lat_limit_reached_irq_handler(irq, data);
1440 break;
1441 case IRQ_HW_MONITOR:
1442 pmif_hw_monitor_irq_handler(irq, data);
1443 break;
1444 case IRQ_WDT:
1445 pmif_wdt_irq_handler(irq, data);
1446 break;
1447 case IRQ_PMIF_ACC_VIO_V2:
1448 pmif_pmif_acc_vio_irq_handler(irq, data);
1449 break;
1450 case IRQ_PMIC_ACC_VIO_V2:
1451 pmif_pmic_acc_vio_irq_handler(irq, data);
1452 break;
1453 default:
1454 pr_notice("%s IRQ[%d] triggered\n",
1455 __func__, idx);
1456 spmi_dump_pmif_record_reg();
1457 break;
1458 }
1459 pmif_writel(arb, irq_f, PMIF_IRQ_CLR_3);
1460 break;
1461 }
1462 }
1463 mutex_unlock(&arb->pmif_mutex);
1464 __pm_relax(arb->pmifThread_lock);
1465
1466 return IRQ_HANDLED;
1467}
1468
1469static irqreturn_t pmif_event_4_irq_handler(int irq, void *data)
1470{
1471 struct pmif *arb = data;
1472 int irq_f = 0, idx = 0;
1473
1474 __pm_stay_awake(arb->pmifThread_lock);
1475 mutex_lock(&arb->pmif_mutex);
1476 irq_f = pmif_readl(arb, PMIF_IRQ_FLAG_4);
1477 if (irq_f == 0) {
1478 mutex_unlock(&arb->pmif_mutex);
1479 __pm_relax(arb->pmifThread_lock);
1480 return IRQ_NONE;
1481 }
1482
1483 for (idx = 0; idx < 31; idx++) {
1484 if ((irq_f & (0x1 << idx)) != 0) {
1485 switch (idx) {
1486 default:
1487 pr_notice("%s IRQ[%d] triggered\n",
1488 __func__, idx);
1489 spmi_dump_pmif_record_reg();
1490 break;
1491 }
1492 pmif_writel(arb, irq_f, PMIF_IRQ_CLR_4);
1493 break;
1494 }
1495 }
1496 mutex_unlock(&arb->pmif_mutex);
1497 __pm_relax(arb->pmifThread_lock);
1498
1499 return IRQ_HANDLED;
1500}
1501
1502static struct pmif_irq_desc pmif_event_irq[] = {
1503 PMIF_IRQDESC(event_0),
1504 PMIF_IRQDESC(event_1),
1505 PMIF_IRQDESC(event_2),
1506 PMIF_IRQDESC(event_3),
1507 PMIF_IRQDESC(event_4),
1508};
1509
1510static void pmif_irq_register(struct platform_device *pdev,
1511 struct pmif *arb, int irq)
1512{
1513 int i = 0, ret = 0;
1514 u32 irq_event_en[5] = {0};
1515
1516 for (i = 0; i < ARRAY_SIZE(pmif_event_irq); i++) {
1517 if (!pmif_event_irq[i].name)
1518 continue;
1519 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1520 pmif_event_irq[i].irq_handler,
1521 IRQF_TRIGGER_HIGH | IRQF_ONESHOT | IRQF_SHARED,
1522 pmif_event_irq[i].name, arb);
1523 if (ret < 0) {
1524 dev_notice(&pdev->dev, "request %s irq fail\n",
1525 pmif_event_irq[i].name);
1526 continue;
1527 }
1528 pmif_event_irq[i].irq = irq;
1529 }
1530
1531 ret = of_property_read_u32_array(pdev->dev.of_node, "irq_event_en",
1532 irq_event_en, ARRAY_SIZE(irq_event_en));
1533
1534 pmif_writel(arb, irq_event_en[0] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_0),
1535 PMIF_IRQ_EVENT_EN_0);
1536 pmif_writel(arb, irq_event_en[1] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_1),
1537 PMIF_IRQ_EVENT_EN_1);
1538 pmif_writel(arb, irq_event_en[2] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_2),
1539 PMIF_IRQ_EVENT_EN_2);
1540 pmif_writel(arb, irq_event_en[3] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_3),
1541 PMIF_IRQ_EVENT_EN_3);
1542 pmif_writel(arb, irq_event_en[4] | pmif_readl(arb, PMIF_IRQ_EVENT_EN_4),
1543 PMIF_IRQ_EVENT_EN_4);
1544}
1545
1546static void rcs_irq_lock(struct irq_data *data)
1547{
1548 struct pmif *arb = irq_data_get_irq_chip_data(data);
1549
1550 mutex_lock(&arb->rcs_irqlock);
1551}
1552
1553static void rcs_irq_sync_unlock(struct irq_data *data)
1554{
1555 struct pmif *arb = irq_data_get_irq_chip_data(data);
1556
1557 mutex_unlock(&arb->rcs_irqlock);
1558}
1559
1560static void rcs_irq_enable(struct irq_data *data)
1561{
1562 unsigned int hwirq = irqd_to_hwirq(data);
1563 struct pmif *arb = irq_data_get_irq_chip_data(data);
1564
1565 arb->rcs_enable_hwirq[hwirq] = true;
1566}
1567
1568static void rcs_irq_disable(struct irq_data *data)
1569{
1570 unsigned int hwirq = irqd_to_hwirq(data);
1571 struct pmif *arb = irq_data_get_irq_chip_data(data);
1572
1573 arb->rcs_enable_hwirq[hwirq] = false;
1574}
1575
1576static const struct irq_chip rcs_irq_chip = {
1577 .name = "rcs_irq",
1578 .irq_bus_lock = rcs_irq_lock,
1579 .irq_bus_sync_unlock = rcs_irq_sync_unlock,
1580 .irq_enable = rcs_irq_enable,
1581 .irq_disable = rcs_irq_disable,
1582};
1583
1584static int rcs_irq_map(struct irq_domain *d, unsigned int virq,
1585 irq_hw_number_t hw)
1586{
1587 struct pmif *arb = d->host_data;
1588
1589 irq_set_chip_data(virq, arb);
1590 irq_set_chip(virq, &arb->irq_chip);
1591 irq_set_nested_thread(virq, 1);
1592 irq_set_parent(virq, arb->rcs_irq);
1593 irq_set_noprobe(virq);
1594
1595 return 0;
1596}
1597
1598static const struct irq_domain_ops rcs_irq_domain_ops = {
1599 .map = rcs_irq_map,
1600 .xlate = irq_domain_xlate_onetwocell,
1601};
1602
1603static irqreturn_t rcs_irq_handler(int irq, void *data)
1604{
1605 struct pmif *arb = data;
1606 unsigned int slv_irq_sta;
1607 int i;
1608
1609 for (i = 0; i < SPMI_MAX_SLAVE_ID; i++) {
1610 slv_irq_sta = mtk_spmi_readl(arb, SPMI_SLV_3_0_EINT + (i / 4));
rjw2e8229f2022-02-15 21:08:12 +0800[diff] [blame]1611 // Need to use 0xFF to clear SPMI_SLV_x_x_EINT before
1612 // callback to pmic, since pmic may rcs to master again in the
1613 // callback function, and we also need to deal this request.
1614 // If we clear after the callback,
1615 // then we may miss this request.
1616 mtk_spmi_writel(arb, (0xFF << ((i % 4) * 8)),
1617 SPMI_SLV_3_0_EINT + (i / 4));
1618
1619 slv_irq_sta = (slv_irq_sta >> ((i % 4) * 8)) & 0xFF;
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1620 if (arb->rcs_enable_hwirq[i] && slv_irq_sta) {
1621 dev_info(&arb->spmic->dev,
1622 "hwirq=%d, sta=0x%x\n", i, slv_irq_sta);
1623 handle_nested_irq(irq_find_mapping(arb->domain, i));
1624 }
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1625 }
1626 return IRQ_HANDLED;
1627}
1628
1629static int rcs_irq_register(struct platform_device *pdev,
1630 struct pmif *arb, int irq)
1631{
1632 int i, ret = 0;
1633
1634 mutex_init(&arb->rcs_irqlock);
1635 arb->rcs_enable_hwirq = devm_kcalloc(&pdev->dev, SPMI_MAX_SLAVE_ID,
1636 sizeof(*arb->rcs_enable_hwirq),
1637 GFP_KERNEL);
1638 if (!arb->rcs_enable_hwirq)
1639 return -ENOMEM;
1640
1641 arb->irq_chip = rcs_irq_chip;
1642 arb->domain = irq_domain_add_linear(pdev->dev.of_node,
1643 SPMI_MAX_SLAVE_ID,
1644 &rcs_irq_domain_ops, arb);
1645 if (!arb->domain) {
1646 dev_notice(&pdev->dev, "Failed to create IRQ domain\n");
1647 return -ENODEV;
1648 }
1649 /* clear all slave irq status */
1650 for (i = 0; i < SPMI_MAX_SLAVE_ID; i++) {
1651 mtk_spmi_writel(arb, (0xFF << ((i % 4) * 8)),
1652 SPMI_SLV_3_0_EINT + (i / 4));
1653 }
1654 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1655 rcs_irq_handler, IRQF_ONESHOT,
1656 rcs_irq_chip.name, arb);
1657 if (ret < 0) {
1658 dev_notice(&pdev->dev, "Failed to request IRQ=%d, ret = %d\n",
1659 irq, ret);
1660 return ret;
1661 }
1662 enable_irq_wake(irq);
1663
1664 return ret;
1665}
1666
1667static int mtk_spmimst_init(struct platform_device *pdev, struct pmif *arb)
1668{
1669 struct resource *res = NULL;
1670 int err = 0;
1671
1672 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spmimst");
1673 arb->spmimst_base = devm_ioremap_resource(&pdev->dev, res);
1674 if (IS_ERR(arb->spmimst_base)) {
1675 err = PTR_ERR(arb->spmimst_base);
1676 return err;
1677 }
1678
1679 err = of_property_read_u32(pdev->dev.of_node, "grpid", &arb->grpid);
1680 if (err) {
1681 dev_notice(&pdev->dev, "[SPMIMST]:grpid unspecified.\n");
1682 return -EINVAL;
1683 }
1684 /* set group id */
1685 mtk_spmi_enable_group_id(arb, arb->grpid);
1686
1687 /* if spmimst not enabled, enable it */
1688 if ((mtk_spmi_readl(arb, SPMI_REQ_EN) & 0x1) != 0x1) {
1689 dev_info(&pdev->dev, "[SPMIMST]:enable spmimst.\n");
1690 arb->spmi_config_master(arb, arb->mstid, true);
1691 arb->pmif_cali_clock(arb);
1692 }
1693 pr_notice("[SPMIMST]:%s done\n", __func__);
1694
1695 return 0;
1696}
1697
1698
1699static int pmif_probe(struct platform_device *pdev)
1700{
1701 struct device_node *node = NULL;
1702 const struct of_device_id *of_id =
1703 of_match_device(pmif_match_table, &pdev->dev);
1704 struct spmi_controller *ctrl = NULL;
1705 struct pmif *arb = NULL;
1706 struct resource *res = NULL;
1707 u32 swinf_ch_start = 0, ap_swinf_no = 0;
1708#if !defined(CONFIG_FPGA_EARLY_PORTING)
1709 int pmif_clk26m = 0, spmimst_clk = 0;
1710#endif
1711 int err = 0;
1712
1713#if PMIF_BRINGUP
1714 dev_notice(&pdev->dev, "[PMIF]bringup do nothing\n");
1715 return 0;
1716#endif
1717 if (!of_id) {
1718 dev_notice(&pdev->dev, "[PMIF]:Error: No device match found\n");
1719 return -ENODEV;
1720 }
1721
1722 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
1723 if (!ctrl)
1724 return -ENOMEM;
1725
1726 /* re-assign of_id->data */
1727 spmi_controller_set_drvdata(ctrl, (void *)of_id->data);
1728 arb = spmi_controller_get_drvdata(ctrl);
1729 arb->spmic = ctrl;
1730
1731 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmif");
1732 arb->base = devm_ioremap_resource(&pdev->dev, res);
1733 if (IS_ERR(arb->base)) {
1734 err = PTR_ERR(arb->base);
1735 goto err_put_ctrl;
1736 }
1737 /* pmif is not initialized, just init once */
1738 node = of_find_compatible_node(NULL, NULL, "mediatek,infracfg_ao");
1739 arb->infra_base = of_iomap(node, 0);
1740 if (IS_ERR(arb->infra_base)) {
1741 err = PTR_ERR(arb->infra_base);
1742 goto err_put_ctrl;
1743 }
1744
1745 node = of_find_compatible_node(NULL, NULL, "mediatek,topckgen");
1746 arb->topckgen_base = of_iomap(node, 0);
1747 if (IS_ERR(arb->topckgen_base)) {
1748 err = PTR_ERR(arb->topckgen_base);
1749 goto err_put_ctrl;
1750 }
1751
1752 node = of_find_compatible_node(NULL, NULL, "mediatek,toprgu");
1753 arb->toprgu_base = of_iomap(node, 0);
1754 if (IS_ERR(arb->toprgu_base)) {
1755 err = PTR_ERR(arb->toprgu_base);
1756 goto err_put_ctrl;
1757 }
1758#if !defined(CONFIG_FPGA_EARLY_PORTING)
1759 /* get pmif infracfg_ao clock */
1760 arb->pmif_sys_ck = devm_clk_get(&pdev->dev, "pmif_sys_ck");
1761 if (IS_ERR(arb->pmif_sys_ck)) {
1762 dev_notice(&pdev->dev, "[PMIF]:failed to get ap clock: %ld\n",
1763 PTR_ERR(arb->pmif_sys_ck));
1764 return PTR_ERR(arb->pmif_sys_ck);
1765 }
1766
1767 arb->pmif_tmr_ck = devm_clk_get(&pdev->dev, "pmif_tmr_ck");
1768 if (IS_ERR(arb->pmif_tmr_ck)) {
1769 dev_notice(&pdev->dev, "[PMIF]:failed to get tmr clock: %ld\n",
1770 PTR_ERR(arb->pmif_tmr_ck));
1771 return PTR_ERR(arb->pmif_tmr_ck);
1772 }
1773
1774 /* get pmif topckgen clock */
1775 arb->pmif_clk_mux = devm_clk_get(&pdev->dev, "pmif_clk_mux");
1776 if (IS_ERR(arb->pmif_clk_mux)) {
1777 dev_notice(&pdev->dev, "[PMIF]:failed to get clock: %ld\n",
1778 PTR_ERR(arb->pmif_clk_mux));
1779 return PTR_ERR(arb->pmif_clk_mux);
1780 }
1781 /* now enable pmif/spmimst clock */
1782 pmif_clk26m =
1783 readl(arb->infra_base + arb->infra_regs[PMICW_CLOCK_CTRL]);
1784
1785 if ((pmif_clk26m & 0x1) == 0x1) {
1786 arb->pmif_clk26m = devm_clk_get(&pdev->dev, "pmif_clk26m");
1787 if (IS_ERR(arb->pmif_clk26m)) {
1788 dev_notice(&pdev->dev,
1789 "[PMIF]:failed to get clock: %ld\n",
1790 PTR_ERR(arb->pmif_clk26m));
1791 return PTR_ERR(arb->pmif_clk26m);
1792 }
1793 dev_info(&pdev->dev, "[PMIF]:enable clk26m.\n");
1794 err = clk_prepare_enable(arb->pmif_clk26m);
1795 if (err)
1796 return err;
1797 } else {
1798 arb->pmif_clk_mux_parent = devm_clk_get(&pdev->dev,
1799 "pmif_clk_osc_d10");
1800 dev_info(&pdev->dev, "[PMIF]:enable ulposc1 osc d10.\n");
1801 if (IS_ERR(arb->pmif_clk_mux_parent)) {
1802 dev_notice(&pdev->dev,
1803 "[PMIF]:failed to get clock: %ld\n",
1804 PTR_ERR(arb->pmif_clk_mux_parent));
1805 return PTR_ERR(arb->pmif_clk_mux_parent);
1806 }
1807 err = clk_prepare_enable(arb->pmif_clk_mux);
1808 if (err)
1809 return err;
1810 err = clk_set_parent(arb->pmif_clk_mux,
1811 arb->pmif_clk_mux_parent);
1812 if (err)
1813 return err;
1814 }
1815 err = clk_prepare_enable(arb->pmif_sys_ck);
1816 if (err)
1817 return err;
1818 err = clk_prepare_enable(arb->pmif_tmr_ck);
1819 if (err)
1820 return err;
1821
1822 /* get spmimst topckgen clock */
1823 arb->spmimst_clk_mux = devm_clk_get(&pdev->dev, "spmimst_clk_mux");
1824 if (IS_ERR(arb->spmimst_clk_mux)) {
1825 dev_notice(&pdev->dev, "[SPMIMST]:failed to get clock: %ld\n",
1826 PTR_ERR(arb->spmimst_clk_mux));
1827 return PTR_ERR(arb->spmimst_clk_mux);
1828 }
1829 if (of_device_is_compatible(ctrl->dev.parent->of_node,
1830 "mediatek,mt6885-pmif")) {
1831 spmimst_clk =
1832 readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_16]);
1833 spmimst_clk = 0x7;
1834 } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
1835 "mediatek,mt6880-pmif-m")) {
1836 spmimst_clk =
1837 readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6]);
1838 spmimst_clk = (spmimst_clk >> 16) & 0x7;
1839 } else if (of_device_is_compatible(ctrl->dev.parent->of_node,
1840 "mediatek,mt6880-pmif-p")) {
1841 spmimst_clk =
1842 readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_6]);
1843 spmimst_clk = (spmimst_clk >> 24) & 0xF;
1844 } else {
1845 spmimst_clk =
1846 readl(arb->topckgen_base + arb->topckgen_regs[CLK_CFG_15]);
1847 spmimst_clk = (spmimst_clk >> 0x8) & 0x7;
1848 }
1849 switch (spmimst_clk) {
1850 case 0:
1851 arb->spmimst_clk_mux_parent =
1852 devm_clk_get(&pdev->dev, "spmimst_clk26m");
1853 dev_info(&pdev->dev, "[SPMIMST]:enable clk26m.\n");
1854 break;
1855 case 3:
1856 arb->spmimst_clk_mux_parent =
1857 devm_clk_get(&pdev->dev, "spmimst_clk_osc_d10");
1858 dev_info(&pdev->dev, "[SPMIMST]:enable ulposc1 osc d10.\n");
1859 break;
1860 case 7:
1861 arb->spmimst_clk_mux_parent =
1862 devm_clk_get(&pdev->dev, "spmimst_clk_mainpll_d7_d8");
1863 dev_info(&pdev->dev, "[SPMIMST]:enable mainpll d7 d8.\n");
1864 break;
1865 }
1866 if (IS_ERR(arb->spmimst_clk_mux_parent)) {
1867 dev_notice(&pdev->dev,
1868 "[SPMIMST]:failed to get clock: %ld\n",
1869 PTR_ERR(arb->spmimst_clk_mux_parent));
1870 return PTR_ERR(arb->spmimst_clk_mux_parent);
1871 }
1872 err = clk_prepare_enable(arb->spmimst_clk_mux);
1873 if (err)
1874 return err;
1875 err = clk_set_parent(arb->spmimst_clk_mux, arb->spmimst_clk_mux_parent);
1876 if (err)
1877 return err;
1878#else
1879 dev_notice(&pdev->dev, "[PMIF]:no need to get clock at fpga\n");
1880#endif /* #if defined(CONFIG_MTK_FPGA) || defined(CONFIG_FPGA_EARLY_PORTING) */
1881
1882 err = of_property_read_u32(pdev->dev.of_node,
1883 "swinf_ch_start", &swinf_ch_start);
1884 if (err) {
1885 dev_notice(&pdev->dev, "[PMIF]:swinf_ch_start unspecified.\n");
1886 goto err_put_ctrl;
1887 }
1888 arb->swinf_ch_start = swinf_ch_start;
1889
1890 err = of_property_read_u32(pdev->dev.of_node,
1891 "ap_swinf_no", &ap_swinf_no);
1892 if (err) {
1893 dev_notice(&pdev->dev, "[PMIF]:ap_swinf_no unspecified.\n");
1894 goto err_put_ctrl;
1895 }
1896 arb->ap_swinf_no = ap_swinf_no;
1897
1898 if (arb->is_pmif_init_done(arb) == 0) {
1899 /* pmif initialize start */
1900 arb->pmif_enable_clk_set(arb);
1901 arb->pmif_force_normal_mode(arb);
1902 /* Enable SWINF and arbitration for AP. */
1903 arb->pmif_enable_swinf(arb,
1904 arb->swinf_ch_start, arb->ap_swinf_no);
1905 arb->pmif_enable_cmdIssue(arb, true);
1906
1907 arb->pmif_enable(arb);
1908 /* pmif initialize end */
1909 }
1910
1911 raw_spin_lock_init(&arb->lock);
1912 arb->pmifThread_lock =
1913 wakeup_source_register(NULL, "pmif wakelock");
1914 mutex_init(&arb->pmif_mutex);
1915
1916 ctrl->cmd = pmif_arb_cmd;
1917 ctrl->read_cmd = pmif_spmi_read_cmd;
1918 ctrl->write_cmd = pmif_spmi_write_cmd;
1919
1920 if (arb->is_pmif_init_done(arb)) {
1921 /* pmif already done, call spmi master driver init */
1922 err = mtk_spmimst_init(pdev, arb);
1923 if (err)
1924 goto err_put_ctrl;
1925 }
1926 if (arb->pmifid != PMIF_PMIFID_SPMI2) {
1927 /* enable debugger for SPMI-M */
1928 spmi_pmif_dbg_init(ctrl);
1929 spmi_pmif_create_attr(&pmif_driver.driver);
1930 }
1931 arb->irq = platform_get_irq_byname(pdev, "pmif_irq");
1932 if (arb->irq < 0) {
1933 err = arb->irq;
1934 goto err_put_ctrl;
1935 }
1936 pmif_irq_register(pdev, arb, arb->irq);
1937
1938 arb->rcs_irq = platform_get_irq_byname(pdev, "rcs_irq");
1939 if (arb->rcs_irq < 0) {
1940 dev_notice(&pdev->dev,
1941 "Failed to get rcs_irq, ret = %d\n", arb->rcs_irq);
1942 } else {
1943 err = rcs_irq_register(pdev, arb, arb->rcs_irq);
1944 if (err)
1945 goto err_domain_remove;
1946 }
1947
1948 platform_set_drvdata(pdev, ctrl);
1949
1950 err = spmi_controller_add(ctrl);
1951 if (err)
1952 goto err_domain_remove;
1953
1954 return 0;
1955
1956err_domain_remove:
1957 if (arb->domain)
1958 irq_domain_remove(arb->domain);
1959#if !defined(CONFIG_FPGA_EARLY_PORTING)
1960 clk_disable_unprepare(arb->spmimst_clk_mux);
1961 clk_disable_unprepare(arb->pmif_tmr_ck);
1962 clk_disable_unprepare(arb->pmif_sys_ck);
1963 if ((pmif_clk26m & 0x1) == 0x1)
1964 clk_disable_unprepare(arb->pmif_clk26m);
1965 else
1966 clk_disable_unprepare(arb->pmif_clk_mux);
1967#endif
1968err_put_ctrl:
1969 spmi_controller_put(ctrl);
1970 return err;
1971}
1972
1973static int pmif_remove(struct platform_device *pdev)
1974{
1975 struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1976 struct pmif *arb = spmi_controller_get_drvdata(ctrl);
1977
1978 if (arb->domain)
1979 irq_domain_remove(arb->domain);
1980 spmi_controller_remove(ctrl);
1981 spmi_controller_put(ctrl);
1982 return 0;
1983}
1984
1985static struct platform_driver pmif_driver = {
1986 .probe = pmif_probe,
1987 .remove = pmif_remove,
1988 .driver = {
1989 .name = "pmif",
1990 .of_match_table = of_match_ptr(pmif_match_table),
1991 },
1992};
1993
1994static int __init mtk_pmif_init(void)
1995{
1996 int ret = 0;
1997
1998 ret = platform_driver_register(&pmif_driver);
1999 if (ret)
2000 return -ENODEV;
2001 return 0;
2002}
2003postcore_initcall(mtk_pmif_init);
2004
2005/* Module information */
2006MODULE_LICENSE("GPL v2");
2007MODULE_DESCRIPTION("PMIF module");
2008MODULE_AUTHOR("Argus Lin <argus.lin@mediatek.com>");
2009MODULE_ALIAS("platform:pmif");