| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__ |
| 3 | #define __DT_BINDINGS_POWER_RK3368_POWER_H__ |
| 4 | |
| 5 | /* VD_CORE */ |
| 6 | #define RK3368_PD_A53_L0 0 |
| 7 | #define RK3368_PD_A53_L1 1 |
| 8 | #define RK3368_PD_A53_L2 2 |
| 9 | #define RK3368_PD_A53_L3 3 |
| 10 | #define RK3368_PD_SCU_L 4 |
| 11 | #define RK3368_PD_A53_B0 5 |
| 12 | #define RK3368_PD_A53_B1 6 |
| 13 | #define RK3368_PD_A53_B2 7 |
| 14 | #define RK3368_PD_A53_B3 8 |
| 15 | #define RK3368_PD_SCU_B 9 |
| 16 | |
| 17 | /* VD_LOGIC */ |
| 18 | #define RK3368_PD_BUS 10 |
| 19 | #define RK3368_PD_PERI 11 |
| 20 | #define RK3368_PD_VIO 12 |
| 21 | #define RK3368_PD_ALIVE 13 |
| 22 | #define RK3368_PD_VIDEO 14 |
| 23 | #define RK3368_PD_GPU_0 15 |
| 24 | #define RK3368_PD_GPU_1 16 |
| 25 | |
| 26 | /* VD_PMU */ |
| 27 | #define RK3368_PD_PMU 17 |
| 28 | |
| 29 | #endif |