blob: 4b63bcf535898db648630bae51644753657bbdcd [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/version.h>
9#include <linux/err.h>
10#include <linux/i2c.h>
11#include <linux/delay.h>
12#include <sound/soc.h>
13#include <sound/tlv.h>
14#include <sound/pcm_params.h>
15#include <linux/debugfs.h>
16
17#include "mt6660.h"
18
19union mt6660_multi_byte_data {
20 u32 data_u32;
21 u16 data_u16;
22 u8 data_u8;
23 u8 data[4];
24};
25
26struct codec_reg_val {
27 u32 addr;
28 u32 mask;
29 u32 data;
30};
31
32struct reg_size_table {
33 u32 addr;
34 u8 size;
35};
36
37static const struct reg_size_table mt6660_reg_size_table[] = {
38 { MT6660_REG_HPF1_COEF, 4 },
39 { MT6660_REG_HPF2_COEF, 4 },
40 { MT6660_REG_TDM_CFG3, 2 },
41 { MT6660_REG_RESV17, 2 },
42 { MT6660_REG_RESV23, 2 },
43 { MT6660_REG_SIGMAX, 2 },
44 { MT6660_REG_DEVID, 2},
45 { MT6660_REG_TDM_CFG3, 2},
46 { MT6660_REG_HCLIP_CTRL, 2},
47 { MT6660_REG_DA_GAIN, 2},
48};
49
50static int mt6660_get_reg_size(uint32_t addr)
51{
52 int i = 0;
53
54 for (i = 0; i < ARRAY_SIZE(mt6660_reg_size_table); i++) {
55 if (mt6660_reg_size_table[i].addr == addr)
56 return mt6660_reg_size_table[i].size;
57 }
58 return 1;
59}
60
61static int32_t mt6660_i2c_update_bits(struct mt6660_chip *chip,
62 uint32_t addr, uint32_t mask, uint32_t data)
63{
64 int ret = 0;
65 uint32_t value;
66 int size = mt6660_get_reg_size(addr);
67 union mt6660_multi_byte_data mdata;
68
69 memcpy(&mdata, &data, sizeof(uint32_t));
70
71 mutex_lock(&chip->io_lock);
72 ret = i2c_smbus_read_i2c_block_data(
73 chip->i2c, addr, size, (u8 *)&value);
74 if (ret < 0) {
75 mutex_unlock(&chip->io_lock);
76 return ret;
77 }
78 switch (size) {
79 case 1:
80 value &= ~mask;
81 value |= (mdata.data_u8 & mask);
82 break;
83 case 2:
84 value = be16_to_cpu(value);
85 value &= ~mask;
86 value |= (mdata.data_u16 & mask);
87 value = be16_to_cpu(value);
88 break;
89 case 4:
90 value = be32_to_cpu(value);
91 value &= ~mask;
92 value |= (mdata.data_u32 & mask);
93 value = be32_to_cpu(value);
94 break;
95 default:
96 dev_err(chip->dev, "%s Invalid bytes\n", __func__);
97 break;
98 }
99
100 ret = i2c_smbus_write_i2c_block_data(
101 chip->i2c, addr, size, (u8 *)&value);
102 if (ret < 0) {
103 mutex_unlock(&chip->io_lock);
104 return ret;
105 }
106 mutex_unlock(&chip->io_lock);
107
108 return 0;
109}
110
111static int mt6660_dbg_io_read(void *drvdata, u16 reg, void *val, u16 size)
112{
113 struct mt6660_chip *chip = (struct mt6660_chip *)drvdata;
114
115 return i2c_smbus_read_i2c_block_data(chip->i2c, reg, size, val);
116}
117
118static int mt6660_dbg_io_write(void *drvdata, u16 reg,
119 const void *val, u16 size)
120{
121 struct mt6660_chip *chip = (struct mt6660_chip *)drvdata;
122
123 return i2c_smbus_write_i2c_block_data(chip->i2c, reg, size, val);
124}
125
126static int mt6660_i2c_read(struct mt6660_chip *chip, unsigned int reg)
127{
128 int size = mt6660_get_reg_size(reg);
129 int i = 0, ret = 0;
130 u8 data[4] = {0};
131 u32 reg_data = 0;
132
133 ret = i2c_smbus_read_i2c_block_data(chip->i2c, reg, size, data);
134 if (ret < 0)
135 return ret;
136 for (i = 0; i < size; i++) {
137 reg_data <<= 8;
138 reg_data |= data[i];
139 }
140 return reg_data;
141}
142
143static unsigned int mt6660_component_io_read(
144 struct snd_soc_component *component, unsigned int reg)
145{
146 struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
147
148 return mt6660_i2c_read(chip, reg);
149}
150
151static int mt6660_component_io_write(struct snd_soc_component *component,
152 unsigned int reg, unsigned int data)
153{
154 struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
155 int size = mt6660_get_reg_size(reg);
156 u8 reg_data[4] = {0};
157 int i = 0;
158
159 for (i = 0; i < size; i++)
160 reg_data[size - i - 1] = (data >> (8 * i)) & 0xff;
161
162 return i2c_smbus_write_i2c_block_data(chip->i2c, reg, size, reg_data);
163}
164
165static const int mt6660_dump_table[] = {
166 MT6660_REG_DEVID,
167 MT6660_REG_SYSTEM_CTRL,
168 MT6660_REG_IRQ_STATUS1,
169 MT6660_REG_SERIAL_CFG1,
170 MT6660_REG_DATAO_SEL,
171 MT6660_REG_TDM_CFG3,
172 MT6660_REG_HPF_CTRL,
173 MT6660_REG_HPF1_COEF,
174 MT6660_REG_HPF2_COEF,
175 MT6660_REG_PATH_BYPASS,
176 MT6660_REG_WDT_CTRL,
177 MT6660_REG_HCLIP_CTRL,
178 MT6660_REG_VOL_CTRL,
179 MT6660_REG_SPS_CTRL,
180 MT6660_REG_SIGMAX,
181 MT6660_REG_CALI_T0,
182 MT6660_REG_BST_CTRL,
183 MT6660_REG_PROTECTION_CFG,
184 MT6660_REG_DA_GAIN,
185 MT6660_REG_AUDIO_IN2_SEL,
186 MT6660_REG_SIG_GAIN,
187 MT6660_REG_PLL_CFG1,
188 MT6660_REG_DRE_CTRL,
189 MT6660_REG_DRE_THDMODE,
190 MT6660_REG_DRE_CORASE,
191 MT6660_REG_PWM_CTRL,
192 MT6660_REG_DC_PROTECT_CTRL,
193 MT6660_REG_ADC_USB_MODE,
194 MT6660_REG_INTERNAL_CFG,
195 MT6660_REG_RESV0,
196 MT6660_REG_RESV1,
197 MT6660_REG_RESV2,
198 MT6660_REG_RESV3,
199 MT6660_REG_RESV7,
200 MT6660_REG_RESV10,
201 MT6660_REG_RESV11,
202 MT6660_REG_RESV16,
203 MT6660_REG_RESV17,
204 MT6660_REG_RESV19,
205 MT6660_REG_RESV21,
206 MT6660_REG_RESV23,
207 MT6660_REG_RESV31,
208 MT6660_REG_RESV40,
209};
210
211#ifdef CONFIG_DEBUG_FS
212/* reg/size/data/bustype */
213#define PREALLOC_RBUFFER_SIZE (32)
214#define PREALLOC_WBUFFER_SIZE (1000)
215
216static int data_debug_show(struct seq_file *s, void *data)
217{
218 struct dbg_info *di = s->private;
219 struct dbg_internal *d = &di->internal;
220 void *buffer;
221 u8 *pdata;
222 int i, ret;
223
224 if (d->data_buffer_size < d->size) {
225 buffer = kzalloc(d->size, GFP_KERNEL);
226 if (!buffer)
227 return -ENOMEM;
228 kfree(d->data_buffer);
229 d->data_buffer = buffer;
230 d->data_buffer_size = d->size;
231 }
232 /* read transfer */
233 if (!di->io_read)
234 return -EPERM;
235 ret = di->io_read(di->io_drvdata, d->reg, d->data_buffer, d->size);
236 if (ret < 0)
237 return ret;
238 pdata = d->data_buffer;
239 seq_puts(s, "0x");
240 for (i = 0; i < d->size; i++)
241 seq_printf(s, "%02x,", *(pdata + i));
242 seq_puts(s, "\n");
243 return 0;
244}
245
246static int data_debug_open(struct inode *inode, struct file *file)
247{
248 if (file->f_mode & FMODE_READ)
249 return single_open(file, data_debug_show, inode->i_private);
250 return simple_open(inode, file);
251}
252
253static ssize_t data_debug_write(struct file *file,
254 const char __user *user_buf,
255 size_t cnt, loff_t *loff)
256{
257 struct dbg_info *di = file->private_data;
258 struct dbg_internal *d = &di->internal;
259 void *buffer;
260 u8 *pdata;
261 char buf[PREALLOC_WBUFFER_SIZE + 1], *token, *cur;
262 int val_cnt = 0, ret;
263
264 if (cnt > PREALLOC_WBUFFER_SIZE)
265 return -ENOMEM;
266 if (copy_from_user(buf, user_buf, cnt))
267 return -EFAULT;
268 buf[cnt] = 0;
269 /* buffer size check */
270 if (d->data_buffer_size < d->size) {
271 buffer = kzalloc(d->size, GFP_KERNEL);
272 if (!buffer)
273 return -ENOMEM;
274 kfree(d->data_buffer);
275 d->data_buffer = buffer;
276 d->data_buffer_size = d->size;
277 }
278 /* data parsing */
279 cur = buf;
280 pdata = d->data_buffer;
281 while ((token = strsep(&cur, ",\n")) != NULL) {
282 if (!*token)
283 break;
284 if (val_cnt++ >= d->size)
285 break;
286 if (kstrtou8(token, 16, pdata++))
287 return -EINVAL;
288 }
289 if (val_cnt != d->size)
290 return -EINVAL;
291 /* write transfer */
292 if (!di->io_write)
293 return -EPERM;
294 ret = di->io_write(di->io_drvdata, d->reg, d->data_buffer, d->size);
295 return (ret < 0) ? ret : cnt;
296}
297
298static int data_debug_release(struct inode *inode, struct file *file)
299{
300 if (file->f_mode & FMODE_READ)
301 return single_release(inode, file);
302 return 0;
303}
304
305static const struct file_operations data_debug_fops = {
306 .open = data_debug_open,
307 .read = seq_read,
308 .write = data_debug_write,
309 .llseek = seq_lseek,
310 .release = data_debug_release,
311};
312
313static int type_debug_show(struct seq_file *s, void *data)
314{
315 struct dbg_info *di = s->private;
316
317 seq_printf(s, "%s,%s\n", di->typestr, di->devname);
318 return 0;
319}
320
321static int type_debug_open(struct inode *inode, struct file *file)
322{
323 return single_open(file, type_debug_show, inode->i_private);
324}
325
326static const struct file_operations type_debug_fops = {
327 .open = type_debug_open,
328 .read = seq_read,
329 .llseek = seq_lseek,
330 .release = single_release,
331};
332
333static int dump_debug_show(struct seq_file *s, void *data)
334{
335 struct dbg_info *di = s->private;
336 struct mt6660_chip *chip =
337 container_of(di, struct mt6660_chip, dbg_info);
338 int i = 0, ret = 0;
339
340 if (!chip) {
341 pr_err("%s chip is null\n", __func__);
342 return -ENODEV;
343 }
344
345 for (i = 0; i < ARRAY_SIZE(mt6660_dump_table); i++) {
346 ret = mt6660_i2c_read(chip, mt6660_dump_table[i]);
347 seq_printf(s,
348 "reg 0x%02x : 0x%x\n", mt6660_dump_table[i], ret);
349 }
350 return 0;
351}
352
353static int dump_debug_open(struct inode *inode, struct file *file)
354{
355 return single_open(file, dump_debug_show, inode->i_private);
356}
357
358static const struct file_operations dump_debug_fops = {
359 .open = dump_debug_open,
360 .read = seq_read,
361 .llseek = seq_lseek,
362 .release = single_release,
363};
364
365static ssize_t lock_debug_read(struct file *file,
366 char __user *user_buf, size_t cnt, loff_t *loff)
367{
368 struct dbg_info *di = file->private_data;
369 struct dbg_internal *d = &di->internal;
370 char buf[10];
371
372 snprintf(buf, sizeof(buf), "%d\n", mutex_is_locked(&d->io_lock));
373 return simple_read_from_buffer(user_buf, cnt, loff, buf, strlen(buf));
374}
375
376static ssize_t lock_debug_write(struct file *file,
377 const char __user *user_buf,
378 size_t cnt, loff_t *loff)
379{
380 struct dbg_info *di = file->private_data;
381 struct dbg_internal *d = &di->internal;
382 u32 lock;
383 int ret;
384
385 ret = kstrtou32_from_user(user_buf, cnt, 0, &lock);
386 if (ret < 0)
387 return ret;
388 lock ? mutex_lock(&d->io_lock) : mutex_unlock(&d->io_lock);
389 return cnt;
390}
391
392static const struct file_operations lock_debug_fops = {
393 .open = simple_open,
394 .read = lock_debug_read,
395 .write = lock_debug_write,
396};
397
398static int generic_debugfs_init(struct dbg_info *di)
399{
400 struct dbg_internal *d = &di->internal;
401
402 /* valid check */
403 if (!di->dirname || !di->devname || !di->typestr)
404 return -EINVAL;
405 d->data_buffer_size = PREALLOC_RBUFFER_SIZE;
406 d->data_buffer = kzalloc(PREALLOC_RBUFFER_SIZE, GFP_KERNEL);
407 if (!d->data_buffer)
408 return -ENOMEM;
409 /* create debugfs */
410 d->rt_root = debugfs_lookup("ext_dev_io", NULL);
411 if (!d->rt_root) {
412 d->rt_root = debugfs_create_dir("ext_dev_io", NULL);
413 if (!d->rt_root)
414 return -ENODEV;
415 d->rt_dir_create = true;
416 }
417 d->ic_root = debugfs_create_dir(di->dirname, d->rt_root);
418 if (!d->ic_root)
419 goto err_cleanup_rt;
420 if (!debugfs_create_u16("reg", 0644, d->ic_root, &d->reg))
421 goto err_cleanup_ic;
422 if (!debugfs_create_u16("size", 0644, d->ic_root, &d->size))
423 goto err_cleanup_ic;
424 if (!debugfs_create_file("data", 0644,
425 d->ic_root, di, &data_debug_fops))
426 goto err_cleanup_ic;
427 if (!debugfs_create_file("type", 0444,
428 d->ic_root, di, &type_debug_fops))
429 goto err_cleanup_ic;
430 if (!debugfs_create_file("lock", 0644,
431 d->ic_root, di, &lock_debug_fops))
432 goto err_cleanup_ic;
433 if (!debugfs_create_file("dumps", 0444,
434 d->ic_root, di, &dump_debug_fops))
435 goto err_cleanup_ic;
436 mutex_init(&d->io_lock);
437 return 0;
438err_cleanup_ic:
439 debugfs_remove_recursive(d->ic_root);
440err_cleanup_rt:
441 if (d->rt_dir_create)
442 debugfs_remove_recursive(d->rt_root);
443 kfree(d->data_buffer);
444 return -ENODEV;
445}
446
447static void generic_debugfs_exit(struct dbg_info *di)
448{
449 struct dbg_internal *d = &di->internal;
450
451 mutex_destroy(&d->io_lock);
452 debugfs_remove_recursive(d->ic_root);
453 if (d->rt_dir_create)
454 debugfs_remove_recursive(d->rt_root);
455 kfree(d->data_buffer);
456}
457#else
458static inline int generic_debugfs_init(struct dbg_info *di)
459{
460 return 0;
461}
462
463static inline void generic_debugfs_exit(struct dbg_info *di) {}
464#endif /* CONFIG_DEBUG_FS */
465
466static const struct codec_reg_val e4_reg_inits[] = {
467 { MT6660_REG_WDT_CTRL, 0x80, 0x00 },
468 { MT6660_REG_SPS_CTRL, 0x01, 0x01 },
469 { MT6660_REG_AUDIO_IN2_SEL, 0x1c, 0x04 },
470 { MT6660_REG_RESV11, 0x0c, 0x00 },
471 { MT6660_REG_RESV31, 0x03, 0x03 },
472 { MT6660_REG_RESV40, 0x01, 0x00 },
473 { MT6660_REG_RESV0, 0x44, 0x04 },
474 { MT6660_REG_RESV19, 0xff, 0x82 },
475 { MT6660_REG_RESV17, 0x7777, 0x7273 },
476 { MT6660_REG_RESV16, 0x07, 0x03 },
477 { MT6660_REG_DRE_CORASE, 0xe0, 0x20 },
478 { MT6660_REG_ADDA_CLOCK, 0xff, 0x70 },
479 { MT6660_REG_RESV21, 0xff, 0x20 },
480 { MT6660_REG_DRE_THDMODE, 0xff, 0x40 },
481 { MT6660_REG_RESV23, 0xffff, 0x17f8 },
482 { MT6660_REG_PWM_CTRL, 0xff, 0x15 },
483 { MT6660_REG_ADC_USB_MODE, 0xff, 0x00 },
484 { MT6660_REG_PROTECTION_CFG, 0xff, 0x1d },
485 { MT6660_REG_HPF1_COEF, 0xffffffff, 0x7fdb7ffe },
486 { MT6660_REG_HPF2_COEF, 0xffffffff, 0x7fdb7ffe },
487 { MT6660_REG_SIG_GAIN, 0xff, 0x58 },
488 { MT6660_REG_RESV6, 0xff, 0xce },
489 { MT6660_REG_SIGMAX, 0xffff, 0x7fff },
490 { MT6660_REG_DA_GAIN, 0xffff, 0x0116 },
491 { MT6660_REG_TDM_CFG3, 0x1800, 0x0800 },
492 { MT6660_REG_DRE_CTRL, 0x1f, 0x07 },
493};
494
495static int mt6660_i2c_init_setting(struct mt6660_chip *chip)
496{
497 int i, len, ret;
498 const struct codec_reg_val *init_table;
499
500 init_table = e4_reg_inits;
501 len = ARRAY_SIZE(e4_reg_inits);
502
503 for (i = 0; i < len; i++) {
504 ret = mt6660_i2c_update_bits(chip, init_table[i].addr,
505 init_table[i].mask, init_table[i].data);
506 if (ret < 0)
507 return ret;
508 }
509 return 0;
510}
511
512static int mt6660_chip_power_on(
513 struct snd_soc_component *component, int on_off)
514{
515 struct mt6660_chip *chip = (struct mt6660_chip *)
516 snd_soc_component_get_drvdata(component);
517 int ret = 0;
518 unsigned int val;
519
520 dev_dbg(component->dev, "%s: on_off = %d\n", __func__, on_off);
521 mutex_lock(&chip->var_lock);
522 if (on_off) {
523 if (chip->pwr_cnt == 0) {
524 ret = mt6660_i2c_update_bits(chip,
525 MT6660_REG_SYSTEM_CTRL, 0x01, 0x00);
526 val = mt6660_i2c_read(chip, MT6660_REG_IRQ_STATUS1);
527 dev_info(chip->dev,
528 "%s reg0x05 = 0x%x\n", __func__, val);
529 }
530 chip->pwr_cnt++;
531 } else {
532 chip->pwr_cnt--;
533 if (chip->pwr_cnt == 0) {
534 ret = mt6660_i2c_update_bits(chip,
535 MT6660_REG_SYSTEM_CTRL, 0x01, 0xff);
536 }
537 if (chip->pwr_cnt < 0) {
538 dev_warn(chip->dev, "not paired on/off\n");
539 chip->pwr_cnt = 0;
540 }
541 }
542 mutex_unlock(&chip->var_lock);
543 if (ret < 0)
544 pr_err("%s ret = %d\n", __func__, ret);
545 return ret;
546}
547
548static int mt6660_component_set_bias_level(struct snd_soc_component *component,
549 enum snd_soc_bias_level level)
550{
551 struct snd_soc_dapm_context *dapm =
552 snd_soc_component_get_dapm(component);
553 int ret;
554 unsigned int val;
555 struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
556
557 if (dapm->bias_level == level) {
558 dev_warn(component->dev, "%s: repeat level change\n", __func__);
559 return 0;
560 }
561 switch (level) {
562 case SND_SOC_BIAS_ON:
563 case SND_SOC_BIAS_PREPARE:
564 break;
565 case SND_SOC_BIAS_STANDBY:
566 if (dapm->bias_level != SND_SOC_BIAS_OFF)
567 break;
568 dev_dbg(component->dev, "exit low power mode\n");
569 ret = mt6660_chip_power_on(component, 1);
570 if (ret < 0) {
571 dev_err(component->dev, "power on fail\n");
572 return ret;
573 }
574 break;
575 case SND_SOC_BIAS_OFF:
576 dev_dbg(component->dev, "enter low power mode\n");
577 val = mt6660_i2c_read(chip, MT6660_REG_IRQ_STATUS1);
578 dev_info(component->dev,
579 "%s reg0x05 = 0x%x\n", __func__, val);
580 ret = mt6660_chip_power_on(component, 0);
581 if (ret < 0) {
582 dev_err(component->dev, "power off fail\n");
583 return ret;
584 }
585 break;
586 default:
587 return -EINVAL;
588 }
589 dapm->bias_level = level;
590 dev_dbg(component->dev, "c bias_level = %d\n", level);
591 return 0;
592}
593
594static int mt6660_component_probe(struct snd_soc_component *component)
595{
596 struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
597 int ret = 0;
598
599 ret = mt6660_component_set_bias_level(component, SND_SOC_BIAS_STANDBY);
600 if (ret < 0) {
601 dev_err(component->dev, "config bias standby fail\n");
602 return ret;
603 }
604
605 ret = mt6660_component_set_bias_level(component, SND_SOC_BIAS_OFF);
606 if (ret < 0) {
607 dev_err(component->dev, "config bias off fail\n");
608 return ret;
609 }
610 chip->component = component;
611 return 0;
612}
613
614static void mt6660_component_remove(struct snd_soc_component *component)
615{
616 struct mt6660_chip *chip = snd_soc_component_get_drvdata(component);
617
618 dev_dbg(component->dev, "%s++\n", __func__);
619 chip->component = NULL;
620 dev_dbg(component->dev, "%s--\n", __func__);
621}
622
623static int mt6660_codec_dac_event(struct snd_soc_dapm_widget *w,
624 struct snd_kcontrol *kcontrol, int event)
625{
626 switch (event) {
627 case SND_SOC_DAPM_POST_PMU:
628 usleep_range(1000, 1100);
629 break;
630 }
631 return 0;
632}
633
634static int mt6660_codec_classd_event(struct snd_soc_dapm_widget *w,
635 struct snd_kcontrol *kcontrol, int event)
636{
637 struct snd_soc_component *component =
638 snd_soc_dapm_to_component(w->dapm);
639 int ret = 0;
640
641 switch (event) {
642 case SND_SOC_DAPM_PRE_PMU:
643 dev_dbg(component->dev,
644 "%s: before classd turn on\n", __func__);
645 /* config to adaptive mode */
646 ret = snd_soc_component_update_bits(component,
647 MT6660_REG_BST_CTRL, 0x03, 0x03);
648 if (ret < 0) {
649 dev_err(component->dev, "config mode adaptive fail\n");
650 return ret;
651 }
652 break;
653 case SND_SOC_DAPM_POST_PMU:
654 /* voltage sensing enable */
655 ret = snd_soc_component_update_bits(component,
656 MT6660_REG_RESV7, 0x04, 0x04);
657 if (ret < 0) {
658 dev_err(component->dev,
659 "enable voltage sensing fail\n");
660 return ret;
661 }
662 break;
663 case SND_SOC_DAPM_PRE_PMD:
664 /* voltage sensing disable */
665 ret = snd_soc_component_update_bits(component,
666 MT6660_REG_RESV7, 0x04, 0x00);
667 if (ret < 0) {
668 dev_err(component->dev,
669 "disable voltage sensing fail\n");
670 return ret;
671 }
672 /* pop-noise improvement 1 */
673 ret = snd_soc_component_update_bits(component,
674 MT6660_REG_RESV10, 0x10, 0x10);
675 if (ret < 0) {
676 dev_err(component->dev,
677 "pop-noise improvement 1 fail\n");
678 return ret;
679 }
680 break;
681 case SND_SOC_DAPM_POST_PMD:
682 dev_dbg(component->dev,
683 "%s: after classd turn off\n", __func__);
684 /* pop-noise improvement 2 */
685 ret = snd_soc_component_update_bits(component,
686 MT6660_REG_RESV10, 0x10, 0x00);
687 if (ret < 0) {
688 dev_err(component->dev,
689 "pop-noise improvement 2 fail\n");
690 return ret;
691 }
692 /* config to off mode */
693 ret = snd_soc_component_update_bits(component,
694 MT6660_REG_BST_CTRL, 0x03, 0x00);
695 if (ret < 0) {
696 dev_err(component->dev, "config mode off fail\n");
697 return ret;
698 }
699 break;
700 }
701 return 0;
702}
703
704static const struct snd_soc_dapm_widget mt6660_component_dapm_widgets[] = {
705 SND_SOC_DAPM_DAC_E("DAC", NULL, MT6660_REG_PLL_CFG1,
706 0, 1, mt6660_codec_dac_event, SND_SOC_DAPM_POST_PMU),
707 SND_SOC_DAPM_ADC("VI ADC", NULL, SND_SOC_NOPM, 0, 0),
708 SND_SOC_DAPM_PGA("PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
709 SND_SOC_DAPM_OUT_DRV_E("ClassD", MT6660_REG_SYSTEM_CTRL, 2, 0,
710 NULL, 0, mt6660_codec_classd_event,
711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
712 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
713 SND_SOC_DAPM_SPK("SPK", NULL),
714};
715
716static const struct snd_soc_dapm_route mt6660_component_dapm_routes[] = {
717 { "DAC", NULL, "aif_playback"},
718 { "PGA", NULL, "DAC"},
719 { "ClassD", NULL, "PGA"},
720 { "SPK", NULL, "ClassD"},
721 { "VI ADC", NULL, "ClassD"},
722 { "aif_capture", NULL, "VI ADC"},
723};
724
725static int mt6660_component_put_volsw(struct snd_kcontrol *kcontrol,
726 struct snd_ctl_elem_value *ucontrol)
727{
728 struct snd_soc_component *component =
729 snd_soc_kcontrol_component(kcontrol);
730 int ret, put_ret = 0;
731
732 ret = mt6660_chip_power_on(component, 1);
733 if (ret < 0)
734 dev_err(component->dev, "%s: pwr on fail\n", __func__);
735 put_ret = snd_soc_put_volsw(kcontrol, ucontrol);
736 if (ret < 0)
737 return ret;
738 ret = mt6660_chip_power_on(component, 0);
739 if (ret < 0)
740 dev_err(component->dev, "%s: pwr off fail\n", __func__);
741 return put_ret;
742}
743
744static int mt6660_component_get_volsw(struct snd_kcontrol *kcontrol,
745 struct snd_ctl_elem_value *ucontrol)
746{
747 struct snd_soc_component *component =
748 snd_soc_kcontrol_component(kcontrol);
749 struct mt6660_chip *chip = (struct mt6660_chip *)
750 snd_soc_component_get_drvdata(component);
751 int ret = -EINVAL;
752
753 if (!strcmp(kcontrol->id.name, "Chip_Rev")) {
754 ucontrol->value.integer.value[0] = chip->chip_rev & 0x0f;
755 ret = 0;
756 }
757 return ret;
758}
759
760static const DECLARE_TLV_DB_SCALE(vol_ctl_tlv, -1155, 5, 0);
761
762static const struct snd_kcontrol_new mt6660_component_snd_controls[] = {
763 SOC_SINGLE_EXT_TLV("Volume_Ctrl", MT6660_REG_VOL_CTRL, 0, 255,
764 1, snd_soc_get_volsw, mt6660_component_put_volsw,
765 vol_ctl_tlv),
766 SOC_SINGLE_EXT("WDT_Enable", MT6660_REG_WDT_CTRL, 7, 1, 0,
767 snd_soc_get_volsw, mt6660_component_put_volsw),
768 SOC_SINGLE_EXT("Hard_Clip_Enable", MT6660_REG_HCLIP_CTRL, 8, 1, 0,
769 snd_soc_get_volsw, mt6660_component_put_volsw),
770 SOC_SINGLE_EXT("Clip_Enable", MT6660_REG_SPS_CTRL, 0, 1, 0,
771 snd_soc_get_volsw, mt6660_component_put_volsw),
772 SOC_SINGLE_EXT("BoostMode", MT6660_REG_BST_CTRL, 0, 3, 0,
773 snd_soc_get_volsw, mt6660_component_put_volsw),
774 SOC_SINGLE_EXT("DRE_Enable", MT6660_REG_DRE_CTRL, 0, 1, 0,
775 snd_soc_get_volsw, mt6660_component_put_volsw),
776 SOC_SINGLE_EXT("DC_Protect_Enable",
777 MT6660_REG_DC_PROTECT_CTRL, 3, 1, 0,
778 snd_soc_get_volsw, mt6660_component_put_volsw),
779 SOC_SINGLE_EXT("I2SLRS", MT6660_REG_DATAO_SEL, 6, 3, 0,
780 snd_soc_get_volsw, mt6660_component_put_volsw),
781 SOC_SINGLE_EXT("I2SDOLS", MT6660_REG_DATAO_SEL, 3, 7, 0,
782 snd_soc_get_volsw, mt6660_component_put_volsw),
783 SOC_SINGLE_EXT("I2SDORS", MT6660_REG_DATAO_SEL, 0, 7, 0,
784 snd_soc_get_volsw, mt6660_component_put_volsw),
785 /* for debug purpose */
786 SOC_SINGLE_EXT("HPF_AUD_IN_EN", MT6660_REG_HPF_CTRL, 0, 1, 0,
787 snd_soc_get_volsw, mt6660_component_put_volsw),
788 SOC_SINGLE_EXT("AUD_LOOP_BACK", MT6660_REG_PATH_BYPASS, 4, 1, 0,
789 snd_soc_get_volsw, mt6660_component_put_volsw),
790 SOC_SINGLE_EXT("Mute_Enable", MT6660_REG_SYSTEM_CTRL, 1, 1, 0,
791 snd_soc_get_volsw, mt6660_component_put_volsw),
792 SOC_SINGLE_EXT("CS_Comp_Disable", MT6660_REG_PATH_BYPASS, 2, 1, 0,
793 snd_soc_get_volsw, mt6660_component_put_volsw),
794 SOC_SINGLE_EXT("T0_SEL", MT6660_REG_CALI_T0, 0, 7, 0,
795 snd_soc_get_volsw, NULL),
796 SOC_SINGLE_EXT("Chip_Rev", SND_SOC_NOPM, 0, 16, 0,
797 mt6660_component_get_volsw, NULL),
798};
799
800
801static const struct snd_soc_component_driver mt6660_component_driver = {
802 .probe = mt6660_component_probe,
803 .remove = mt6660_component_remove,
804
805 .read = mt6660_component_io_read,
806 .write = mt6660_component_io_write,
807
808 .controls = mt6660_component_snd_controls,
809 .num_controls = ARRAY_SIZE(mt6660_component_snd_controls),
810 .dapm_widgets = mt6660_component_dapm_widgets,
811 .num_dapm_widgets = ARRAY_SIZE(mt6660_component_dapm_widgets),
812 .dapm_routes = mt6660_component_dapm_routes,
813 .num_dapm_routes = ARRAY_SIZE(mt6660_component_dapm_routes),
814
815 .set_bias_level = mt6660_component_set_bias_level,
816 .idle_bias_on = false, /* idle_bias_off = true */
817};
818
819static int mt6660_component_aif_startup(struct snd_pcm_substream *substream,
820 struct snd_soc_dai *dai)
821{
822 struct snd_soc_dapm_context *dapm =
823 snd_soc_component_get_dapm(dai->component);
824 int ret = 0;
825
826 dev_dbg(dai->dev, "%s\n", __func__);
827 if (dapm->bias_level == SND_SOC_BIAS_OFF)
828 ret = mt6660_component_set_bias_level(dai->component,
829 SND_SOC_BIAS_STANDBY);
830 return ret;
831}
832
833static int mt6660_component_aif_hw_params(struct snd_pcm_substream *substream,
834 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *dai)
835{
836 int word_len = params_physical_width(hw_params);
837 int aud_bit = params_width(hw_params);
838 u16 reg_data = 0;
839 int ret = 0;
840
841 dev_dbg(dai->dev, "%s: ++\n", __func__);
842 dev_dbg(dai->dev, "format: 0x%08x\n", params_format(hw_params));
843 dev_dbg(dai->dev, "rate: 0x%08x\n", params_rate(hw_params));
844 dev_dbg(dai->dev, "word_len: %d, aud_bit: %d\n", word_len, aud_bit);
845 if (word_len > 32 || word_len < 16) {
846 dev_err(dai->dev, "not supported word length\n");
847 return -ENOTSUPP;
848 }
849 switch (aud_bit) {
850 case 16:
851 reg_data = 3;
852 break;
853 case 18:
854 reg_data = 2;
855 break;
856 case 20:
857 reg_data = 1;
858 break;
859 case 24:
860 case 32:
861 reg_data = 0;
862 break;
863 default:
864 return -ENOTSUPP;
865 }
866 ret = snd_soc_component_update_bits(dai->component,
867 MT6660_REG_SERIAL_CFG1, 0xc0, (reg_data << 6));
868 if (ret < 0) {
869 dev_err(dai->dev, "config aud bit fail\n");
870 return ret;
871 }
872 ret = snd_soc_component_update_bits(dai->component,
873 MT6660_REG_TDM_CFG3, 0x3f0, word_len << 4);
874 if (ret < 0) {
875 dev_err(dai->dev, "config word len fail\n");
876 return ret;
877 }
878 dev_dbg(dai->dev, "%s: --\n", __func__);
879 return 0;
880}
881
882static const struct snd_soc_dai_ops mt6660_component_aif_ops = {
883 .startup = mt6660_component_aif_startup,
884 .hw_params = mt6660_component_aif_hw_params,
885};
886
887#define STUB_RATES SNDRV_PCM_RATE_8000_192000
888#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
889 SNDRV_PCM_FMTBIT_U16_LE | \
890 SNDRV_PCM_FMTBIT_S24_LE | \
891 SNDRV_PCM_FMTBIT_U24_LE | \
892 SNDRV_PCM_FMTBIT_S32_LE | \
893 SNDRV_PCM_FMTBIT_U32_LE)
894
895static struct snd_soc_dai_driver mt6660_codec_dai = {
896 .name = "mt6660-aif",
897 .playback = {
898 .stream_name = "aif_playback",
899 .channels_min = 1,
900 .channels_max = 2,
901 .rates = STUB_RATES,
902 .formats = STUB_FORMATS,
903 },
904 .capture = {
905 .stream_name = "aif_capture",
906 .channels_min = 1,
907 .channels_max = 2,
908 .rates = STUB_RATES,
909 .formats = STUB_FORMATS,
910 },
911 /* dai properties */
912 .symmetric_rates = 1,
913 .symmetric_channels = 1,
914 .symmetric_samplebits = 1,
915 /* dai operations */
916 .ops = &mt6660_component_aif_ops,
917};
918
919static inline int mt6660_chip_id_check(struct i2c_client *i2c)
920{
921 u8 id[2] = {0};
922 int ret = 0;
923
924 i2c_smbus_write_byte_data(i2c, 0x03, 0x00);
925 ret = i2c_smbus_read_i2c_block_data(i2c, MT6660_REG_DEVID, 2, id);
926 if (ret < 0)
927 return ret;
928 ret = (id[0] << 8) + id[1];
929 ret &= 0x0ff0;
930 if (ret != 0x00e0 && ret != 0x01e0)
931 return -ENODEV;
932 i2c_smbus_write_byte_data(i2c, 0x03, 0x01);
933 return 0;
934}
935
936static inline int _mt6660_chip_sw_reset(struct mt6660_chip *chip)
937{
938 i2c_smbus_write_byte_data(chip->i2c, MT6660_REG_SYSTEM_CTRL, 0x80);
939 msleep(30);
940 return 0;
941}
942
943static inline int _mt6660_chip_power_on(struct mt6660_chip *chip, int on_off)
944{
945 u8 reg_data = 0;
946 int ret = 0;
947
948 ret = i2c_smbus_read_byte_data(chip->i2c, MT6660_REG_SYSTEM_CTRL);
949 if (ret < 0)
950 return ret;
951 reg_data = (u8)ret;
952 if (on_off)
953 reg_data &= (~0x01);
954 else
955 reg_data |= 0x01;
956 return i2c_smbus_write_byte_data(
957 chip->i2c, MT6660_REG_SYSTEM_CTRL, reg_data);
958}
959
960static inline int _mt6660_read_chip_revision(struct mt6660_chip *chip)
961{
962 u8 reg_data[2] = {0};
963 int ret = 0;
964
965 ret = i2c_smbus_read_i2c_block_data(
966 chip->i2c, MT6660_REG_DEVID, 2, reg_data);
967 if (ret < 0) {
968 dev_err(chip->dev, "get chip revision fail\n");
969 return ret;
970 }
971 chip->chip_rev = reg_data[1];
972 return 0;
973}
974
975int mt6660_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
976{
977 struct mt6660_chip *chip = NULL;
978 int ret = 0;
979
980 ret = mt6660_chip_id_check(client);
981 if (ret < 0) {
982 dev_err(&client->dev, "chip id check fail\n");
983 return ret;
984 }
985 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
986 if (!chip)
987 return -ENOMEM;
988 chip->i2c = client;
989 chip->dev = &client->dev;
990 mutex_init(&chip->var_lock);
991 mutex_init(&chip->io_lock);
992 i2c_set_clientdata(client, chip);
993
994 /* debugfs interface */
995 chip->dbg_info.dirname = devm_kasprintf(&client->dev,
996 GFP_KERNEL, "MT6660.%s",
997 dev_name(&client->dev));
998 chip->dbg_info.devname = dev_name(&client->dev);
999 chip->dbg_info.typestr = devm_kasprintf(&client->dev,
1000 GFP_KERNEL, "I2C,MT6660");
1001 chip->dbg_info.io_drvdata = chip;
1002 chip->dbg_info.io_read = mt6660_dbg_io_read;
1003 chip->dbg_info.io_write = mt6660_dbg_io_write;
1004
1005 ret = generic_debugfs_init(&chip->dbg_info);
1006 if (ret < 0) {
1007 dev_err(&client->dev, "generic dbg init fail\n");
1008 return -EINVAL;
1009 }
1010
1011 /* chip power on */
1012 ret = _mt6660_chip_power_on(chip, 1);
1013 if (ret < 0) {
1014 dev_err(chip->dev, "chip power on 1 fail\n");
1015 goto probe_fail;
1016 }
1017 /* chip reset first */
1018 ret = _mt6660_chip_sw_reset(chip);
1019 if (ret < 0) {
1020 dev_err(chip->dev, "chip reset fail\n");
1021 goto probe_fail;
1022 }
1023 /* chip power on */
1024 ret = _mt6660_chip_power_on(chip, 1);
1025 if (ret < 0) {
1026 dev_err(chip->dev, "chip power on 2 fail\n");
1027 goto probe_fail;
1028 }
1029 ret = _mt6660_read_chip_revision(chip);
1030 if (ret < 0) {
1031 dev_err(chip->dev, "read chip revision fail\n");
1032 goto probe_fail;
1033 }
1034 ret = mt6660_i2c_init_setting(chip);
1035 if (ret < 0) {
1036 dev_err(chip->dev, "chip i2c init setting fail\n");
1037 goto probe_fail;
1038 }
1039 ret = _mt6660_chip_power_on(chip, 0);
1040 if (ret < 0) {
1041 dev_err(chip->dev, "chip power off fail\n");
1042 goto probe_fail;
1043 }
1044 return snd_soc_register_component(chip->dev,
1045 &mt6660_component_driver, &mt6660_codec_dai, 1);
1046probe_fail:
1047 mutex_destroy(&chip->var_lock);
1048 return ret;
1049}
1050
1051int mt6660_i2c_remove(struct i2c_client *client)
1052{
1053 struct mt6660_chip *chip = i2c_get_clientdata(client);
1054
1055 dev_dbg(chip->dev, "%s++\n", __func__);
1056 snd_soc_unregister_component(chip->dev);
1057 generic_debugfs_exit(&chip->dbg_info);
1058 mutex_destroy(&chip->var_lock);
1059 dev_dbg(chip->dev, "%s--\n", __func__);
1060 return 0;
1061}
1062
1063static const struct of_device_id __maybe_unused mt6660_of_id[] = {
1064 { .compatible = "mediatek,mt6660",},
1065 {},
1066};
1067MODULE_DEVICE_TABLE(of, mt6660_of_id);
1068
1069static const struct i2c_device_id mt6660_i2c_id[] = {
1070 {"mt6660", 0 },
1071 {},
1072};
1073MODULE_DEVICE_TABLE(i2c, mt6660_i2c_id);
1074
1075static struct i2c_driver mt6660_i2c_driver = {
1076 .driver = {
1077 .name = "mt6660",
1078 .owner = THIS_MODULE,
1079 .of_match_table = of_match_ptr(mt6660_of_id),
1080 },
1081 .probe = mt6660_i2c_probe,
1082 .remove = mt6660_i2c_remove,
1083 .id_table = mt6660_i2c_id,
1084};
1085module_i2c_driver(mt6660_i2c_driver);
1086
1087MODULE_AUTHOR("Jeff Chang <jeff_chang@richtek.com>");
1088MODULE_DESCRIPTION("MT6660 SPKAMP Driver");
1089MODULE_LICENSE("GPL");
1090MODULE_VERSION("1.0.6_G");