| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__ |
| 3 | #define __DT_BINDINGS_POWER_RK3399_POWER_H__ |
| 4 | |
| 5 | /* VD_CORE_L */ |
| 6 | #define RK3399_PD_A53_L0 0 |
| 7 | #define RK3399_PD_A53_L1 1 |
| 8 | #define RK3399_PD_A53_L2 2 |
| 9 | #define RK3399_PD_A53_L3 3 |
| 10 | #define RK3399_PD_SCU_L 4 |
| 11 | |
| 12 | /* VD_CORE_B */ |
| 13 | #define RK3399_PD_A72_B0 5 |
| 14 | #define RK3399_PD_A72_B1 6 |
| 15 | #define RK3399_PD_SCU_B 7 |
| 16 | |
| 17 | /* VD_LOGIC */ |
| 18 | #define RK3399_PD_TCPD0 8 |
| 19 | #define RK3399_PD_TCPD1 9 |
| 20 | #define RK3399_PD_CCI 10 |
| 21 | #define RK3399_PD_CCI0 11 |
| 22 | #define RK3399_PD_CCI1 12 |
| 23 | #define RK3399_PD_PERILP 13 |
| 24 | #define RK3399_PD_PERIHP 14 |
| 25 | #define RK3399_PD_VIO 15 |
| 26 | #define RK3399_PD_VO 16 |
| 27 | #define RK3399_PD_VOPB 17 |
| 28 | #define RK3399_PD_VOPL 18 |
| 29 | #define RK3399_PD_ISP0 19 |
| 30 | #define RK3399_PD_ISP1 20 |
| 31 | #define RK3399_PD_HDCP 21 |
| 32 | #define RK3399_PD_GMAC 22 |
| 33 | #define RK3399_PD_EMMC 23 |
| 34 | #define RK3399_PD_USB3 24 |
| 35 | #define RK3399_PD_EDP 25 |
| 36 | #define RK3399_PD_GIC 26 |
| 37 | #define RK3399_PD_SD 27 |
| 38 | #define RK3399_PD_SDIOAUDIO 28 |
| 39 | #define RK3399_PD_ALIVE 29 |
| 40 | |
| 41 | /* VD_CENTER */ |
| 42 | #define RK3399_PD_CENTER 30 |
| 43 | #define RK3399_PD_VCODEC 31 |
| 44 | #define RK3399_PD_VDU 32 |
| 45 | #define RK3399_PD_RGA 33 |
| 46 | #define RK3399_PD_IEP 34 |
| 47 | |
| 48 | /* VD_GPU */ |
| 49 | #define RK3399_PD_GPU 35 |
| 50 | |
| 51 | /* VD_PMU */ |
| 52 | #define RK3399_PD_PMU 36 |
| 53 | |
| 54 | #endif |