| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2011 Linaro Ltd. |
| 4 | * |
| 5 | * The code contained herein is licensed under the GNU General Public |
| 6 | * License. You may obtain a copy of the GNU General Public License |
| 7 | * Version 2 or later at the following locations: |
| 8 | * |
| 9 | * http://www.opensource.org/licenses/gpl-license.html |
| 10 | * http://www.gnu.org/copyleft/gpl.html |
| 11 | */ |
| 12 | |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/irq.h> |
| 15 | #include <linux/of_address.h> |
| 16 | #include <linux/of_irq.h> |
| 17 | #include <linux/of_platform.h> |
| 18 | #include <asm/mach/arch.h> |
| 19 | #include <asm/mach/time.h> |
| 20 | |
| 21 | #include "common.h" |
| 22 | #include "hardware.h" |
| 23 | |
| 24 | static void __init imx51_init_early(void) |
| 25 | { |
| 26 | mxc_set_cpu_type(MXC_CPU_MX51); |
| 27 | } |
| 28 | |
| 29 | /* |
| 30 | * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by |
| 31 | * the Freescale marketing division. However this did not remove the |
| 32 | * hardware from the chip which still needs to be configured for proper |
| 33 | * IPU support. |
| 34 | */ |
| 35 | #define MX51_MIPI_HSC_BASE 0x83fdc000 |
| 36 | static void __init imx51_ipu_mipi_setup(void) |
| 37 | { |
| 38 | void __iomem *hsc_addr; |
| 39 | |
| 40 | hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K); |
| 41 | WARN_ON(!hsc_addr); |
| 42 | |
| 43 | /* setup MIPI module to legacy mode */ |
| 44 | imx_writel(0xf00, hsc_addr); |
| 45 | |
| 46 | /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ |
| 47 | imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); |
| 48 | |
| 49 | iounmap(hsc_addr); |
| 50 | } |
| 51 | |
| 52 | static void __init imx51_m4if_setup(void) |
| 53 | { |
| 54 | void __iomem *m4if_base; |
| 55 | struct device_node *np; |
| 56 | |
| 57 | np = of_find_compatible_node(NULL, NULL, "fsl,imx51-m4if"); |
| 58 | if (!np) |
| 59 | return; |
| 60 | |
| 61 | m4if_base = of_iomap(np, 0); |
| 62 | of_node_put(np); |
| 63 | if (!m4if_base) { |
| 64 | pr_err("Unable to map M4IF registers\n"); |
| 65 | return; |
| 66 | } |
| 67 | |
| 68 | /* |
| 69 | * Configure VPU and IPU with higher priorities |
| 70 | * in order to avoid artifacts during video playback |
| 71 | */ |
| 72 | writel_relaxed(0x00000203, m4if_base + 0x40); |
| 73 | writel_relaxed(0x00000000, m4if_base + 0x44); |
| 74 | writel_relaxed(0x00120125, m4if_base + 0x9c); |
| 75 | writel_relaxed(0x001901A3, m4if_base + 0x48); |
| 76 | iounmap(m4if_base); |
| 77 | } |
| 78 | |
| 79 | static void __init imx51_dt_init(void) |
| 80 | { |
| 81 | imx51_ipu_mipi_setup(); |
| 82 | imx_src_init(); |
| 83 | imx51_m4if_setup(); |
| 84 | imx5_pmu_init(); |
| 85 | imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); |
| 86 | } |
| 87 | |
| 88 | static void __init imx51_init_late(void) |
| 89 | { |
| 90 | mx51_neon_fixup(); |
| 91 | imx51_pm_init(); |
| 92 | } |
| 93 | |
| 94 | static const char * const imx51_dt_board_compat[] __initconst = { |
| 95 | "fsl,imx51", |
| 96 | NULL |
| 97 | }; |
| 98 | |
| 99 | DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)") |
| 100 | .init_early = imx51_init_early, |
| 101 | .init_machine = imx51_dt_init, |
| 102 | .init_late = imx51_init_late, |
| 103 | .dt_compat = imx51_dt_board_compat, |
| 104 | MACHINE_END |