| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 
|  | 2 | /* | 
|  | 3 | * OMAP2 clock function prototypes and macros | 
|  | 4 | * | 
|  | 5 | * Copyright (C) 2005-2010 Texas Instruments, Inc. | 
|  | 6 | * Copyright (C) 2004-2010 Nokia Corporation | 
|  | 7 | */ | 
|  | 8 |  | 
|  | 9 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H | 
|  | 10 | #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H | 
|  | 11 |  | 
|  | 12 | #include <linux/clk-provider.h> | 
|  | 13 | #include "clock.h" | 
|  | 14 |  | 
|  | 15 | unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, | 
|  | 16 | unsigned long parent_rate); | 
|  | 17 | int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, | 
|  | 18 | unsigned long parent_rate); | 
|  | 19 | long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, | 
|  | 20 | unsigned long *parent_rate); | 
|  | 21 | unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk, | 
|  | 22 | unsigned long parent_rate); | 
|  | 23 | unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, | 
|  | 24 | unsigned long parent_rate); | 
|  | 25 | void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw); | 
|  | 26 | unsigned long omap2xxx_clk_get_core_rate(void); | 
|  | 27 | u32 omap2xxx_get_sysclkdiv(void); | 
|  | 28 | void omap2xxx_clk_prepare_for_reboot(void); | 
|  | 29 | void omap2xxx_clkt_vps_check_bootloader_rates(void); | 
|  | 30 | void omap2xxx_clkt_vps_late_init(void); | 
|  | 31 |  | 
|  | 32 | #ifdef CONFIG_SOC_OMAP2420 | 
|  | 33 | int omap2420_clk_init(void); | 
|  | 34 | #else | 
|  | 35 | #define omap2420_clk_init()	do { } while(0) | 
|  | 36 | #endif | 
|  | 37 |  | 
|  | 38 | #ifdef CONFIG_SOC_OMAP2430 | 
|  | 39 | int omap2430_clk_init(void); | 
|  | 40 | #else | 
|  | 41 | #define omap2430_clk_init()	do { } while(0) | 
|  | 42 | #endif | 
|  | 43 |  | 
|  | 44 | extern struct clk_hw *dclk_hw; | 
|  | 45 |  | 
|  | 46 | #endif |