| xj | b04a402 | 2021-11-25 15:01:52 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2019 MediaTek Inc. |
| 4 | * Author: Argus Lin <argus.lin@mediatek.com> |
| 5 | */ |
| 6 | #define DEBUG |
| 7 | |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/regmap.h> |
| 12 | #include <linux/reset.h> |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/err.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_device.h> |
| 19 | #include <linux/of_address.h> |
| 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/slab.h> |
| 22 | #include <linux/sched/clock.h> |
| 23 | #include <linux/seq_file.h> |
| 24 | #include <linux/uaccess.h> |
| 25 | #include <linux/debugfs.h> |
| 26 | #include "spmi_sw.h" |
| 27 | |
| 28 | enum pmif_dbg_regs { |
| 29 | PMIF_INIT_DONE, |
| 30 | PMIF_INF_BUSY_STA, |
| 31 | PMIF_OTHER_BUSY_STA_0, |
| 32 | PMIF_OTHER_BUSY_STA_1, |
| 33 | PMIF_IRQ_EVENT_EN_0, |
| 34 | PMIF_IRQ_FLAG_0, |
| 35 | PMIF_IRQ_CLR_0, |
| 36 | PMIF_IRQ_EVENT_EN_1, |
| 37 | PMIF_IRQ_FLAG_1, |
| 38 | PMIF_IRQ_CLR_1, |
| 39 | PMIF_IRQ_EVENT_EN_2, |
| 40 | PMIF_IRQ_FLAG_2, |
| 41 | PMIF_IRQ_CLR_2, |
| 42 | PMIF_IRQ_EVENT_EN_3, |
| 43 | PMIF_IRQ_FLAG_3, |
| 44 | PMIF_IRQ_CLR_3, |
| 45 | PMIF_IRQ_EVENT_EN_4, |
| 46 | PMIF_IRQ_FLAG_4, |
| 47 | PMIF_IRQ_CLR_4, |
| 48 | PMIF_WDT_EVENT_EN_0, |
| 49 | PMIF_WDT_FLAG_0, |
| 50 | PMIF_WDT_EVENT_EN_1, |
| 51 | PMIF_WDT_FLAG_1, |
| 52 | PMIF_MONITOR_CTRL, |
| 53 | PMIF_MONITOR_TARGET_CHAN_0, |
| 54 | PMIF_MONITOR_TARGET_CHAN_1, |
| 55 | PMIF_MONITOR_TARGET_CHAN_2, |
| 56 | PMIF_MONITOR_TARGET_CHAN_3, |
| 57 | PMIF_MONITOR_TARGET_CHAN_4, |
| 58 | PMIF_MONITOR_TARGET_CHAN_5, |
| 59 | PMIF_MONITOR_TARGET_CHAN_6, |
| 60 | PMIF_MONITOR_TARGET_CHAN_7, |
| 61 | PMIF_MONITOR_TARGET_WRITE, |
| 62 | PMIF_MONITOR_TARGET_SLVID_0, |
| 63 | PMIF_MONITOR_TARGET_SLVID_1, |
| 64 | PMIF_MONITOR_TARGET_ADDR_0, |
| 65 | PMIF_MONITOR_TARGET_ADDR_1, |
| 66 | PMIF_MONITOR_TARGET_ADDR_2, |
| 67 | PMIF_MONITOR_TARGET_ADDR_3, |
| 68 | PMIF_MONITOR_TARGET_ADDR_4, |
| 69 | PMIF_MONITOR_TARGET_ADDR_5, |
| 70 | PMIF_MONITOR_TARGET_ADDR_6, |
| 71 | PMIF_MONITOR_TARGET_ADDR_7, |
| 72 | PMIF_MONITOR_TARGET_WDATA_0, |
| 73 | PMIF_MONITOR_TARGET_WDATA_1, |
| 74 | PMIF_MONITOR_TARGET_WDATA_2, |
| 75 | PMIF_MONITOR_TARGET_WDATA_3, |
| 76 | PMIF_MONITOR_TARGET_WDATA_4, |
| 77 | PMIF_MONITOR_TARGET_WDATA_5, |
| 78 | PMIF_MONITOR_TARGET_WDATA_6, |
| 79 | PMIF_MONITOR_TARGET_WDATA_7, |
| 80 | PMIF_MONITOR_STA, |
| 81 | PMIF_MONITOR_RECORD_0_0, |
| 82 | PMIF_MONITOR_RECORD_0_1, |
| 83 | PMIF_MONITOR_RECORD_0_2, |
| 84 | PMIF_MONITOR_RECORD_0_3, |
| 85 | PMIF_MONITOR_RECORD_0_4, |
| 86 | PMIF_MONITOR_RECORD_1_0, |
| 87 | PMIF_MONITOR_RECORD_1_1, |
| 88 | PMIF_MONITOR_RECORD_1_2, |
| 89 | PMIF_MONITOR_RECORD_1_3, |
| 90 | PMIF_MONITOR_RECORD_1_4, |
| 91 | PMIF_MONITOR_RECORD_2_0, |
| 92 | PMIF_MONITOR_RECORD_2_1, |
| 93 | PMIF_MONITOR_RECORD_2_2, |
| 94 | PMIF_MONITOR_RECORD_2_3, |
| 95 | PMIF_MONITOR_RECORD_2_4, |
| 96 | PMIF_MONITOR_RECORD_3_0, |
| 97 | PMIF_MONITOR_RECORD_3_1, |
| 98 | PMIF_MONITOR_RECORD_3_2, |
| 99 | PMIF_MONITOR_RECORD_3_3, |
| 100 | PMIF_MONITOR_RECORD_3_4, |
| 101 | PMIF_MONITOR_RECORD_4_0, |
| 102 | PMIF_MONITOR_RECORD_4_1, |
| 103 | PMIF_MONITOR_RECORD_4_2, |
| 104 | PMIF_MONITOR_RECORD_4_3, |
| 105 | PMIF_MONITOR_RECORD_4_4, |
| 106 | PMIF_MONITOR_RECORD_5_0, |
| 107 | PMIF_MONITOR_RECORD_5_1, |
| 108 | PMIF_MONITOR_RECORD_5_2, |
| 109 | PMIF_MONITOR_RECORD_5_3, |
| 110 | PMIF_MONITOR_RECORD_5_4, |
| 111 | PMIF_MONITOR_RECORD_6_0, |
| 112 | PMIF_MONITOR_RECORD_6_1, |
| 113 | PMIF_MONITOR_RECORD_6_2, |
| 114 | PMIF_MONITOR_RECORD_6_3, |
| 115 | PMIF_MONITOR_RECORD_6_4, |
| 116 | PMIF_MONITOR_RECORD_7_0, |
| 117 | PMIF_MONITOR_RECORD_7_1, |
| 118 | PMIF_MONITOR_RECORD_7_2, |
| 119 | PMIF_MONITOR_RECORD_7_3, |
| 120 | PMIF_MONITOR_RECORD_7_4, |
| 121 | PMIF_MONITOR_RECORD_8_0, |
| 122 | PMIF_MONITOR_RECORD_8_1, |
| 123 | PMIF_MONITOR_RECORD_8_2, |
| 124 | PMIF_MONITOR_RECORD_8_3, |
| 125 | PMIF_MONITOR_RECORD_8_4, |
| 126 | PMIF_MONITOR_RECORD_9_0, |
| 127 | PMIF_MONITOR_RECORD_9_1, |
| 128 | PMIF_MONITOR_RECORD_9_2, |
| 129 | PMIF_MONITOR_RECORD_9_3, |
| 130 | PMIF_MONITOR_RECORD_9_4, |
| 131 | PMIF_MONITOR_RECORD_10_0, |
| 132 | PMIF_MONITOR_RECORD_10_1, |
| 133 | PMIF_MONITOR_RECORD_10_2, |
| 134 | PMIF_MONITOR_RECORD_10_3, |
| 135 | PMIF_MONITOR_RECORD_10_4, |
| 136 | PMIF_MONITOR_RECORD_11_0, |
| 137 | PMIF_MONITOR_RECORD_11_1, |
| 138 | PMIF_MONITOR_RECORD_11_2, |
| 139 | PMIF_MONITOR_RECORD_11_3, |
| 140 | PMIF_MONITOR_RECORD_11_4, |
| 141 | PMIF_MONITOR_RECORD_12_0, |
| 142 | PMIF_MONITOR_RECORD_12_1, |
| 143 | PMIF_MONITOR_RECORD_12_2, |
| 144 | PMIF_MONITOR_RECORD_12_3, |
| 145 | PMIF_MONITOR_RECORD_12_4, |
| 146 | PMIF_MONITOR_RECORD_13_0, |
| 147 | PMIF_MONITOR_RECORD_13_1, |
| 148 | PMIF_MONITOR_RECORD_13_2, |
| 149 | PMIF_MONITOR_RECORD_13_3, |
| 150 | PMIF_MONITOR_RECORD_13_4, |
| 151 | PMIF_MONITOR_RECORD_14_0, |
| 152 | PMIF_MONITOR_RECORD_14_1, |
| 153 | PMIF_MONITOR_RECORD_14_2, |
| 154 | PMIF_MONITOR_RECORD_14_3, |
| 155 | PMIF_MONITOR_RECORD_14_4, |
| 156 | PMIF_MONITOR_RECORD_15_0, |
| 157 | PMIF_MONITOR_RECORD_15_1, |
| 158 | PMIF_MONITOR_RECORD_15_2, |
| 159 | PMIF_MONITOR_RECORD_15_3, |
| 160 | PMIF_MONITOR_RECORD_15_4, |
| 161 | PMIF_MONITOR_RECORD_16_0, |
| 162 | PMIF_MONITOR_RECORD_16_1, |
| 163 | PMIF_MONITOR_RECORD_16_2, |
| 164 | PMIF_MONITOR_RECORD_16_3, |
| 165 | PMIF_MONITOR_RECORD_16_4, |
| 166 | PMIF_MONITOR_RECORD_17_0, |
| 167 | PMIF_MONITOR_RECORD_17_1, |
| 168 | PMIF_MONITOR_RECORD_17_2, |
| 169 | PMIF_MONITOR_RECORD_17_3, |
| 170 | PMIF_MONITOR_RECORD_17_4, |
| 171 | PMIF_MONITOR_RECORD_18_0, |
| 172 | PMIF_MONITOR_RECORD_18_1, |
| 173 | PMIF_MONITOR_RECORD_18_2, |
| 174 | PMIF_MONITOR_RECORD_18_3, |
| 175 | PMIF_MONITOR_RECORD_18_4, |
| 176 | PMIF_MONITOR_RECORD_19_0, |
| 177 | PMIF_MONITOR_RECORD_19_1, |
| 178 | PMIF_MONITOR_RECORD_19_2, |
| 179 | PMIF_MONITOR_RECORD_19_3, |
| 180 | PMIF_MONITOR_RECORD_19_4, |
| 181 | PMIF_MONITOR_RECORD_20_0, |
| 182 | PMIF_MONITOR_RECORD_20_1, |
| 183 | PMIF_MONITOR_RECORD_20_2, |
| 184 | PMIF_MONITOR_RECORD_20_3, |
| 185 | PMIF_MONITOR_RECORD_20_4, |
| 186 | PMIF_MONITOR_RECORD_21_0, |
| 187 | PMIF_MONITOR_RECORD_21_1, |
| 188 | PMIF_MONITOR_RECORD_21_2, |
| 189 | PMIF_MONITOR_RECORD_21_3, |
| 190 | PMIF_MONITOR_RECORD_21_4, |
| 191 | PMIF_MONITOR_RECORD_22_0, |
| 192 | PMIF_MONITOR_RECORD_22_1, |
| 193 | PMIF_MONITOR_RECORD_22_2, |
| 194 | PMIF_MONITOR_RECORD_22_3, |
| 195 | PMIF_MONITOR_RECORD_22_4, |
| 196 | PMIF_MONITOR_RECORD_23_0, |
| 197 | PMIF_MONITOR_RECORD_23_1, |
| 198 | PMIF_MONITOR_RECORD_23_2, |
| 199 | PMIF_MONITOR_RECORD_23_3, |
| 200 | PMIF_MONITOR_RECORD_23_4, |
| 201 | PMIF_MONITOR_RECORD_24_0, |
| 202 | PMIF_MONITOR_RECORD_24_1, |
| 203 | PMIF_MONITOR_RECORD_24_2, |
| 204 | PMIF_MONITOR_RECORD_24_3, |
| 205 | PMIF_MONITOR_RECORD_24_4, |
| 206 | PMIF_MONITOR_RECORD_25_0, |
| 207 | PMIF_MONITOR_RECORD_25_1, |
| 208 | PMIF_MONITOR_RECORD_25_2, |
| 209 | PMIF_MONITOR_RECORD_25_3, |
| 210 | PMIF_MONITOR_RECORD_25_4, |
| 211 | PMIF_MONITOR_RECORD_26_0, |
| 212 | PMIF_MONITOR_RECORD_26_1, |
| 213 | PMIF_MONITOR_RECORD_26_2, |
| 214 | PMIF_MONITOR_RECORD_26_3, |
| 215 | PMIF_MONITOR_RECORD_26_4, |
| 216 | PMIF_MONITOR_RECORD_27_0, |
| 217 | PMIF_MONITOR_RECORD_27_1, |
| 218 | PMIF_MONITOR_RECORD_27_2, |
| 219 | PMIF_MONITOR_RECORD_27_3, |
| 220 | PMIF_MONITOR_RECORD_27_4, |
| 221 | PMIF_MONITOR_RECORD_28_0, |
| 222 | PMIF_MONITOR_RECORD_28_1, |
| 223 | PMIF_MONITOR_RECORD_28_2, |
| 224 | PMIF_MONITOR_RECORD_28_3, |
| 225 | PMIF_MONITOR_RECORD_28_4, |
| 226 | PMIF_MONITOR_RECORD_29_0, |
| 227 | PMIF_MONITOR_RECORD_29_1, |
| 228 | PMIF_MONITOR_RECORD_29_2, |
| 229 | PMIF_MONITOR_RECORD_29_3, |
| 230 | PMIF_MONITOR_RECORD_29_4, |
| 231 | PMIF_MONITOR_RECORD_30_0, |
| 232 | PMIF_MONITOR_RECORD_30_1, |
| 233 | PMIF_MONITOR_RECORD_30_2, |
| 234 | PMIF_MONITOR_RECORD_30_3, |
| 235 | PMIF_MONITOR_RECORD_30_4, |
| 236 | PMIF_MONITOR_RECORD_31_0, |
| 237 | PMIF_MONITOR_RECORD_31_1, |
| 238 | PMIF_MONITOR_RECORD_31_2, |
| 239 | PMIF_MONITOR_RECORD_31_3, |
| 240 | PMIF_MONITOR_RECORD_31_4, |
| 241 | PMIF_DEBUG_CTRL, |
| 242 | PMIF_RESERVED_0, |
| 243 | PMIF_SWINF_0_ACC, |
| 244 | PMIF_SWINF_0_WDATA_31_0, |
| 245 | PMIF_SWINF_0_WDATA_63_32, |
| 246 | PMIF_SWINF_0_RDATA_31_0, |
| 247 | PMIF_SWINF_0_RDATA_63_32, |
| 248 | PMIF_SWINF_0_VLD_CLR, |
| 249 | PMIF_SWINF_0_STA, |
| 250 | PMIF_SWINF_1_ACC, |
| 251 | PMIF_SWINF_1_WDATA_31_0, |
| 252 | PMIF_SWINF_1_WDATA_63_32, |
| 253 | PMIF_SWINF_1_RDATA_31_0, |
| 254 | PMIF_SWINF_1_RDATA_63_32, |
| 255 | PMIF_SWINF_1_VLD_CLR, |
| 256 | PMIF_SWINF_1_STA, |
| 257 | PMIF_SWINF_2_ACC, |
| 258 | PMIF_SWINF_2_WDATA_31_0, |
| 259 | PMIF_SWINF_2_WDATA_63_32, |
| 260 | PMIF_SWINF_2_RDATA_31_0, |
| 261 | PMIF_SWINF_2_RDATA_63_32, |
| 262 | PMIF_SWINF_2_VLD_CLR, |
| 263 | PMIF_SWINF_2_STA, |
| 264 | PMIF_SWINF_3_ACC, |
| 265 | PMIF_SWINF_3_WDATA_31_0, |
| 266 | PMIF_SWINF_3_WDATA_63_32, |
| 267 | PMIF_SWINF_3_RDATA_31_0, |
| 268 | PMIF_SWINF_3_RDATA_63_32, |
| 269 | PMIF_SWINF_3_VLD_CLR, |
| 270 | PMIF_SWINF_3_STA, |
| 271 | |
| 272 | PMIC_ACC_VIO_INFO_0, |
| 273 | PMIC_ACC_VIO_INFO_1, |
| 274 | PMIC_ACC_VIO_INFO_2, |
| 275 | PMIC_ACC_VIO_INFO_3, |
| 276 | PMIC_ACC_VIO_INFO_4, |
| 277 | PMIC_ACC_VIO_INFO_5, |
| 278 | PMIC_ACC_SCP_VIO_INFO_0, |
| 279 | PMIC_ACC_SCP_VIO_INFO_1, |
| 280 | PMIC_ACC_SCP_VIO_INFO_2, |
| 281 | PMIC_ACC_SCP_VIO_INFO_3, |
| 282 | PMIC_ACC_SCP_VIO_INFO_4, |
| 283 | PMIC_ACC_SCP_VIO_INFO_5, |
| 284 | PMIF_ACC_VIO_INFO_0, |
| 285 | PMIF_ACC_VIO_INFO_1, |
| 286 | PMIF_ACC_VIO_INFO_2, |
| 287 | /* MT6853/MT6880 new register */ |
| 288 | PMIC_ALL_ACC_VIO_INFO_0, |
| 289 | PMIC_ALL_ACC_VIO_INFO_1, |
| 290 | }; |
| 291 | |
| 292 | static const u32 mt6880_pmif_dbg_regs[] = { |
| 293 | [PMIF_INIT_DONE] = 0x0000, |
| 294 | [PMIF_INF_BUSY_STA] = 0x0018, |
| 295 | [PMIF_OTHER_BUSY_STA_0] = 0x001C, |
| 296 | [PMIF_OTHER_BUSY_STA_1] = 0x0020, |
| 297 | [PMIF_IRQ_EVENT_EN_0] = 0x0420, |
| 298 | [PMIF_IRQ_FLAG_0] = 0x0428, |
| 299 | [PMIF_IRQ_CLR_0] = 0x042C, |
| 300 | [PMIF_IRQ_EVENT_EN_1] = 0x0430, |
| 301 | [PMIF_IRQ_FLAG_1] = 0x0438, |
| 302 | [PMIF_IRQ_CLR_1] = 0x043C, |
| 303 | [PMIF_IRQ_EVENT_EN_2] = 0x0440, |
| 304 | [PMIF_IRQ_FLAG_2] = 0x0448, |
| 305 | [PMIF_IRQ_CLR_2] = 0x044C, |
| 306 | [PMIF_IRQ_EVENT_EN_3] = 0x0450, |
| 307 | [PMIF_IRQ_FLAG_3] = 0x0458, |
| 308 | [PMIF_IRQ_CLR_3] = 0x045C, |
| 309 | [PMIF_IRQ_EVENT_EN_4] = 0x0460, |
| 310 | [PMIF_IRQ_FLAG_4] = 0x0468, |
| 311 | [PMIF_IRQ_CLR_4] = 0x046C, |
| 312 | [PMIF_WDT_EVENT_EN_0] = 0x0474, |
| 313 | [PMIF_WDT_FLAG_0] = 0x0478, |
| 314 | [PMIF_WDT_EVENT_EN_1] = 0x047C, |
| 315 | [PMIF_WDT_FLAG_1] = 0x0480, |
| 316 | [PMIF_MONITOR_CTRL] = 0x0484, |
| 317 | [PMIF_MONITOR_TARGET_CHAN_0] = 0x0488, |
| 318 | [PMIF_MONITOR_TARGET_CHAN_1] = 0x048C, |
| 319 | [PMIF_MONITOR_TARGET_CHAN_2] = 0x0490, |
| 320 | [PMIF_MONITOR_TARGET_CHAN_3] = 0x0494, |
| 321 | [PMIF_MONITOR_TARGET_CHAN_4] = 0x0498, |
| 322 | [PMIF_MONITOR_TARGET_CHAN_5] = 0x049C, |
| 323 | [PMIF_MONITOR_TARGET_CHAN_6] = 0x04A0, |
| 324 | [PMIF_MONITOR_TARGET_CHAN_7] = 0x04A4, |
| 325 | [PMIF_MONITOR_TARGET_WRITE] = 0x04A8, |
| 326 | [PMIF_MONITOR_TARGET_SLVID_0] = 0x04AC, |
| 327 | [PMIF_MONITOR_TARGET_SLVID_1] = 0x04B0, |
| 328 | [PMIF_MONITOR_TARGET_ADDR_0] = 0x04B4, |
| 329 | [PMIF_MONITOR_TARGET_ADDR_1] = 0x04B8, |
| 330 | [PMIF_MONITOR_TARGET_ADDR_2] = 0x04BC, |
| 331 | [PMIF_MONITOR_TARGET_ADDR_3] = 0x04C0, |
| 332 | [PMIF_MONITOR_TARGET_ADDR_4] = 0x04C4, |
| 333 | [PMIF_MONITOR_TARGET_ADDR_5] = 0x04C8, |
| 334 | [PMIF_MONITOR_TARGET_ADDR_6] = 0x04CC, |
| 335 | [PMIF_MONITOR_TARGET_ADDR_7] = 0x04D0, |
| 336 | [PMIF_MONITOR_TARGET_WDATA_0] = 0x04D4, |
| 337 | [PMIF_MONITOR_TARGET_WDATA_1] = 0x04D8, |
| 338 | [PMIF_MONITOR_TARGET_WDATA_2] = 0x04DC, |
| 339 | [PMIF_MONITOR_TARGET_WDATA_3] = 0x04E0, |
| 340 | [PMIF_MONITOR_TARGET_WDATA_4] = 0x04E4, |
| 341 | [PMIF_MONITOR_TARGET_WDATA_5] = 0x04E8, |
| 342 | [PMIF_MONITOR_TARGET_WDATA_6] = 0x04EC, |
| 343 | [PMIF_MONITOR_TARGET_WDATA_7] = 0x04F0, |
| 344 | [PMIF_MONITOR_STA] = 0x04F4, |
| 345 | [PMIF_MONITOR_RECORD_0_0] = 0x04F8, |
| 346 | [PMIF_MONITOR_RECORD_0_1] = 0x04FC, |
| 347 | [PMIF_MONITOR_RECORD_0_2] = 0x0500, |
| 348 | [PMIF_MONITOR_RECORD_0_3] = 0x0504, |
| 349 | [PMIF_MONITOR_RECORD_0_4] = 0x0508, |
| 350 | [PMIF_MONITOR_RECORD_1_0] = 0x050C, |
| 351 | [PMIF_MONITOR_RECORD_1_1] = 0x0510, |
| 352 | [PMIF_MONITOR_RECORD_1_2] = 0x0514, |
| 353 | [PMIF_MONITOR_RECORD_1_3] = 0x0518, |
| 354 | [PMIF_MONITOR_RECORD_1_4] = 0x051C, |
| 355 | [PMIF_MONITOR_RECORD_2_0] = 0x0520, |
| 356 | [PMIF_MONITOR_RECORD_2_1] = 0x0524, |
| 357 | [PMIF_MONITOR_RECORD_2_2] = 0x0528, |
| 358 | [PMIF_MONITOR_RECORD_2_3] = 0x052C, |
| 359 | [PMIF_MONITOR_RECORD_2_4] = 0x0530, |
| 360 | [PMIF_MONITOR_RECORD_3_0] = 0x0534, |
| 361 | [PMIF_MONITOR_RECORD_3_1] = 0x0538, |
| 362 | [PMIF_MONITOR_RECORD_3_2] = 0x053C, |
| 363 | [PMIF_MONITOR_RECORD_3_3] = 0x0540, |
| 364 | [PMIF_MONITOR_RECORD_3_4] = 0x0544, |
| 365 | [PMIF_MONITOR_RECORD_4_0] = 0x0548, |
| 366 | [PMIF_MONITOR_RECORD_4_1] = 0x054C, |
| 367 | [PMIF_MONITOR_RECORD_4_2] = 0x0550, |
| 368 | [PMIF_MONITOR_RECORD_4_3] = 0x0554, |
| 369 | [PMIF_MONITOR_RECORD_4_4] = 0x0558, |
| 370 | [PMIF_MONITOR_RECORD_5_0] = 0x055C, |
| 371 | [PMIF_MONITOR_RECORD_5_1] = 0x0560, |
| 372 | [PMIF_MONITOR_RECORD_5_2] = 0x0564, |
| 373 | [PMIF_MONITOR_RECORD_5_3] = 0x0568, |
| 374 | [PMIF_MONITOR_RECORD_5_4] = 0x056C, |
| 375 | [PMIF_MONITOR_RECORD_6_0] = 0x0570, |
| 376 | [PMIF_MONITOR_RECORD_6_1] = 0x0574, |
| 377 | [PMIF_MONITOR_RECORD_6_2] = 0x0578, |
| 378 | [PMIF_MONITOR_RECORD_6_3] = 0x057C, |
| 379 | [PMIF_MONITOR_RECORD_6_4] = 0x0580, |
| 380 | [PMIF_MONITOR_RECORD_7_0] = 0x0584, |
| 381 | [PMIF_MONITOR_RECORD_7_1] = 0x0588, |
| 382 | [PMIF_MONITOR_RECORD_7_2] = 0x058C, |
| 383 | [PMIF_MONITOR_RECORD_7_3] = 0x0590, |
| 384 | [PMIF_MONITOR_RECORD_7_4] = 0x0594, |
| 385 | [PMIF_MONITOR_RECORD_8_0] = 0x0598, |
| 386 | [PMIF_MONITOR_RECORD_8_1] = 0x059C, |
| 387 | [PMIF_MONITOR_RECORD_8_2] = 0x05A0, |
| 388 | [PMIF_MONITOR_RECORD_8_3] = 0x05A4, |
| 389 | [PMIF_MONITOR_RECORD_8_4] = 0x05A8, |
| 390 | [PMIF_MONITOR_RECORD_9_0] = 0x05AC, |
| 391 | [PMIF_MONITOR_RECORD_9_1] = 0x05B0, |
| 392 | [PMIF_MONITOR_RECORD_9_2] = 0x05B4, |
| 393 | [PMIF_MONITOR_RECORD_9_3] = 0x05B8, |
| 394 | [PMIF_MONITOR_RECORD_9_4] = 0x05BC, |
| 395 | [PMIF_MONITOR_RECORD_10_0] = 0x05C0, |
| 396 | [PMIF_MONITOR_RECORD_10_1] = 0x05C4, |
| 397 | [PMIF_MONITOR_RECORD_10_2] = 0x05C8, |
| 398 | [PMIF_MONITOR_RECORD_10_3] = 0x05CC, |
| 399 | [PMIF_MONITOR_RECORD_10_4] = 0x05D0, |
| 400 | [PMIF_MONITOR_RECORD_11_0] = 0x05D4, |
| 401 | [PMIF_MONITOR_RECORD_11_1] = 0x05D8, |
| 402 | [PMIF_MONITOR_RECORD_11_2] = 0x05DC, |
| 403 | [PMIF_MONITOR_RECORD_11_3] = 0x05E0, |
| 404 | [PMIF_MONITOR_RECORD_11_4] = 0x05E4, |
| 405 | [PMIF_MONITOR_RECORD_12_0] = 0x05E8, |
| 406 | [PMIF_MONITOR_RECORD_12_1] = 0x05EC, |
| 407 | [PMIF_MONITOR_RECORD_12_2] = 0x05F0, |
| 408 | [PMIF_MONITOR_RECORD_12_3] = 0x05F4, |
| 409 | [PMIF_MONITOR_RECORD_12_4] = 0x05F8, |
| 410 | [PMIF_MONITOR_RECORD_13_0] = 0x05FC, |
| 411 | [PMIF_MONITOR_RECORD_13_1] = 0x0600, |
| 412 | [PMIF_MONITOR_RECORD_13_2] = 0x0604, |
| 413 | [PMIF_MONITOR_RECORD_13_3] = 0x0608, |
| 414 | [PMIF_MONITOR_RECORD_13_4] = 0x060C, |
| 415 | [PMIF_MONITOR_RECORD_14_0] = 0x0610, |
| 416 | [PMIF_MONITOR_RECORD_14_1] = 0x0614, |
| 417 | [PMIF_MONITOR_RECORD_14_2] = 0x0618, |
| 418 | [PMIF_MONITOR_RECORD_14_3] = 0x061C, |
| 419 | [PMIF_MONITOR_RECORD_14_4] = 0x0620, |
| 420 | [PMIF_MONITOR_RECORD_15_0] = 0x0624, |
| 421 | [PMIF_MONITOR_RECORD_15_1] = 0x0628, |
| 422 | [PMIF_MONITOR_RECORD_15_2] = 0x062C, |
| 423 | [PMIF_MONITOR_RECORD_15_3] = 0x0630, |
| 424 | [PMIF_MONITOR_RECORD_15_4] = 0x0634, |
| 425 | [PMIF_MONITOR_RECORD_16_0] = 0x0638, |
| 426 | [PMIF_MONITOR_RECORD_16_1] = 0x063C, |
| 427 | [PMIF_MONITOR_RECORD_16_2] = 0x0640, |
| 428 | [PMIF_MONITOR_RECORD_16_3] = 0x0644, |
| 429 | [PMIF_MONITOR_RECORD_16_4] = 0x0648, |
| 430 | [PMIF_MONITOR_RECORD_17_0] = 0x064C, |
| 431 | [PMIF_MONITOR_RECORD_17_1] = 0x0650, |
| 432 | [PMIF_MONITOR_RECORD_17_2] = 0x0654, |
| 433 | [PMIF_MONITOR_RECORD_17_3] = 0x0658, |
| 434 | [PMIF_MONITOR_RECORD_17_4] = 0x065C, |
| 435 | [PMIF_MONITOR_RECORD_18_0] = 0x0660, |
| 436 | [PMIF_MONITOR_RECORD_18_1] = 0x0664, |
| 437 | [PMIF_MONITOR_RECORD_18_2] = 0x0668, |
| 438 | [PMIF_MONITOR_RECORD_18_3] = 0x066C, |
| 439 | [PMIF_MONITOR_RECORD_18_4] = 0x0670, |
| 440 | [PMIF_MONITOR_RECORD_19_0] = 0x0674, |
| 441 | [PMIF_MONITOR_RECORD_19_1] = 0x0678, |
| 442 | [PMIF_MONITOR_RECORD_19_2] = 0x067C, |
| 443 | [PMIF_MONITOR_RECORD_19_3] = 0x0680, |
| 444 | [PMIF_MONITOR_RECORD_19_4] = 0x0684, |
| 445 | [PMIF_MONITOR_RECORD_20_0] = 0x0688, |
| 446 | [PMIF_MONITOR_RECORD_20_1] = 0x068C, |
| 447 | [PMIF_MONITOR_RECORD_20_2] = 0x0690, |
| 448 | [PMIF_MONITOR_RECORD_20_3] = 0x0694, |
| 449 | [PMIF_MONITOR_RECORD_20_4] = 0x0698, |
| 450 | [PMIF_MONITOR_RECORD_21_0] = 0x069C, |
| 451 | [PMIF_MONITOR_RECORD_21_1] = 0x06A0, |
| 452 | [PMIF_MONITOR_RECORD_21_2] = 0x06A4, |
| 453 | [PMIF_MONITOR_RECORD_21_3] = 0x06A8, |
| 454 | [PMIF_MONITOR_RECORD_21_4] = 0x06AC, |
| 455 | [PMIF_MONITOR_RECORD_22_0] = 0x06B0, |
| 456 | [PMIF_MONITOR_RECORD_22_1] = 0x06B4, |
| 457 | [PMIF_MONITOR_RECORD_22_2] = 0x06B8, |
| 458 | [PMIF_MONITOR_RECORD_22_3] = 0x06BC, |
| 459 | [PMIF_MONITOR_RECORD_22_4] = 0x06C0, |
| 460 | [PMIF_MONITOR_RECORD_23_0] = 0x06C4, |
| 461 | [PMIF_MONITOR_RECORD_23_1] = 0x06C8, |
| 462 | [PMIF_MONITOR_RECORD_23_2] = 0x06CC, |
| 463 | [PMIF_MONITOR_RECORD_23_3] = 0x06D0, |
| 464 | [PMIF_MONITOR_RECORD_23_4] = 0x06D4, |
| 465 | [PMIF_MONITOR_RECORD_24_0] = 0x06D8, |
| 466 | [PMIF_MONITOR_RECORD_24_1] = 0x06DC, |
| 467 | [PMIF_MONITOR_RECORD_24_2] = 0x06E0, |
| 468 | [PMIF_MONITOR_RECORD_24_3] = 0x06E4, |
| 469 | [PMIF_MONITOR_RECORD_24_4] = 0x06E8, |
| 470 | [PMIF_MONITOR_RECORD_25_0] = 0x06EC, |
| 471 | [PMIF_MONITOR_RECORD_25_1] = 0x06F0, |
| 472 | [PMIF_MONITOR_RECORD_25_2] = 0x06F4, |
| 473 | [PMIF_MONITOR_RECORD_25_3] = 0x06F8, |
| 474 | [PMIF_MONITOR_RECORD_25_4] = 0x06FC, |
| 475 | [PMIF_MONITOR_RECORD_26_0] = 0x0700, |
| 476 | [PMIF_MONITOR_RECORD_26_1] = 0x0704, |
| 477 | [PMIF_MONITOR_RECORD_26_2] = 0x0708, |
| 478 | [PMIF_MONITOR_RECORD_26_3] = 0x070C, |
| 479 | [PMIF_MONITOR_RECORD_26_4] = 0x0710, |
| 480 | [PMIF_MONITOR_RECORD_27_0] = 0x0714, |
| 481 | [PMIF_MONITOR_RECORD_27_1] = 0x0718, |
| 482 | [PMIF_MONITOR_RECORD_27_2] = 0x071C, |
| 483 | [PMIF_MONITOR_RECORD_27_3] = 0x0720, |
| 484 | [PMIF_MONITOR_RECORD_27_4] = 0x0724, |
| 485 | [PMIF_MONITOR_RECORD_28_0] = 0x0728, |
| 486 | [PMIF_MONITOR_RECORD_28_1] = 0x072C, |
| 487 | [PMIF_MONITOR_RECORD_28_2] = 0x0730, |
| 488 | [PMIF_MONITOR_RECORD_28_3] = 0x0734, |
| 489 | [PMIF_MONITOR_RECORD_28_4] = 0x0738, |
| 490 | [PMIF_MONITOR_RECORD_29_0] = 0x073C, |
| 491 | [PMIF_MONITOR_RECORD_29_1] = 0x0740, |
| 492 | [PMIF_MONITOR_RECORD_29_2] = 0x0744, |
| 493 | [PMIF_MONITOR_RECORD_29_3] = 0x0748, |
| 494 | [PMIF_MONITOR_RECORD_29_4] = 0x074C, |
| 495 | [PMIF_MONITOR_RECORD_30_0] = 0x0750, |
| 496 | [PMIF_MONITOR_RECORD_30_1] = 0x0754, |
| 497 | [PMIF_MONITOR_RECORD_30_2] = 0x0758, |
| 498 | [PMIF_MONITOR_RECORD_30_3] = 0x075C, |
| 499 | [PMIF_MONITOR_RECORD_30_4] = 0x0760, |
| 500 | [PMIF_MONITOR_RECORD_31_0] = 0x0764, |
| 501 | [PMIF_MONITOR_RECORD_31_1] = 0x0768, |
| 502 | [PMIF_MONITOR_RECORD_31_2] = 0x076C, |
| 503 | [PMIF_MONITOR_RECORD_31_3] = 0x0770, |
| 504 | [PMIF_MONITOR_RECORD_31_4] = 0x0774, |
| 505 | [PMIF_DEBUG_CTRL] = 0x0778, |
| 506 | [PMIF_RESERVED_0] = 0x0780, |
| 507 | [PMIF_SWINF_0_ACC] = 0x0800, |
| 508 | [PMIF_SWINF_0_WDATA_31_0] = 0x0804, |
| 509 | [PMIF_SWINF_0_RDATA_31_0] = 0x0814, |
| 510 | [PMIF_SWINF_0_VLD_CLR] = 0x0824, |
| 511 | [PMIF_SWINF_0_STA] = 0x0828, |
| 512 | [PMIF_SWINF_1_ACC] = 0x0840, |
| 513 | [PMIF_SWINF_1_WDATA_31_0] = 0x0844, |
| 514 | [PMIF_SWINF_1_RDATA_31_0] = 0x0854, |
| 515 | [PMIF_SWINF_1_VLD_CLR] = 0x0864, |
| 516 | [PMIF_SWINF_1_STA] = 0x0868, |
| 517 | [PMIF_SWINF_2_ACC] = 0x0880, |
| 518 | [PMIF_SWINF_2_WDATA_31_0] = 0x0884, |
| 519 | [PMIF_SWINF_2_RDATA_31_0] = 0x0894, |
| 520 | [PMIF_SWINF_2_VLD_CLR] = 0x08A4, |
| 521 | [PMIF_SWINF_2_STA] = 0x08A8, |
| 522 | [PMIF_SWINF_3_ACC] = 0x08C0, |
| 523 | [PMIF_SWINF_3_WDATA_31_0] = 0x08C4, |
| 524 | [PMIF_SWINF_3_RDATA_31_0] = 0x08D4, |
| 525 | [PMIF_SWINF_3_VLD_CLR] = 0x08E4, |
| 526 | [PMIF_SWINF_3_STA] = 0x08E8, |
| 527 | [PMIC_ACC_VIO_INFO_0] = 0x0950, |
| 528 | [PMIC_ACC_VIO_INFO_1] = 0x0954, |
| 529 | [PMIC_ACC_VIO_INFO_2] = 0x0958, |
| 530 | [PMIC_ACC_VIO_INFO_3] = 0x095C, |
| 531 | [PMIC_ACC_VIO_INFO_4] = 0x0960, |
| 532 | [PMIC_ACC_VIO_INFO_5] = 0x0964, |
| 533 | [PMIC_ACC_SCP_VIO_INFO_0] = 0x0968, |
| 534 | [PMIC_ACC_SCP_VIO_INFO_1] = 0x096C, |
| 535 | [PMIC_ACC_SCP_VIO_INFO_2] = 0x0970, |
| 536 | [PMIC_ACC_SCP_VIO_INFO_3] = 0x0974, |
| 537 | [PMIC_ACC_SCP_VIO_INFO_4] = 0x0978, |
| 538 | [PMIC_ACC_SCP_VIO_INFO_5] = 0x097C, |
| 539 | [PMIF_ACC_VIO_INFO_0] = 0x0980, |
| 540 | [PMIF_ACC_VIO_INFO_1] = 0x0984, |
| 541 | [PMIF_ACC_VIO_INFO_2] = 0x0988, |
| 542 | [PMIC_ALL_ACC_VIO_INFO_0] = 0x098C, |
| 543 | [PMIC_ALL_ACC_VIO_INFO_1] = 0x0990, |
| 544 | }; |
| 545 | |
| 546 | static const u32 mt6873_pmif_dbg_regs[] = { |
| 547 | [PMIF_INIT_DONE] = 0x0000, |
| 548 | [PMIF_INF_BUSY_STA] = 0x0018, |
| 549 | [PMIF_OTHER_BUSY_STA_0] = 0x001C, |
| 550 | [PMIF_OTHER_BUSY_STA_1] = 0x0020, |
| 551 | [PMIF_IRQ_EVENT_EN_0] = 0x0418, |
| 552 | [PMIF_IRQ_FLAG_0] = 0x0420, |
| 553 | [PMIF_IRQ_CLR_0] = 0x0424, |
| 554 | [PMIF_IRQ_EVENT_EN_1] = 0x0428, |
| 555 | [PMIF_IRQ_FLAG_1] = 0x0430, |
| 556 | [PMIF_IRQ_CLR_1] = 0x0434, |
| 557 | [PMIF_IRQ_EVENT_EN_2] = 0x0438, |
| 558 | [PMIF_IRQ_FLAG_2] = 0x0440, |
| 559 | [PMIF_IRQ_CLR_2] = 0x0444, |
| 560 | [PMIF_IRQ_EVENT_EN_3] = 0x0448, |
| 561 | [PMIF_IRQ_FLAG_3] = 0x0450, |
| 562 | [PMIF_IRQ_CLR_3] = 0x0454, |
| 563 | [PMIF_IRQ_EVENT_EN_4] = 0x0458, |
| 564 | [PMIF_IRQ_FLAG_4] = 0x0460, |
| 565 | [PMIF_IRQ_CLR_4] = 0x0464, |
| 566 | [PMIF_WDT_EVENT_EN_0] = 0x046C, |
| 567 | [PMIF_WDT_FLAG_0] = 0x0470, |
| 568 | [PMIF_WDT_EVENT_EN_1] = 0x0474, |
| 569 | [PMIF_WDT_FLAG_1] = 0x0478, |
| 570 | [PMIF_MONITOR_CTRL] = 0x047C, |
| 571 | [PMIF_MONITOR_TARGET_CHAN_0] = 0x0480, |
| 572 | [PMIF_MONITOR_TARGET_CHAN_1] = 0x0484, |
| 573 | [PMIF_MONITOR_TARGET_CHAN_2] = 0x0488, |
| 574 | [PMIF_MONITOR_TARGET_CHAN_3] = 0x048C, |
| 575 | [PMIF_MONITOR_TARGET_CHAN_4] = 0x0490, |
| 576 | [PMIF_MONITOR_TARGET_CHAN_5] = 0x0494, |
| 577 | [PMIF_MONITOR_TARGET_CHAN_6] = 0x0498, |
| 578 | [PMIF_MONITOR_TARGET_CHAN_7] = 0x049C, |
| 579 | [PMIF_MONITOR_TARGET_WRITE] = 0x04A0, |
| 580 | [PMIF_MONITOR_TARGET_SLVID_0] = 0x04A4, |
| 581 | [PMIF_MONITOR_TARGET_SLVID_1] = 0x04A8, |
| 582 | [PMIF_MONITOR_TARGET_ADDR_0] = 0x04AC, |
| 583 | [PMIF_MONITOR_TARGET_ADDR_1] = 0x04B0, |
| 584 | [PMIF_MONITOR_TARGET_ADDR_2] = 0x04B4, |
| 585 | [PMIF_MONITOR_TARGET_ADDR_3] = 0x04B8, |
| 586 | [PMIF_MONITOR_TARGET_ADDR_4] = 0x04BC, |
| 587 | [PMIF_MONITOR_TARGET_ADDR_5] = 0x04C0, |
| 588 | [PMIF_MONITOR_TARGET_ADDR_6] = 0x04C4, |
| 589 | [PMIF_MONITOR_TARGET_ADDR_7] = 0x04C8, |
| 590 | [PMIF_MONITOR_TARGET_WDATA_0] = 0x04CC, |
| 591 | [PMIF_MONITOR_TARGET_WDATA_1] = 0x04D0, |
| 592 | [PMIF_MONITOR_TARGET_WDATA_2] = 0x04D4, |
| 593 | [PMIF_MONITOR_TARGET_WDATA_3] = 0x04D8, |
| 594 | [PMIF_MONITOR_TARGET_WDATA_4] = 0x04DC, |
| 595 | [PMIF_MONITOR_TARGET_WDATA_5] = 0x04E0, |
| 596 | [PMIF_MONITOR_TARGET_WDATA_6] = 0x04E4, |
| 597 | [PMIF_MONITOR_TARGET_WDATA_7] = 0x04E8, |
| 598 | [PMIF_MONITOR_STA] = 0x04EC, |
| 599 | [PMIF_MONITOR_RECORD_0_0] = 0x04F0, |
| 600 | [PMIF_MONITOR_RECORD_0_1] = 0x04F4, |
| 601 | [PMIF_MONITOR_RECORD_0_2] = 0x04F8, |
| 602 | [PMIF_MONITOR_RECORD_0_3] = 0x04FC, |
| 603 | [PMIF_MONITOR_RECORD_0_4] = 0x0500, |
| 604 | [PMIF_MONITOR_RECORD_1_0] = 0x0504, |
| 605 | [PMIF_MONITOR_RECORD_1_1] = 0x0508, |
| 606 | [PMIF_MONITOR_RECORD_1_2] = 0x050C, |
| 607 | [PMIF_MONITOR_RECORD_1_3] = 0x0510, |
| 608 | [PMIF_MONITOR_RECORD_1_4] = 0x0514, |
| 609 | [PMIF_MONITOR_RECORD_2_0] = 0x0518, |
| 610 | [PMIF_MONITOR_RECORD_2_1] = 0x051C, |
| 611 | [PMIF_MONITOR_RECORD_2_2] = 0x0520, |
| 612 | [PMIF_MONITOR_RECORD_2_3] = 0x0524, |
| 613 | [PMIF_MONITOR_RECORD_2_4] = 0x0528, |
| 614 | [PMIF_MONITOR_RECORD_3_0] = 0x052C, |
| 615 | [PMIF_MONITOR_RECORD_3_1] = 0x0530, |
| 616 | [PMIF_MONITOR_RECORD_3_2] = 0x0534, |
| 617 | [PMIF_MONITOR_RECORD_3_3] = 0x0538, |
| 618 | [PMIF_MONITOR_RECORD_3_4] = 0x053C, |
| 619 | [PMIF_MONITOR_RECORD_4_0] = 0x0540, |
| 620 | [PMIF_MONITOR_RECORD_4_1] = 0x0544, |
| 621 | [PMIF_MONITOR_RECORD_4_2] = 0x0548, |
| 622 | [PMIF_MONITOR_RECORD_4_3] = 0x054C, |
| 623 | [PMIF_MONITOR_RECORD_4_4] = 0x0550, |
| 624 | [PMIF_MONITOR_RECORD_5_0] = 0x0554, |
| 625 | [PMIF_MONITOR_RECORD_5_1] = 0x0558, |
| 626 | [PMIF_MONITOR_RECORD_5_2] = 0x055C, |
| 627 | [PMIF_MONITOR_RECORD_5_3] = 0x0560, |
| 628 | [PMIF_MONITOR_RECORD_5_4] = 0x0564, |
| 629 | [PMIF_MONITOR_RECORD_6_0] = 0x0568, |
| 630 | [PMIF_MONITOR_RECORD_6_1] = 0x056C, |
| 631 | [PMIF_MONITOR_RECORD_6_2] = 0x0570, |
| 632 | [PMIF_MONITOR_RECORD_6_3] = 0x0574, |
| 633 | [PMIF_MONITOR_RECORD_6_4] = 0x0578, |
| 634 | [PMIF_MONITOR_RECORD_7_0] = 0x057C, |
| 635 | [PMIF_MONITOR_RECORD_7_1] = 0x0580, |
| 636 | [PMIF_MONITOR_RECORD_7_2] = 0x0584, |
| 637 | [PMIF_MONITOR_RECORD_7_3] = 0x0588, |
| 638 | [PMIF_MONITOR_RECORD_7_4] = 0x058C, |
| 639 | [PMIF_MONITOR_RECORD_8_0] = 0x0590, |
| 640 | [PMIF_MONITOR_RECORD_8_1] = 0x0594, |
| 641 | [PMIF_MONITOR_RECORD_8_2] = 0x0598, |
| 642 | [PMIF_MONITOR_RECORD_8_3] = 0x059C, |
| 643 | [PMIF_MONITOR_RECORD_8_4] = 0x05A0, |
| 644 | [PMIF_MONITOR_RECORD_9_0] = 0x05A4, |
| 645 | [PMIF_MONITOR_RECORD_9_1] = 0x05A8, |
| 646 | [PMIF_MONITOR_RECORD_9_2] = 0x05AC, |
| 647 | [PMIF_MONITOR_RECORD_9_3] = 0x05B0, |
| 648 | [PMIF_MONITOR_RECORD_9_4] = 0x05B4, |
| 649 | [PMIF_MONITOR_RECORD_10_0] = 0x05B8, |
| 650 | [PMIF_MONITOR_RECORD_10_1] = 0x05BC, |
| 651 | [PMIF_MONITOR_RECORD_10_2] = 0x05C0, |
| 652 | [PMIF_MONITOR_RECORD_10_3] = 0x05C4, |
| 653 | [PMIF_MONITOR_RECORD_10_4] = 0x05C8, |
| 654 | [PMIF_MONITOR_RECORD_11_0] = 0x05CC, |
| 655 | [PMIF_MONITOR_RECORD_11_1] = 0x05D0, |
| 656 | [PMIF_MONITOR_RECORD_11_2] = 0x05D4, |
| 657 | [PMIF_MONITOR_RECORD_11_3] = 0x05D8, |
| 658 | [PMIF_MONITOR_RECORD_11_4] = 0x05DC, |
| 659 | [PMIF_MONITOR_RECORD_12_0] = 0x05E0, |
| 660 | [PMIF_MONITOR_RECORD_12_1] = 0x05E4, |
| 661 | [PMIF_MONITOR_RECORD_12_2] = 0x05E8, |
| 662 | [PMIF_MONITOR_RECORD_12_3] = 0x05EC, |
| 663 | [PMIF_MONITOR_RECORD_12_4] = 0x05F0, |
| 664 | [PMIF_MONITOR_RECORD_13_0] = 0x05F4, |
| 665 | [PMIF_MONITOR_RECORD_13_1] = 0x05F8, |
| 666 | [PMIF_MONITOR_RECORD_13_2] = 0x05FC, |
| 667 | [PMIF_MONITOR_RECORD_13_3] = 0x0600, |
| 668 | [PMIF_MONITOR_RECORD_13_4] = 0x0604, |
| 669 | [PMIF_MONITOR_RECORD_14_0] = 0x0608, |
| 670 | [PMIF_MONITOR_RECORD_14_1] = 0x060C, |
| 671 | [PMIF_MONITOR_RECORD_14_2] = 0x0610, |
| 672 | [PMIF_MONITOR_RECORD_14_3] = 0x0614, |
| 673 | [PMIF_MONITOR_RECORD_14_4] = 0x0618, |
| 674 | [PMIF_MONITOR_RECORD_15_0] = 0x061C, |
| 675 | [PMIF_MONITOR_RECORD_15_1] = 0x0620, |
| 676 | [PMIF_MONITOR_RECORD_15_2] = 0x0624, |
| 677 | [PMIF_MONITOR_RECORD_15_3] = 0x0628, |
| 678 | [PMIF_MONITOR_RECORD_15_4] = 0x062C, |
| 679 | [PMIF_MONITOR_RECORD_16_0] = 0x0630, |
| 680 | [PMIF_MONITOR_RECORD_16_1] = 0x0634, |
| 681 | [PMIF_MONITOR_RECORD_16_2] = 0x0638, |
| 682 | [PMIF_MONITOR_RECORD_16_3] = 0x063C, |
| 683 | [PMIF_MONITOR_RECORD_16_4] = 0x0640, |
| 684 | [PMIF_MONITOR_RECORD_17_0] = 0x0644, |
| 685 | [PMIF_MONITOR_RECORD_17_1] = 0x0648, |
| 686 | [PMIF_MONITOR_RECORD_17_2] = 0x064C, |
| 687 | [PMIF_MONITOR_RECORD_17_3] = 0x0650, |
| 688 | [PMIF_MONITOR_RECORD_17_4] = 0x0654, |
| 689 | [PMIF_MONITOR_RECORD_18_0] = 0x0658, |
| 690 | [PMIF_MONITOR_RECORD_18_1] = 0x065C, |
| 691 | [PMIF_MONITOR_RECORD_18_2] = 0x0660, |
| 692 | [PMIF_MONITOR_RECORD_18_3] = 0x0664, |
| 693 | [PMIF_MONITOR_RECORD_18_4] = 0x0668, |
| 694 | [PMIF_MONITOR_RECORD_19_0] = 0x066C, |
| 695 | [PMIF_MONITOR_RECORD_19_1] = 0x0670, |
| 696 | [PMIF_MONITOR_RECORD_19_2] = 0x0674, |
| 697 | [PMIF_MONITOR_RECORD_19_3] = 0x0678, |
| 698 | [PMIF_MONITOR_RECORD_19_4] = 0x067C, |
| 699 | [PMIF_MONITOR_RECORD_20_0] = 0x0680, |
| 700 | [PMIF_MONITOR_RECORD_20_1] = 0x0684, |
| 701 | [PMIF_MONITOR_RECORD_20_2] = 0x0688, |
| 702 | [PMIF_MONITOR_RECORD_20_3] = 0x068C, |
| 703 | [PMIF_MONITOR_RECORD_20_4] = 0x0690, |
| 704 | [PMIF_MONITOR_RECORD_21_0] = 0x0694, |
| 705 | [PMIF_MONITOR_RECORD_21_1] = 0x0698, |
| 706 | [PMIF_MONITOR_RECORD_21_2] = 0x069C, |
| 707 | [PMIF_MONITOR_RECORD_21_3] = 0x06A0, |
| 708 | [PMIF_MONITOR_RECORD_21_4] = 0x06A4, |
| 709 | [PMIF_MONITOR_RECORD_22_0] = 0x06A8, |
| 710 | [PMIF_MONITOR_RECORD_22_1] = 0x06AC, |
| 711 | [PMIF_MONITOR_RECORD_22_2] = 0x06B0, |
| 712 | [PMIF_MONITOR_RECORD_22_3] = 0x06B4, |
| 713 | [PMIF_MONITOR_RECORD_22_4] = 0x06B8, |
| 714 | [PMIF_MONITOR_RECORD_23_0] = 0x06BC, |
| 715 | [PMIF_MONITOR_RECORD_23_1] = 0x06C0, |
| 716 | [PMIF_MONITOR_RECORD_23_2] = 0x06C4, |
| 717 | [PMIF_MONITOR_RECORD_23_3] = 0x06C8, |
| 718 | [PMIF_MONITOR_RECORD_23_4] = 0x06CC, |
| 719 | [PMIF_MONITOR_RECORD_24_0] = 0x06D0, |
| 720 | [PMIF_MONITOR_RECORD_24_1] = 0x06D4, |
| 721 | [PMIF_MONITOR_RECORD_24_2] = 0x06D8, |
| 722 | [PMIF_MONITOR_RECORD_24_3] = 0x06DC, |
| 723 | [PMIF_MONITOR_RECORD_24_4] = 0x06E0, |
| 724 | [PMIF_MONITOR_RECORD_25_0] = 0x06E4, |
| 725 | [PMIF_MONITOR_RECORD_25_1] = 0x06E8, |
| 726 | [PMIF_MONITOR_RECORD_25_2] = 0x06EC, |
| 727 | [PMIF_MONITOR_RECORD_25_3] = 0x06F0, |
| 728 | [PMIF_MONITOR_RECORD_25_4] = 0x06F4, |
| 729 | [PMIF_MONITOR_RECORD_26_0] = 0x06F8, |
| 730 | [PMIF_MONITOR_RECORD_26_1] = 0x06FC, |
| 731 | [PMIF_MONITOR_RECORD_26_2] = 0x0700, |
| 732 | [PMIF_MONITOR_RECORD_26_3] = 0x0704, |
| 733 | [PMIF_MONITOR_RECORD_26_4] = 0x0708, |
| 734 | [PMIF_MONITOR_RECORD_27_0] = 0x070C, |
| 735 | [PMIF_MONITOR_RECORD_27_1] = 0x0710, |
| 736 | [PMIF_MONITOR_RECORD_27_2] = 0x0714, |
| 737 | [PMIF_MONITOR_RECORD_27_3] = 0x0718, |
| 738 | [PMIF_MONITOR_RECORD_27_4] = 0x071C, |
| 739 | [PMIF_MONITOR_RECORD_28_0] = 0x0720, |
| 740 | [PMIF_MONITOR_RECORD_28_1] = 0x0724, |
| 741 | [PMIF_MONITOR_RECORD_28_2] = 0x0728, |
| 742 | [PMIF_MONITOR_RECORD_28_3] = 0x072C, |
| 743 | [PMIF_MONITOR_RECORD_28_4] = 0x0730, |
| 744 | [PMIF_MONITOR_RECORD_29_0] = 0x0734, |
| 745 | [PMIF_MONITOR_RECORD_29_1] = 0x0738, |
| 746 | [PMIF_MONITOR_RECORD_29_2] = 0x073C, |
| 747 | [PMIF_MONITOR_RECORD_29_3] = 0x0740, |
| 748 | [PMIF_MONITOR_RECORD_29_4] = 0x0744, |
| 749 | [PMIF_MONITOR_RECORD_30_0] = 0x0748, |
| 750 | [PMIF_MONITOR_RECORD_30_1] = 0x074C, |
| 751 | [PMIF_MONITOR_RECORD_30_2] = 0x0750, |
| 752 | [PMIF_MONITOR_RECORD_30_3] = 0x0754, |
| 753 | [PMIF_MONITOR_RECORD_30_4] = 0x0758, |
| 754 | [PMIF_MONITOR_RECORD_31_0] = 0x075C, |
| 755 | [PMIF_MONITOR_RECORD_31_1] = 0x0760, |
| 756 | [PMIF_MONITOR_RECORD_31_2] = 0x0764, |
| 757 | [PMIF_MONITOR_RECORD_31_3] = 0x0768, |
| 758 | [PMIF_MONITOR_RECORD_31_4] = 0x076C, |
| 759 | [PMIF_DEBUG_CTRL] = 0x0770, |
| 760 | [PMIF_RESERVED_0] = 0x0778, |
| 761 | [PMIF_SWINF_0_ACC] = 0x0C00, |
| 762 | [PMIF_SWINF_0_WDATA_31_0] = 0x0C04, |
| 763 | [PMIF_SWINF_0_WDATA_63_32] = 0x0C08, |
| 764 | [PMIF_SWINF_0_RDATA_31_0] = 0x0C14, |
| 765 | [PMIF_SWINF_0_RDATA_63_32] = 0x0C18, |
| 766 | [PMIF_SWINF_0_VLD_CLR] = 0x0C24, |
| 767 | [PMIF_SWINF_0_STA] = 0x0C28, |
| 768 | [PMIF_SWINF_1_ACC] = 0x0C40, |
| 769 | [PMIF_SWINF_1_WDATA_31_0] = 0x0C44, |
| 770 | [PMIF_SWINF_1_WDATA_63_32] = 0x0C48, |
| 771 | [PMIF_SWINF_1_RDATA_31_0] = 0x0C54, |
| 772 | [PMIF_SWINF_1_RDATA_63_32] = 0x0C58, |
| 773 | [PMIF_SWINF_1_VLD_CLR] = 0x0C64, |
| 774 | [PMIF_SWINF_1_STA] = 0x0C68, |
| 775 | [PMIF_SWINF_2_ACC] = 0x0C80, |
| 776 | [PMIF_SWINF_2_WDATA_31_0] = 0x0C84, |
| 777 | [PMIF_SWINF_2_WDATA_63_32] = 0x0C88, |
| 778 | [PMIF_SWINF_2_RDATA_31_0] = 0x0C94, |
| 779 | [PMIF_SWINF_2_RDATA_63_32] = 0x0C98, |
| 780 | [PMIF_SWINF_2_VLD_CLR] = 0x0CA4, |
| 781 | [PMIF_SWINF_2_STA] = 0x0CA8, |
| 782 | [PMIF_SWINF_3_ACC] = 0x0CC0, |
| 783 | [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4, |
| 784 | [PMIF_SWINF_3_WDATA_63_32] = 0x0CC8, |
| 785 | [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4, |
| 786 | [PMIF_SWINF_3_RDATA_63_32] = 0x0CD8, |
| 787 | [PMIF_SWINF_3_VLD_CLR] = 0x0CE4, |
| 788 | [PMIF_SWINF_3_STA] = 0x0CE8, |
| 789 | [PMIC_ACC_VIO_INFO_0] = 0x0F50, |
| 790 | [PMIC_ACC_VIO_INFO_1] = 0x0F54, |
| 791 | [PMIC_ACC_VIO_INFO_2] = 0x0F58, |
| 792 | [PMIC_ACC_VIO_INFO_3] = 0x0F5C, |
| 793 | [PMIC_ACC_VIO_INFO_4] = 0x0F60, |
| 794 | [PMIC_ACC_VIO_INFO_5] = 0x0F64, |
| 795 | [PMIC_ACC_SCP_VIO_INFO_0] = 0x0F68, |
| 796 | [PMIC_ACC_SCP_VIO_INFO_1] = 0x0F6C, |
| 797 | [PMIC_ACC_SCP_VIO_INFO_2] = 0x0F70, |
| 798 | [PMIC_ACC_SCP_VIO_INFO_3] = 0x0F74, |
| 799 | [PMIC_ACC_SCP_VIO_INFO_4] = 0x0F78, |
| 800 | [PMIC_ACC_SCP_VIO_INFO_5] = 0x0F7C, |
| 801 | [PMIF_ACC_VIO_INFO_0] = 0x0F80, |
| 802 | [PMIF_ACC_VIO_INFO_1] = 0x0F84, |
| 803 | [PMIF_ACC_VIO_INFO_2] = 0x0F88, |
| 804 | }; |
| 805 | |
| 806 | static const u32 mt6885_pmif_dbg_regs[] = { |
| 807 | [PMIF_INIT_DONE] = 0x0000, |
| 808 | [PMIF_INF_BUSY_STA] = 0x0018, |
| 809 | [PMIF_OTHER_BUSY_STA_0] = 0x001C, |
| 810 | [PMIF_OTHER_BUSY_STA_1] = 0x0020, |
| 811 | [PMIF_IRQ_EVENT_EN_0] = 0x0418, |
| 812 | [PMIF_IRQ_FLAG_0] = 0x0420, |
| 813 | [PMIF_IRQ_CLR_0] = 0x0424, |
| 814 | [PMIF_IRQ_EVENT_EN_1] = 0x0428, |
| 815 | [PMIF_IRQ_FLAG_1] = 0x0430, |
| 816 | [PMIF_IRQ_CLR_1] = 0x0434, |
| 817 | [PMIF_IRQ_EVENT_EN_2] = 0x0438, |
| 818 | [PMIF_IRQ_FLAG_2] = 0x0440, |
| 819 | [PMIF_IRQ_CLR_2] = 0x0444, |
| 820 | [PMIF_IRQ_EVENT_EN_3] = 0x0448, |
| 821 | [PMIF_IRQ_FLAG_3] = 0x0450, |
| 822 | [PMIF_IRQ_CLR_3] = 0x0454, |
| 823 | [PMIF_IRQ_EVENT_EN_4] = 0x0458, |
| 824 | [PMIF_IRQ_FLAG_4] = 0x0460, |
| 825 | [PMIF_IRQ_CLR_4] = 0x0464, |
| 826 | [PMIF_WDT_EVENT_EN_0] = 0x046C, |
| 827 | [PMIF_WDT_FLAG_0] = 0x0470, |
| 828 | [PMIF_WDT_EVENT_EN_1] = 0x0474, |
| 829 | [PMIF_WDT_FLAG_1] = 0x0478, |
| 830 | [PMIF_MONITOR_CTRL] = 0x047C, |
| 831 | [PMIF_MONITOR_TARGET_CHAN_0] = 0x0480, |
| 832 | [PMIF_MONITOR_TARGET_CHAN_1] = 0x0484, |
| 833 | [PMIF_MONITOR_TARGET_CHAN_2] = 0x0488, |
| 834 | [PMIF_MONITOR_TARGET_CHAN_3] = 0x048C, |
| 835 | [PMIF_MONITOR_TARGET_CHAN_4] = 0x0490, |
| 836 | [PMIF_MONITOR_TARGET_CHAN_5] = 0x0494, |
| 837 | [PMIF_MONITOR_TARGET_CHAN_6] = 0x0498, |
| 838 | [PMIF_MONITOR_TARGET_CHAN_7] = 0x049C, |
| 839 | [PMIF_MONITOR_TARGET_WRITE] = 0x04A0, |
| 840 | [PMIF_MONITOR_TARGET_ADDR_0] = 0x04A4, |
| 841 | [PMIF_MONITOR_TARGET_ADDR_1] = 0x04A8, |
| 842 | [PMIF_MONITOR_TARGET_ADDR_2] = 0x04AC, |
| 843 | [PMIF_MONITOR_TARGET_ADDR_3] = 0x04B0, |
| 844 | [PMIF_MONITOR_TARGET_ADDR_4] = 0x04B4, |
| 845 | [PMIF_MONITOR_TARGET_ADDR_5] = 0x04B8, |
| 846 | [PMIF_MONITOR_TARGET_ADDR_6] = 0x04BC, |
| 847 | [PMIF_MONITOR_TARGET_ADDR_7] = 0x04C0, |
| 848 | [PMIF_MONITOR_TARGET_WDATA_0] = 0x04C4, |
| 849 | [PMIF_MONITOR_TARGET_WDATA_1] = 0x04C8, |
| 850 | [PMIF_MONITOR_TARGET_WDATA_2] = 0x04CC, |
| 851 | [PMIF_MONITOR_TARGET_WDATA_3] = 0x04D0, |
| 852 | [PMIF_MONITOR_TARGET_WDATA_4] = 0x04D4, |
| 853 | [PMIF_MONITOR_TARGET_WDATA_5] = 0x04D8, |
| 854 | [PMIF_MONITOR_TARGET_WDATA_6] = 0x04DC, |
| 855 | [PMIF_MONITOR_TARGET_WDATA_7] = 0x04E0, |
| 856 | [PMIF_MONITOR_STA] = 0x04E4, |
| 857 | [PMIF_MONITOR_RECORD_0_0] = 0x04E8, |
| 858 | [PMIF_MONITOR_RECORD_0_1] = 0x04EC, |
| 859 | [PMIF_MONITOR_RECORD_0_2] = 0x04F0, |
| 860 | [PMIF_MONITOR_RECORD_0_3] = 0x04F4, |
| 861 | [PMIF_MONITOR_RECORD_0_4] = 0x04F8, |
| 862 | [PMIF_MONITOR_RECORD_1_0] = 0x04FC, |
| 863 | [PMIF_MONITOR_RECORD_1_1] = 0x0500, |
| 864 | [PMIF_MONITOR_RECORD_1_2] = 0x0504, |
| 865 | [PMIF_MONITOR_RECORD_1_3] = 0x0508, |
| 866 | [PMIF_MONITOR_RECORD_1_4] = 0x050C, |
| 867 | [PMIF_MONITOR_RECORD_2_0] = 0x0510, |
| 868 | [PMIF_MONITOR_RECORD_2_1] = 0x0514, |
| 869 | [PMIF_MONITOR_RECORD_2_2] = 0x0518, |
| 870 | [PMIF_MONITOR_RECORD_2_3] = 0x051C, |
| 871 | [PMIF_MONITOR_RECORD_2_4] = 0x0520, |
| 872 | [PMIF_MONITOR_RECORD_3_0] = 0x0524, |
| 873 | [PMIF_MONITOR_RECORD_3_1] = 0x0528, |
| 874 | [PMIF_MONITOR_RECORD_3_2] = 0x052C, |
| 875 | [PMIF_MONITOR_RECORD_3_3] = 0x0530, |
| 876 | [PMIF_MONITOR_RECORD_3_4] = 0x0534, |
| 877 | [PMIF_MONITOR_RECORD_4_0] = 0x0538, |
| 878 | [PMIF_MONITOR_RECORD_4_1] = 0x053C, |
| 879 | [PMIF_MONITOR_RECORD_4_2] = 0x0540, |
| 880 | [PMIF_MONITOR_RECORD_4_3] = 0x0544, |
| 881 | [PMIF_MONITOR_RECORD_4_4] = 0x0548, |
| 882 | [PMIF_MONITOR_RECORD_5_0] = 0x054C, |
| 883 | [PMIF_MONITOR_RECORD_5_1] = 0x0550, |
| 884 | [PMIF_MONITOR_RECORD_5_2] = 0x0554, |
| 885 | [PMIF_MONITOR_RECORD_5_3] = 0x0558, |
| 886 | [PMIF_MONITOR_RECORD_5_4] = 0x055C, |
| 887 | [PMIF_MONITOR_RECORD_6_0] = 0x0560, |
| 888 | [PMIF_MONITOR_RECORD_6_1] = 0x0564, |
| 889 | [PMIF_MONITOR_RECORD_6_2] = 0x0568, |
| 890 | [PMIF_MONITOR_RECORD_6_3] = 0x056C, |
| 891 | [PMIF_MONITOR_RECORD_6_4] = 0x0570, |
| 892 | [PMIF_MONITOR_RECORD_7_0] = 0x0574, |
| 893 | [PMIF_MONITOR_RECORD_7_1] = 0x0578, |
| 894 | [PMIF_MONITOR_RECORD_7_2] = 0x057C, |
| 895 | [PMIF_MONITOR_RECORD_7_3] = 0x0580, |
| 896 | [PMIF_MONITOR_RECORD_7_4] = 0x0584, |
| 897 | [PMIF_MONITOR_RECORD_8_0] = 0x0588, |
| 898 | [PMIF_MONITOR_RECORD_8_1] = 0x058C, |
| 899 | [PMIF_MONITOR_RECORD_8_2] = 0x0590, |
| 900 | [PMIF_MONITOR_RECORD_8_3] = 0x0594, |
| 901 | [PMIF_MONITOR_RECORD_8_4] = 0x0598, |
| 902 | [PMIF_MONITOR_RECORD_9_0] = 0x059C, |
| 903 | [PMIF_MONITOR_RECORD_9_1] = 0x05A0, |
| 904 | [PMIF_MONITOR_RECORD_9_2] = 0x05A4, |
| 905 | [PMIF_MONITOR_RECORD_9_3] = 0x05A8, |
| 906 | [PMIF_MONITOR_RECORD_9_4] = 0x05AC, |
| 907 | [PMIF_MONITOR_RECORD_10_0] = 0x05B0, |
| 908 | [PMIF_MONITOR_RECORD_10_1] = 0x05B4, |
| 909 | [PMIF_MONITOR_RECORD_10_2] = 0x05B8, |
| 910 | [PMIF_MONITOR_RECORD_10_3] = 0x05BC, |
| 911 | [PMIF_MONITOR_RECORD_10_4] = 0x05C0, |
| 912 | [PMIF_MONITOR_RECORD_11_0] = 0x05C4, |
| 913 | [PMIF_MONITOR_RECORD_11_1] = 0x05C8, |
| 914 | [PMIF_MONITOR_RECORD_11_2] = 0x05CC, |
| 915 | [PMIF_MONITOR_RECORD_11_3] = 0x05D0, |
| 916 | [PMIF_MONITOR_RECORD_11_4] = 0x05D4, |
| 917 | [PMIF_MONITOR_RECORD_12_0] = 0x05D8, |
| 918 | [PMIF_MONITOR_RECORD_12_1] = 0x05DC, |
| 919 | [PMIF_MONITOR_RECORD_12_2] = 0x05E0, |
| 920 | [PMIF_MONITOR_RECORD_12_3] = 0x05E4, |
| 921 | [PMIF_MONITOR_RECORD_12_4] = 0x05E8, |
| 922 | [PMIF_MONITOR_RECORD_13_0] = 0x05EC, |
| 923 | [PMIF_MONITOR_RECORD_13_1] = 0x05F0, |
| 924 | [PMIF_MONITOR_RECORD_13_2] = 0x05F4, |
| 925 | [PMIF_MONITOR_RECORD_13_3] = 0x05F8, |
| 926 | [PMIF_MONITOR_RECORD_13_4] = 0x05FC, |
| 927 | [PMIF_MONITOR_RECORD_14_0] = 0x0600, |
| 928 | [PMIF_MONITOR_RECORD_14_1] = 0x0604, |
| 929 | [PMIF_MONITOR_RECORD_14_2] = 0x0608, |
| 930 | [PMIF_MONITOR_RECORD_14_3] = 0x060C, |
| 931 | [PMIF_MONITOR_RECORD_14_4] = 0x0610, |
| 932 | [PMIF_MONITOR_RECORD_15_0] = 0x0614, |
| 933 | [PMIF_MONITOR_RECORD_15_1] = 0x0618, |
| 934 | [PMIF_MONITOR_RECORD_15_2] = 0x061C, |
| 935 | [PMIF_MONITOR_RECORD_15_3] = 0x0620, |
| 936 | [PMIF_MONITOR_RECORD_15_4] = 0x0624, |
| 937 | [PMIF_MONITOR_RECORD_16_0] = 0x0628, |
| 938 | [PMIF_MONITOR_RECORD_16_1] = 0x062C, |
| 939 | [PMIF_MONITOR_RECORD_16_2] = 0x0630, |
| 940 | [PMIF_MONITOR_RECORD_16_3] = 0x0634, |
| 941 | [PMIF_MONITOR_RECORD_16_4] = 0x0638, |
| 942 | [PMIF_MONITOR_RECORD_17_0] = 0x063C, |
| 943 | [PMIF_MONITOR_RECORD_17_1] = 0x0640, |
| 944 | [PMIF_MONITOR_RECORD_17_2] = 0x0644, |
| 945 | [PMIF_MONITOR_RECORD_17_3] = 0x0648, |
| 946 | [PMIF_MONITOR_RECORD_17_4] = 0x064C, |
| 947 | [PMIF_MONITOR_RECORD_18_0] = 0x0650, |
| 948 | [PMIF_MONITOR_RECORD_18_1] = 0x0654, |
| 949 | [PMIF_MONITOR_RECORD_18_2] = 0x0658, |
| 950 | [PMIF_MONITOR_RECORD_18_3] = 0x065C, |
| 951 | [PMIF_MONITOR_RECORD_18_4] = 0x0660, |
| 952 | [PMIF_MONITOR_RECORD_19_0] = 0x0664, |
| 953 | [PMIF_MONITOR_RECORD_19_1] = 0x0668, |
| 954 | [PMIF_MONITOR_RECORD_19_2] = 0x066C, |
| 955 | [PMIF_MONITOR_RECORD_19_3] = 0x0670, |
| 956 | [PMIF_MONITOR_RECORD_19_4] = 0x0674, |
| 957 | [PMIF_MONITOR_RECORD_20_0] = 0x0678, |
| 958 | [PMIF_MONITOR_RECORD_20_1] = 0x067C, |
| 959 | [PMIF_MONITOR_RECORD_20_2] = 0x0680, |
| 960 | [PMIF_MONITOR_RECORD_20_3] = 0x0684, |
| 961 | [PMIF_MONITOR_RECORD_20_4] = 0x0688, |
| 962 | [PMIF_MONITOR_RECORD_21_0] = 0x068C, |
| 963 | [PMIF_MONITOR_RECORD_21_1] = 0x0690, |
| 964 | [PMIF_MONITOR_RECORD_21_2] = 0x0694, |
| 965 | [PMIF_MONITOR_RECORD_21_3] = 0x0698, |
| 966 | [PMIF_MONITOR_RECORD_21_4] = 0x069C, |
| 967 | [PMIF_MONITOR_RECORD_22_0] = 0x06A0, |
| 968 | [PMIF_MONITOR_RECORD_22_1] = 0x06A4, |
| 969 | [PMIF_MONITOR_RECORD_22_2] = 0x06A8, |
| 970 | [PMIF_MONITOR_RECORD_22_3] = 0x06AC, |
| 971 | [PMIF_MONITOR_RECORD_22_4] = 0x06B0, |
| 972 | [PMIF_MONITOR_RECORD_23_0] = 0x06B4, |
| 973 | [PMIF_MONITOR_RECORD_23_1] = 0x06B8, |
| 974 | [PMIF_MONITOR_RECORD_23_2] = 0x06BC, |
| 975 | [PMIF_MONITOR_RECORD_23_3] = 0x06C0, |
| 976 | [PMIF_MONITOR_RECORD_23_4] = 0x06C4, |
| 977 | [PMIF_MONITOR_RECORD_24_0] = 0x06C8, |
| 978 | [PMIF_MONITOR_RECORD_24_1] = 0x06CC, |
| 979 | [PMIF_MONITOR_RECORD_24_2] = 0x06D0, |
| 980 | [PMIF_MONITOR_RECORD_24_3] = 0x06D4, |
| 981 | [PMIF_MONITOR_RECORD_24_4] = 0x06D8, |
| 982 | [PMIF_MONITOR_RECORD_25_0] = 0x06DC, |
| 983 | [PMIF_MONITOR_RECORD_25_1] = 0x06E0, |
| 984 | [PMIF_MONITOR_RECORD_25_2] = 0x06E4, |
| 985 | [PMIF_MONITOR_RECORD_25_3] = 0x06E8, |
| 986 | [PMIF_MONITOR_RECORD_25_4] = 0x06EC, |
| 987 | [PMIF_MONITOR_RECORD_26_0] = 0x06F0, |
| 988 | [PMIF_MONITOR_RECORD_26_1] = 0x06F4, |
| 989 | [PMIF_MONITOR_RECORD_26_2] = 0x06F8, |
| 990 | [PMIF_MONITOR_RECORD_26_3] = 0x06FC, |
| 991 | [PMIF_MONITOR_RECORD_26_4] = 0x0700, |
| 992 | [PMIF_MONITOR_RECORD_27_0] = 0x0704, |
| 993 | [PMIF_MONITOR_RECORD_27_1] = 0x0708, |
| 994 | [PMIF_MONITOR_RECORD_27_2] = 0x070C, |
| 995 | [PMIF_MONITOR_RECORD_27_3] = 0x0710, |
| 996 | [PMIF_MONITOR_RECORD_27_4] = 0x0714, |
| 997 | [PMIF_MONITOR_RECORD_28_0] = 0x0718, |
| 998 | [PMIF_MONITOR_RECORD_28_1] = 0x071C, |
| 999 | [PMIF_MONITOR_RECORD_28_2] = 0x0720, |
| 1000 | [PMIF_MONITOR_RECORD_28_3] = 0x0724, |
| 1001 | [PMIF_MONITOR_RECORD_28_4] = 0x0728, |
| 1002 | [PMIF_MONITOR_RECORD_29_0] = 0x072C, |
| 1003 | [PMIF_MONITOR_RECORD_29_1] = 0x0730, |
| 1004 | [PMIF_MONITOR_RECORD_29_2] = 0x0734, |
| 1005 | [PMIF_MONITOR_RECORD_29_3] = 0x0738, |
| 1006 | [PMIF_MONITOR_RECORD_29_4] = 0x073C, |
| 1007 | [PMIF_MONITOR_RECORD_30_0] = 0x0740, |
| 1008 | [PMIF_MONITOR_RECORD_30_1] = 0x0744, |
| 1009 | [PMIF_MONITOR_RECORD_30_2] = 0x0748, |
| 1010 | [PMIF_MONITOR_RECORD_30_3] = 0x074C, |
| 1011 | [PMIF_MONITOR_RECORD_30_4] = 0x0750, |
| 1012 | [PMIF_MONITOR_RECORD_31_0] = 0x0754, |
| 1013 | [PMIF_MONITOR_RECORD_31_1] = 0x0758, |
| 1014 | [PMIF_MONITOR_RECORD_31_2] = 0x075C, |
| 1015 | [PMIF_MONITOR_RECORD_31_3] = 0x0760, |
| 1016 | [PMIF_MONITOR_RECORD_31_4] = 0x0764, |
| 1017 | [PMIF_DEBUG_CTRL] = 0x0768, |
| 1018 | [PMIF_RESERVED_0] = 0x0770, |
| 1019 | [PMIF_SWINF_0_ACC] = 0x0C00, |
| 1020 | [PMIF_SWINF_0_WDATA_31_0] = 0x0C04, |
| 1021 | [PMIF_SWINF_0_WDATA_63_32] = 0x0C08, |
| 1022 | [PMIF_SWINF_0_RDATA_31_0] = 0x0C14, |
| 1023 | [PMIF_SWINF_0_RDATA_63_32] = 0x0C18, |
| 1024 | [PMIF_SWINF_0_VLD_CLR] = 0x0C24, |
| 1025 | [PMIF_SWINF_0_STA] = 0x0C28, |
| 1026 | [PMIF_SWINF_1_ACC] = 0x0C40, |
| 1027 | [PMIF_SWINF_1_WDATA_31_0] = 0x0C44, |
| 1028 | [PMIF_SWINF_1_WDATA_63_32] = 0x0C48, |
| 1029 | [PMIF_SWINF_1_RDATA_31_0] = 0x0C54, |
| 1030 | [PMIF_SWINF_1_RDATA_63_32] = 0x0C58, |
| 1031 | [PMIF_SWINF_1_VLD_CLR] = 0x0C64, |
| 1032 | [PMIF_SWINF_1_STA] = 0x0C68, |
| 1033 | [PMIF_SWINF_2_ACC] = 0x0C80, |
| 1034 | [PMIF_SWINF_2_WDATA_31_0] = 0x0C84, |
| 1035 | [PMIF_SWINF_2_WDATA_63_32] = 0x0C88, |
| 1036 | [PMIF_SWINF_2_RDATA_31_0] = 0x0C94, |
| 1037 | [PMIF_SWINF_2_RDATA_63_32] = 0x0C98, |
| 1038 | [PMIF_SWINF_2_VLD_CLR] = 0x0CA4, |
| 1039 | [PMIF_SWINF_2_STA] = 0x0CA8, |
| 1040 | [PMIF_SWINF_3_ACC] = 0x0CC0, |
| 1041 | [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4, |
| 1042 | [PMIF_SWINF_3_WDATA_63_32] = 0x0CC8, |
| 1043 | [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4, |
| 1044 | [PMIF_SWINF_3_RDATA_63_32] = 0x0CD8, |
| 1045 | [PMIF_SWINF_3_VLD_CLR] = 0x0CE4, |
| 1046 | [PMIF_SWINF_3_STA] = 0x0CE8, |
| 1047 | [PMIC_ACC_VIO_INFO_0] = 0x0F50, |
| 1048 | [PMIC_ACC_VIO_INFO_1] = 0x0F54, |
| 1049 | [PMIC_ACC_VIO_INFO_2] = 0x0F58, |
| 1050 | [PMIC_ACC_VIO_INFO_3] = 0x0F5C, |
| 1051 | [PMIC_ACC_VIO_INFO_4] = 0x0F60, |
| 1052 | [PMIC_ACC_VIO_INFO_5] = 0x0F64, |
| 1053 | [PMIC_ACC_SCP_VIO_INFO_0] = 0x0F68, |
| 1054 | [PMIC_ACC_SCP_VIO_INFO_1] = 0x0F6C, |
| 1055 | [PMIC_ACC_SCP_VIO_INFO_2] = 0x0F70, |
| 1056 | [PMIC_ACC_SCP_VIO_INFO_3] = 0x0F74, |
| 1057 | [PMIC_ACC_SCP_VIO_INFO_4] = 0x0F78, |
| 1058 | [PMIC_ACC_SCP_VIO_INFO_5] = 0x0F7C, |
| 1059 | [PMIF_ACC_VIO_INFO_0] = 0x0F80, |
| 1060 | [PMIF_ACC_VIO_INFO_1] = 0x0F84, |
| 1061 | [PMIF_ACC_VIO_INFO_2] = 0x0F88, |
| 1062 | }; |
| 1063 | |
| 1064 | static char d_log_buf[1280]; |
| 1065 | static struct spmi_controller *dbg_ctrl; |
| 1066 | static char *wp; |
| 1067 | |
| 1068 | /* spmi & pmif debug mechanism */ |
| 1069 | void spmi_dump_wdt_reg(void) |
| 1070 | { |
| 1071 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1072 | unsigned int offset, tmp_dat; |
| 1073 | unsigned int start, end, log_size = 0; |
| 1074 | |
| 1075 | start = arb->dbgregs[PMIF_WDT_EVENT_EN_0]; |
| 1076 | end = arb->dbgregs[PMIF_WDT_FLAG_1]; |
| 1077 | |
| 1078 | for (offset = start; offset <= end; offset += 4) { |
| 1079 | tmp_dat = readl(arb->base + offset); |
| 1080 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1081 | offset, tmp_dat); |
| 1082 | } |
| 1083 | log_size += sprintf(wp + log_size, "\n"); |
| 1084 | pr_info("[PMIF] %s", wp); |
| 1085 | } |
| 1086 | |
| 1087 | void spmi_dump_pmif_acc_vio_reg(void) |
| 1088 | { |
| 1089 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1090 | unsigned int offset, tmp_dat; |
| 1091 | unsigned int start, end, log_size = 0; |
| 1092 | |
| 1093 | start = arb->dbgregs[PMIF_ACC_VIO_INFO_0]; |
| 1094 | if (arb->dbgver == 2) |
| 1095 | end = arb->dbgregs[PMIC_ALL_ACC_VIO_INFO_1]; |
| 1096 | else |
| 1097 | end = arb->dbgregs[PMIF_ACC_VIO_INFO_2]; |
| 1098 | |
| 1099 | for (offset = start; offset <= end; offset += 4) { |
| 1100 | tmp_dat = readl(arb->base + offset); |
| 1101 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1102 | offset, tmp_dat); |
| 1103 | } |
| 1104 | log_size += sprintf(wp + log_size, "\n"); |
| 1105 | pr_info("[PMIF] %s", wp); |
| 1106 | } |
| 1107 | |
| 1108 | void spmi_dump_pmic_acc_vio_reg(void) |
| 1109 | { |
| 1110 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1111 | unsigned int offset, tmp_dat; |
| 1112 | unsigned int start, end, log_size = 0; |
| 1113 | |
| 1114 | start = arb->dbgregs[PMIC_ACC_VIO_INFO_0]; |
| 1115 | end = arb->dbgregs[PMIC_ACC_VIO_INFO_5]; |
| 1116 | |
| 1117 | for (offset = start; offset <= end; offset += 4) { |
| 1118 | tmp_dat = readl(arb->base + offset); |
| 1119 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1120 | offset, tmp_dat); |
| 1121 | } |
| 1122 | log_size += sprintf(wp + log_size, "\n"); |
| 1123 | pr_info("[PMIF] %s", wp); |
| 1124 | } |
| 1125 | |
| 1126 | static char *get_pmif_busy_reg_dump(void) |
| 1127 | { |
| 1128 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1129 | unsigned int offset, tmp_dat; |
| 1130 | unsigned int start, end, log_size = 0; |
| 1131 | |
| 1132 | start = arb->dbgregs[PMIF_INF_BUSY_STA]; |
| 1133 | end = arb->dbgregs[PMIF_OTHER_BUSY_STA_1]; |
| 1134 | |
| 1135 | for (offset = start; offset <= end; offset += 4) { |
| 1136 | tmp_dat = readl(arb->base + offset); |
| 1137 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1138 | offset, tmp_dat); |
| 1139 | } |
| 1140 | log_size += sprintf(wp + log_size, "\n"); |
| 1141 | return wp; |
| 1142 | } |
| 1143 | |
| 1144 | static char *get_pmif_swinf_reg_dump(void) |
| 1145 | { |
| 1146 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1147 | unsigned int swinf = 0, step, offset, tmp_dat, log_size = 0; |
| 1148 | unsigned int cmd, is_write, slvid, bytecnt, addr; |
| 1149 | unsigned int wd_31_0, rd_31_0; |
| 1150 | unsigned int err, sbusy, done, qfillcnt, qfreecnt, qempty, qfull; |
| 1151 | unsigned int req, fsm, en; |
| 1152 | |
| 1153 | step = arb->dbgregs[PMIF_SWINF_1_ACC] - arb->dbgregs[PMIF_SWINF_0_ACC]; |
| 1154 | for (swinf = 0; swinf < 4; swinf++) { |
| 1155 | offset = arb->dbgregs[PMIF_SWINF_0_ACC] + swinf * step; |
| 1156 | tmp_dat = readl(arb->base + offset); |
| 1157 | cmd = (tmp_dat & (0x3 << 30)) >> 30; |
| 1158 | is_write = (tmp_dat & (0x1 << 29)) >> 29; |
| 1159 | slvid = (tmp_dat & (0xf << 24)) >> 24; |
| 1160 | bytecnt = (tmp_dat & (0xf << 16)) >> 16; |
| 1161 | addr = (tmp_dat & (0xffff << 0)) >> 0; |
| 1162 | |
| 1163 | offset = arb->dbgregs[PMIF_SWINF_0_WDATA_31_0] + swinf * step; |
| 1164 | wd_31_0 = readl(arb->base + offset); |
| 1165 | |
| 1166 | offset = arb->dbgregs[PMIF_SWINF_0_RDATA_31_0] + swinf * step; |
| 1167 | rd_31_0 = readl(arb->base + offset); |
| 1168 | |
| 1169 | offset = arb->dbgregs[PMIF_SWINF_0_STA] + swinf * step; |
| 1170 | tmp_dat = readl(arb->base + offset); |
| 1171 | err = (tmp_dat & (0x1 << 18)) >> 18; |
| 1172 | sbusy = (tmp_dat & (0x1 << 17)) >> 17; |
| 1173 | done = (tmp_dat & (0x1 << 15)) >> 15; |
| 1174 | qfillcnt = (tmp_dat & (0xf << 11)) >> 11; |
| 1175 | qfreecnt = (tmp_dat & (0xf << 7)) >> 7; |
| 1176 | qempty = (tmp_dat & (0x1 << 6)) >> 6; |
| 1177 | qfull = (tmp_dat & (0x1 << 5)) >> 5; |
| 1178 | req = (tmp_dat & (0x1 << 4)) >> 4; |
| 1179 | fsm = (tmp_dat & (0x7 << 1)) >> 1; |
| 1180 | en = (tmp_dat & (0x1 << 0)) >> 0; |
| 1181 | |
| 1182 | log_size += sprintf( |
| 1183 | wp + log_size, |
| 1184 | "[swinf:%d, cmd:0x%x, is_write:%d, slvid:%d ", |
| 1185 | swinf, cmd, is_write, slvid); |
| 1186 | if (is_write) { |
| 1187 | log_size += sprintf( |
| 1188 | wp + log_size, |
| 1189 | "bytecnt:%d (write addr 0x%x=0x%x)]\n", |
| 1190 | bytecnt, addr, wd_31_0); |
| 1191 | } else { |
| 1192 | log_size += sprintf( |
| 1193 | wp + log_size, |
| 1194 | "bytecnt:%d (read addr 0x%x=0x%x)]\n", |
| 1195 | bytecnt, addr, rd_31_0); |
| 1196 | } |
| 1197 | log_size += sprintf( |
| 1198 | wp + log_size, |
| 1199 | "[err:%d, sbusy:%d, done:%d, qfillcnt:%d ", |
| 1200 | err, sbusy, done, qfillcnt); |
| 1201 | log_size += sprintf( |
| 1202 | wp + log_size, |
| 1203 | "qfreecnt:%d, qempty:%d, qfull:%d, req:%d ", |
| 1204 | qfreecnt, qempty, qfull, req); |
| 1205 | log_size += sprintf(wp + log_size, "fsm:%d, en:%d]\n", fsm, en); |
| 1206 | } |
| 1207 | log_size += sprintf(wp + log_size, "\n"); |
| 1208 | return wp; |
| 1209 | } |
| 1210 | |
| 1211 | static char *get_spmimst_all_reg_dump(void) |
| 1212 | { |
| 1213 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1214 | unsigned int tmp_dat, log_size = 0; |
| 1215 | int i; |
| 1216 | |
| 1217 | log_size += sprintf(wp, "\n[SPMI] "); |
| 1218 | for (i = 0; i < SPMI_NUM_REGS; i++) { |
| 1219 | tmp_dat = readl(arb->spmimst_base + arb->spmimst_regs[i]); |
| 1220 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1221 | arb->spmimst_regs[i], tmp_dat); |
| 1222 | if ((i + 1) % 8 == 0) |
| 1223 | log_size += sprintf(wp + log_size, "\n[SPMI] "); |
| 1224 | } |
| 1225 | log_size += sprintf(wp + log_size, "\n"); |
| 1226 | return wp; |
| 1227 | } |
| 1228 | |
| 1229 | void spmi_dump_pmif_busy_reg(void) |
| 1230 | { |
| 1231 | pr_info("[PMIF] %s", get_pmif_busy_reg_dump()); |
| 1232 | } |
| 1233 | |
| 1234 | static void spmi_dump_pmif_busy_reg_d(struct seq_file *m) |
| 1235 | { |
| 1236 | seq_puts(m, get_pmif_busy_reg_dump()); |
| 1237 | } |
| 1238 | |
| 1239 | void spmi_dump_pmif_swinf_reg(void) |
| 1240 | { |
| 1241 | pr_info("[PMIF]\n%s", get_pmif_swinf_reg_dump()); |
| 1242 | } |
| 1243 | |
| 1244 | static void spmi_dump_pmif_swinf_reg_d(struct seq_file *m) |
| 1245 | { |
| 1246 | seq_puts(m, get_pmif_swinf_reg_dump()); |
| 1247 | } |
| 1248 | |
| 1249 | void spmi_dump_pmif_all_reg(void) |
| 1250 | { |
| 1251 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1252 | unsigned int offset, tmp_dat, log_size = 0; |
| 1253 | unsigned int start, end; |
| 1254 | int i = 0; |
| 1255 | |
| 1256 | start = arb->dbgregs[PMIF_INIT_DONE]; |
| 1257 | end = arb->dbgregs[PMIF_RESERVED_0]; |
| 1258 | |
| 1259 | for (offset = start; offset <= end; offset += 4) { |
| 1260 | tmp_dat = readl(arb->base + offset); |
| 1261 | log_size += sprintf(wp + log_size, "(0x%x)=0x%x ", |
| 1262 | offset, tmp_dat); |
| 1263 | i++; |
| 1264 | if (i % 64 == 0) { |
| 1265 | pr_info("\n[PMIF] %s", wp); |
| 1266 | log_size = 0; |
| 1267 | } else if (i % 8 == 0) |
| 1268 | log_size += sprintf(wp + log_size, "\n[PMIF] "); |
| 1269 | } |
| 1270 | pr_info("\n[PMIF] %s", wp); |
| 1271 | } |
| 1272 | |
| 1273 | static void spmi_dump_pmif_all_reg_d(struct seq_file *m) |
| 1274 | { |
| 1275 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1276 | unsigned int offset, tmp_dat; |
| 1277 | unsigned int start, end; |
| 1278 | |
| 1279 | start = arb->dbgregs[PMIF_INIT_DONE]; |
| 1280 | end = arb->dbgregs[PMIF_RESERVED_0]; |
| 1281 | |
| 1282 | for (offset = start; offset <= end; offset += 4) { |
| 1283 | tmp_dat = readl(arb->base + offset); |
| 1284 | seq_printf(m, "(0x%x)=0x%x ", offset, tmp_dat); |
| 1285 | } |
| 1286 | seq_puts(m, "\n"); |
| 1287 | } |
| 1288 | |
| 1289 | void spmi_dump_pmif_record_reg(void) |
| 1290 | { |
| 1291 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1292 | unsigned int i = 0, step, offset, tmp_dat; |
| 1293 | unsigned int chan, cmd, is_write, slvid, bytecnt, addr; |
| 1294 | unsigned int wd_31_0, log_size = 0; |
| 1295 | char wd_str[15] = ""; |
| 1296 | |
| 1297 | /* stop logging */ |
| 1298 | writel(0, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]); |
| 1299 | step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] - |
| 1300 | arb->dbgregs[PMIF_MONITOR_RECORD_0_0]; |
| 1301 | |
| 1302 | for (i = 0; i < 32; i++) { |
| 1303 | offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + i * step; |
| 1304 | tmp_dat = readl(arb->base + offset); |
| 1305 | chan = (tmp_dat & (0x1f << 27)) >> 27; |
| 1306 | cmd = (tmp_dat & (0x3 << 25)) >> 25; |
| 1307 | is_write = (tmp_dat & (0x1 << 24)) >> 24; |
| 1308 | slvid = (tmp_dat & (0xf << 20)) >> 20; |
| 1309 | bytecnt = (tmp_dat & (0xf << 16)) >> 16; |
| 1310 | addr = (tmp_dat & (0xffff << 0)) >> 0; |
| 1311 | |
| 1312 | offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + i * step; |
| 1313 | wd_31_0 = readl(arb->base + offset); |
| 1314 | if (is_write) |
| 1315 | snprintf(wd_str, 12, "=0x%x", wd_31_0); |
| 1316 | else |
| 1317 | wd_str[0] = '\0'; |
| 1318 | |
| 1319 | log_size += sprintf(wp + log_size, |
| 1320 | "[PMIF] (%d)[chan:%d, cmd:0x%x, rw:0x%x, slvid:%d, ", |
| 1321 | i, chan, cmd, is_write, slvid); |
| 1322 | log_size += sprintf(wp + log_size, |
| 1323 | "bytecnt:%d, (addr 0x%x%s)]\n", |
| 1324 | bytecnt, addr, wd_str); |
| 1325 | if ((i + 1) % 8 == 0) { |
| 1326 | pr_info("\n%s", wp); |
| 1327 | log_size = 0; |
| 1328 | } |
| 1329 | } |
| 1330 | /* logging mode no need to clear record, re-enable logging */ |
| 1331 | writel(0x5, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]); |
| 1332 | } |
| 1333 | |
| 1334 | static void spmi_dump_pmif_record_reg_d(struct seq_file *m) |
| 1335 | { |
| 1336 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1337 | unsigned int i = 0, step, offset, tmp_dat; |
| 1338 | unsigned int chan, cmd, is_write, slvid, bytecnt, addr; |
| 1339 | unsigned int wd_31_0; |
| 1340 | char wd_str[15] = ""; |
| 1341 | |
| 1342 | /* stop logging */ |
| 1343 | writel(0, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]); |
| 1344 | step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] - |
| 1345 | arb->dbgregs[PMIF_MONITOR_RECORD_0_0]; |
| 1346 | step = arb->dbgregs[PMIF_MONITOR_RECORD_1_0] - |
| 1347 | arb->dbgregs[PMIF_MONITOR_RECORD_0_0]; |
| 1348 | |
| 1349 | for (i = 0; i < 32; i++) { |
| 1350 | offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_0] + i * step; |
| 1351 | tmp_dat = readl(arb->base + offset); |
| 1352 | chan = (tmp_dat & (0x1f << 27)) >> 27; |
| 1353 | cmd = (tmp_dat & (0x3 << 25)) >> 25; |
| 1354 | is_write = (tmp_dat & (0x1 << 24)) >> 24; |
| 1355 | slvid = (tmp_dat & (0xf << 20)) >> 20; |
| 1356 | bytecnt = (tmp_dat & (0xf << 16)) >> 16; |
| 1357 | addr = (tmp_dat & (0xffff << 0)) >> 0; |
| 1358 | |
| 1359 | offset = arb->dbgregs[PMIF_MONITOR_RECORD_0_1] + i * step; |
| 1360 | wd_31_0 = readl(arb->base + offset); |
| 1361 | if (is_write) |
| 1362 | snprintf(wd_str, 12, "=0x%x", wd_31_0); |
| 1363 | else |
| 1364 | wd_str[0] = '\0'; |
| 1365 | |
| 1366 | seq_printf(m, "(%d)[chan:%d, cmd:0x%x, rw:0x%x, slvid:%d, ", |
| 1367 | i, chan, cmd, is_write, slvid); |
| 1368 | seq_printf(m, "bytecnt:%d, (addr 0x%x%s)]\n", |
| 1369 | bytecnt, addr, wd_str); |
| 1370 | } |
| 1371 | /* logging mode no need to clear record, re-enable logging */ |
| 1372 | writel(0x5, arb->base + arb->dbgregs[PMIF_MONITOR_CTRL]); |
| 1373 | } |
| 1374 | |
| 1375 | void spmi_dump_spmimst_all_reg(void) |
| 1376 | { |
| 1377 | pr_info("%s", get_spmimst_all_reg_dump()); |
| 1378 | } |
| 1379 | |
| 1380 | static void spmi_dump_spmimst_all_reg_d(struct seq_file *m) |
| 1381 | { |
| 1382 | seq_puts(m, get_spmimst_all_reg_dump()); |
| 1383 | } |
| 1384 | |
| 1385 | /* |
| 1386 | * PMIF dump busy register log |
| 1387 | */ |
| 1388 | static int proc_dump_pmif_busy_reg_show(struct seq_file *m, void *v) |
| 1389 | { |
| 1390 | seq_puts(m, "********** PMIF dump busy register**********\n"); |
| 1391 | spmi_dump_pmif_busy_reg(); |
| 1392 | spmi_dump_pmif_busy_reg_d(m); |
| 1393 | |
| 1394 | return 0; |
| 1395 | } |
| 1396 | |
| 1397 | static int proc_dump_pmif_busy_reg_open(struct inode *inode, struct file *file) |
| 1398 | { |
| 1399 | return single_open(file, proc_dump_pmif_busy_reg_show, NULL); |
| 1400 | } |
| 1401 | |
| 1402 | static const struct file_operations dump_pmif_busy_reg_proc_fops = { |
| 1403 | .open = proc_dump_pmif_busy_reg_open, |
| 1404 | .read = seq_read, |
| 1405 | }; |
| 1406 | |
| 1407 | /* |
| 1408 | * PMIF dump swinf log |
| 1409 | */ |
| 1410 | |
| 1411 | static int proc_dump_pmif_swinf_show(struct seq_file *m, void *v) |
| 1412 | { |
| 1413 | seq_puts(m, "********** PMIF dump swinf register**********\n"); |
| 1414 | spmi_dump_pmif_swinf_reg(); |
| 1415 | spmi_dump_pmif_swinf_reg_d(m); |
| 1416 | |
| 1417 | return 0; |
| 1418 | } |
| 1419 | |
| 1420 | static int proc_dump_pmif_swinf_open(struct inode *inode, struct file *file) |
| 1421 | { |
| 1422 | return single_open(file, proc_dump_pmif_swinf_show, NULL); |
| 1423 | } |
| 1424 | |
| 1425 | static const struct file_operations dump_pmif_swinf_proc_fops = { |
| 1426 | .open = proc_dump_pmif_swinf_open, |
| 1427 | .read = seq_read, |
| 1428 | }; |
| 1429 | |
| 1430 | /* |
| 1431 | * PMIF dump all register log |
| 1432 | */ |
| 1433 | static int proc_dump_pmif_all_reg_show(struct seq_file *m, void *v) |
| 1434 | { |
| 1435 | seq_puts(m, "********** PMIF dump all register**********\n"); |
| 1436 | spmi_dump_pmif_all_reg(); |
| 1437 | spmi_dump_pmif_all_reg_d(m); |
| 1438 | |
| 1439 | return 0; |
| 1440 | } |
| 1441 | |
| 1442 | static int proc_dump_pmif_all_reg_open(struct inode *inode, struct file *file) |
| 1443 | { |
| 1444 | return single_open(file, proc_dump_pmif_all_reg_show, NULL); |
| 1445 | } |
| 1446 | |
| 1447 | static const struct file_operations dump_pmif_all_reg_proc_fops = { |
| 1448 | .open = proc_dump_pmif_all_reg_open, |
| 1449 | .read = seq_read, |
| 1450 | }; |
| 1451 | |
| 1452 | /* |
| 1453 | * PMIF dump record register log |
| 1454 | */ |
| 1455 | static int proc_dump_pmif_record_reg_show(struct seq_file *m, void *v) |
| 1456 | { |
| 1457 | seq_puts(m, "********** PMIF dump record register**********\n"); |
| 1458 | seq_puts(m, "*swinf:4=MD,swinf:5:GZ,swinf:6:AP,swinf:7:RSV\n"); |
| 1459 | spmi_dump_pmif_record_reg(); |
| 1460 | spmi_dump_pmif_record_reg_d(m); |
| 1461 | |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
| 1465 | static int proc_dump_pmif_record_reg_open(struct inode *inode, |
| 1466 | struct file *file) |
| 1467 | { |
| 1468 | return single_open(file, proc_dump_pmif_record_reg_show, NULL); |
| 1469 | } |
| 1470 | |
| 1471 | static const struct file_operations dump_pmif_record_reg_proc_fops = { |
| 1472 | .open = proc_dump_pmif_record_reg_open, |
| 1473 | .read = seq_read, |
| 1474 | }; |
| 1475 | |
| 1476 | /* |
| 1477 | * SPMIMST dump all register log |
| 1478 | */ |
| 1479 | static int proc_dump_spmimst_all_reg_show(struct seq_file *m, void *v) |
| 1480 | { |
| 1481 | seq_puts(m, "********** SPMIMST dump all register**********\n"); |
| 1482 | spmi_dump_spmimst_all_reg(); |
| 1483 | spmi_dump_spmimst_all_reg_d(m); |
| 1484 | |
| 1485 | return 0; |
| 1486 | } |
| 1487 | |
| 1488 | static int proc_dump_spmimst_all_reg_open(struct inode *inode, |
| 1489 | struct file *file) |
| 1490 | { |
| 1491 | return single_open(file, proc_dump_spmimst_all_reg_show, NULL); |
| 1492 | } |
| 1493 | |
| 1494 | static const struct file_operations dump_spmimst_all_reg_proc_fops = { |
| 1495 | .open = proc_dump_spmimst_all_reg_open, |
| 1496 | .read = seq_read, |
| 1497 | }; |
| 1498 | |
| 1499 | static u32 gpmif_of; |
| 1500 | static u32 gpmif_val; |
| 1501 | static ssize_t pmif_access_show(struct device_driver *ddri, char *buf) |
| 1502 | { |
| 1503 | if (buf == NULL) { |
| 1504 | pr_notice("[%s] *buf is NULL!\n", __func__); |
| 1505 | return -EINVAL; |
| 1506 | } |
| 1507 | sprintf(buf, "[%s] [0x%x]=0x%x\n", __func__, gpmif_of, gpmif_val); |
| 1508 | |
| 1509 | return strlen(buf); |
| 1510 | } |
| 1511 | static ssize_t pmif_access_store(struct device_driver *ddri, |
| 1512 | const char *buf, size_t count) |
| 1513 | { |
| 1514 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1515 | int ret = 0; |
| 1516 | u32 offset = 0; |
| 1517 | u32 value = 0; |
| 1518 | |
| 1519 | pr_info("[%s]\n", __func__); |
| 1520 | if (buf != NULL && count != 0) { |
| 1521 | pr_info("[%s] size is %d, buf is %s\n", |
| 1522 | __func__, (int)count, buf); |
| 1523 | |
| 1524 | if (strlen(buf) < 3) { |
| 1525 | pr_notice("%s() Invalid input!!\n", __func__); |
| 1526 | return -EINVAL; |
| 1527 | } |
| 1528 | |
| 1529 | ret = sscanf(buf, "0x%x 0x%x", &offset, &value); |
| 1530 | if (ret < 0) |
| 1531 | return ret; |
| 1532 | |
| 1533 | if (value) { |
| 1534 | if (offset > arb->dbgregs[PMIF_SWINF_3_STA]) { |
| 1535 | pr_notice("%s() Illegal offset[0x%x]!!\n", |
| 1536 | __func__, offset); |
| 1537 | } else { |
| 1538 | pr_info("%s() set offset[0x%x]=0x%x\n", |
| 1539 | __func__, offset, value); |
| 1540 | writel(value, arb->base + offset); |
| 1541 | } |
| 1542 | } |
| 1543 | |
| 1544 | gpmif_of = offset; |
| 1545 | gpmif_val = readl(arb->base + offset); |
| 1546 | } |
| 1547 | return count; |
| 1548 | } |
| 1549 | static u32 gspmi_of; |
| 1550 | static u32 gspmi_val; |
| 1551 | static ssize_t spmi_access_show(struct device_driver *ddri, char *buf) |
| 1552 | { |
| 1553 | if (buf == NULL) { |
| 1554 | pr_notice("[%s] *buf is NULL!\n", __func__); |
| 1555 | return -EINVAL; |
| 1556 | } |
| 1557 | sprintf(buf, "[%s] [0x%x]=0x%x\n", __func__, gspmi_of, gspmi_val); |
| 1558 | |
| 1559 | return strlen(buf); |
| 1560 | } |
| 1561 | static ssize_t spmi_access_store(struct device_driver *ddri, |
| 1562 | const char *buf, size_t count) |
| 1563 | { |
| 1564 | struct pmif *arb = spmi_controller_get_drvdata(dbg_ctrl); |
| 1565 | int ret = 0; |
| 1566 | u32 offset = 0; |
| 1567 | u32 value = 0; |
| 1568 | |
| 1569 | pr_info("[%s]\n", __func__); |
| 1570 | if (buf != NULL && count != 0) { |
| 1571 | pr_info("[%s] size is %d, buf is %s\n", |
| 1572 | __func__, (int)count, buf); |
| 1573 | |
| 1574 | if (strlen(buf) < 3) { |
| 1575 | pr_notice("%s() Invalid input!!\n", __func__); |
| 1576 | return -EINVAL; |
| 1577 | } |
| 1578 | |
| 1579 | ret = sscanf(buf, "0x%x 0x%x", &offset, &value); |
| 1580 | if (ret < 0) |
| 1581 | return ret; |
| 1582 | |
| 1583 | if (value) { |
| 1584 | if (offset > arb->spmimst_regs[SPMI_MST_DBG]) { |
| 1585 | pr_notice("%s() Illegal offset[0x%x]!!\n", |
| 1586 | __func__, offset); |
| 1587 | } else { |
| 1588 | pr_info("%s() set offset[0x%x]=0x%x\n", |
| 1589 | __func__, offset, value); |
| 1590 | writel(value, arb->spmimst_base + offset); |
| 1591 | } |
| 1592 | } |
| 1593 | |
| 1594 | gspmi_of = offset; |
| 1595 | gspmi_val = readl(arb->spmimst_base + offset); |
| 1596 | } |
| 1597 | return count; |
| 1598 | } |
| 1599 | static DRIVER_ATTR_RW(pmif_access); |
| 1600 | static DRIVER_ATTR_RW(spmi_access); |
| 1601 | |
| 1602 | static struct driver_attribute *spmi_pmif_attr_list[] = { |
| 1603 | &driver_attr_pmif_access, |
| 1604 | &driver_attr_spmi_access, |
| 1605 | }; |
| 1606 | |
| 1607 | int spmi_pmif_create_attr(struct device_driver *driver) |
| 1608 | { |
| 1609 | int idx, err; |
| 1610 | int num = ARRAY_SIZE(spmi_pmif_attr_list); |
| 1611 | struct dentry *mtk_spmi_dir; |
| 1612 | |
| 1613 | mtk_spmi_dir = debugfs_create_dir("mtk_spmi", NULL); |
| 1614 | if (!mtk_spmi_dir) { |
| 1615 | pr_notice("fail to mkdir /sys/kernel/debug/mtk_spmi\n"); |
| 1616 | return -ENOMEM; |
| 1617 | } |
| 1618 | |
| 1619 | /*--/sys/kernel/debug/mtk_spmi--*/ |
| 1620 | debugfs_create_file("dump_pmif_busy_reg", 0644, |
| 1621 | mtk_spmi_dir, NULL, |
| 1622 | &dump_pmif_busy_reg_proc_fops); |
| 1623 | debugfs_create_file("dump_pmif_swinf", 0644, |
| 1624 | mtk_spmi_dir, NULL, |
| 1625 | &dump_pmif_swinf_proc_fops); |
| 1626 | debugfs_create_file("dump_pmif_all_reg", 0644, |
| 1627 | mtk_spmi_dir, NULL, |
| 1628 | &dump_pmif_all_reg_proc_fops); |
| 1629 | debugfs_create_file("dump_pmif_record_reg", 0644, |
| 1630 | mtk_spmi_dir, NULL, |
| 1631 | &dump_pmif_record_reg_proc_fops); |
| 1632 | debugfs_create_file("dump_spmimst_all_reg", 0644, |
| 1633 | mtk_spmi_dir, NULL, |
| 1634 | &dump_spmimst_all_reg_proc_fops); |
| 1635 | |
| 1636 | if (driver == NULL) |
| 1637 | return -EINVAL; |
| 1638 | |
| 1639 | /*--/sys/devices/platform/10027000.spmi/driver--*/ |
| 1640 | for (idx = 0; idx < num; idx++) { |
| 1641 | err = driver_create_file(driver, spmi_pmif_attr_list[idx]); |
| 1642 | if (err) { |
| 1643 | pr_notice("%s() driver_create_file %s err:%d\n", |
| 1644 | __func__, spmi_pmif_attr_list[idx]->attr.name, err); |
| 1645 | break; |
| 1646 | } |
| 1647 | } |
| 1648 | return err; |
| 1649 | } |
| 1650 | |
| 1651 | int spmi_pmif_dbg_init(struct spmi_controller *ctrl) |
| 1652 | { |
| 1653 | struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
| 1654 | |
| 1655 | dbg_ctrl = ctrl; |
| 1656 | wp = d_log_buf; |
| 1657 | if (of_device_is_compatible(ctrl->dev.parent->of_node, |
| 1658 | "mediatek,mt6885-pmif")) { |
| 1659 | arb->dbgregs = mt6885_pmif_dbg_regs; |
| 1660 | arb->dbgver = 1; |
| 1661 | } else if (of_device_is_compatible(ctrl->dev.parent->of_node, |
| 1662 | "mediatek,mt6873-pmif")) { |
| 1663 | arb->dbgregs = mt6873_pmif_dbg_regs; |
| 1664 | arb->dbgver = 1; |
| 1665 | } else if (of_device_is_compatible(ctrl->dev.parent->of_node, |
| 1666 | "mediatek,mt6880-pmif-m")) { |
| 1667 | arb->dbgregs = mt6880_pmif_dbg_regs; |
| 1668 | arb->dbgver = 2; |
| 1669 | } else if (of_device_is_compatible(ctrl->dev.parent->of_node, |
| 1670 | "mediatek,mt6880-pmif-p")) { |
| 1671 | arb->dbgregs = mt6880_pmif_dbg_regs; |
| 1672 | arb->dbgver = 2; |
| 1673 | } |
| 1674 | |
| 1675 | return 0; |
| 1676 | } |