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192.168.1.100 / T800 / c8bdf760eff3f191e103ce6507638f5d0d4e6b51 / . / src / kernel / linux / v4.19 / drivers / tty / synclink_gt.c
blob: b88ecf102764e43e532a461f148ad97c282bea78 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static char *driver_name = "SyncLink GT";
91static char *slgt_driver_name = "synclink_gt";
92static char *tty_dev_prefix = "ttySLG";
93MODULE_LICENSE("GPL");
94#define MGSL_MAGIC 0x5401
95#define MAX_DEVICES 32
96
97static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103};
104MODULE_DEVICE_TABLE(pci, pci_table);
105
106static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107static void remove_one(struct pci_dev *dev);
108static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
112 .remove = remove_one,
113};
114
115static bool pci_registered;
116
117/*
118 * module configuration and status
119 */
120static struct slgt_info *slgt_device_list;
121static int slgt_device_count;
122
123static int ttymajor;
124static int debug_level;
125static int maxframe[MAX_DEVICES];
126
127module_param(ttymajor, int, 0);
128module_param(debug_level, int, 0);
129module_param_array(maxframe, int, NULL, 0);
130
131MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
134
135/*
136 * tty support and callbacks
137 */
138static struct tty_driver *serial_driver;
139
140static int open(struct tty_struct *tty, struct file * filp);
141static void close(struct tty_struct *tty, struct file * filp);
142static void hangup(struct tty_struct *tty);
143static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
144
145static int write(struct tty_struct *tty, const unsigned char *buf, int count);
146static int put_char(struct tty_struct *tty, unsigned char ch);
147static void send_xchar(struct tty_struct *tty, char ch);
148static void wait_until_sent(struct tty_struct *tty, int timeout);
149static int write_room(struct tty_struct *tty);
150static void flush_chars(struct tty_struct *tty);
151static void flush_buffer(struct tty_struct *tty);
152static void tx_hold(struct tty_struct *tty);
153static void tx_release(struct tty_struct *tty);
154
155static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
156static int chars_in_buffer(struct tty_struct *tty);
157static void throttle(struct tty_struct * tty);
158static void unthrottle(struct tty_struct * tty);
159static int set_break(struct tty_struct *tty, int break_state);
160
161/*
162 * generic HDLC support and callbacks
163 */
164#if SYNCLINK_GENERIC_HDLC
165#define dev_to_port(D) (dev_to_hdlc(D)->priv)
166static void hdlcdev_tx_done(struct slgt_info *info);
167static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
168static int hdlcdev_init(struct slgt_info *info);
169static void hdlcdev_exit(struct slgt_info *info);
170#endif
171
172
173/*
174 * device specific structures, macros and functions
175 */
176
177#define SLGT_MAX_PORTS 4
178#define SLGT_REG_SIZE 256
179
180/*
181 * conditional wait facility
182 */
183struct cond_wait {
184 struct cond_wait *next;
185 wait_queue_head_t q;
186 wait_queue_entry_t wait;
187 unsigned int data;
188};
189static void init_cond_wait(struct cond_wait *w, unsigned int data);
190static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
191static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
192static void flush_cond_wait(struct cond_wait **head);
193
194/*
195 * DMA buffer descriptor and access macros
196 */
197struct slgt_desc
198{
199 __le16 count;
200 __le16 status;
201 __le32 pbuf; /* physical address of data buffer */
202 __le32 next; /* physical address of next descriptor */
203
204 /* driver book keeping */
205 char *buf; /* virtual address of data buffer */
206 unsigned int pdesc; /* physical address of this descriptor */
207 dma_addr_t buf_dma_addr;
208 unsigned short buf_count;
209};
210
211#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
212#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
213#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
214#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
215#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
216#define desc_count(a) (le16_to_cpu((a).count))
217#define desc_status(a) (le16_to_cpu((a).status))
218#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
219#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
220#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
221#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
222#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
223
224struct _input_signal_events {
225 int ri_up;
226 int ri_down;
227 int dsr_up;
228 int dsr_down;
229 int dcd_up;
230 int dcd_down;
231 int cts_up;
232 int cts_down;
233};
234
235/*
236 * device instance data structure
237 */
238struct slgt_info {
239 void *if_ptr; /* General purpose pointer (used by SPPP) */
240 struct tty_port port;
241
242 struct slgt_info *next_device; /* device list link */
243
244 int magic;
245
246 char device_name[25];
247 struct pci_dev *pdev;
248
249 int port_count; /* count of ports on adapter */
250 int adapter_num; /* adapter instance number */
251 int port_num; /* port instance number */
252
253 /* array of pointers to port contexts on this adapter */
254 struct slgt_info *port_array[SLGT_MAX_PORTS];
255
256 int line; /* tty line instance number */
257
258 struct mgsl_icount icount;
259
260 int timeout;
261 int x_char; /* xon/xoff character */
262 unsigned int read_status_mask;
263 unsigned int ignore_status_mask;
264
265 wait_queue_head_t status_event_wait_q;
266 wait_queue_head_t event_wait_q;
267 struct timer_list tx_timer;
268 struct timer_list rx_timer;
269
270 unsigned int gpio_present;
271 struct cond_wait *gpio_wait_q;
272
273 spinlock_t lock; /* spinlock for synchronizing with ISR */
274
275 struct work_struct task;
276 u32 pending_bh;
277 bool bh_requested;
278 bool bh_running;
279
280 int isr_overflow;
281 bool irq_requested; /* true if IRQ requested */
282 bool irq_occurred; /* for diagnostics use */
283
284 /* device configuration */
285
286 unsigned int bus_type;
287 unsigned int irq_level;
288 unsigned long irq_flags;
289
290 unsigned char __iomem * reg_addr; /* memory mapped registers address */
291 u32 phys_reg_addr;
292 bool reg_addr_requested;
293
294 MGSL_PARAMS params; /* communications parameters */
295 u32 idle_mode;
296 u32 max_frame_size; /* as set by device config */
297
298 unsigned int rbuf_fill_level;
299 unsigned int rx_pio;
300 unsigned int if_mode;
301 unsigned int base_clock;
302 unsigned int xsync;
303 unsigned int xctrl;
304
305 /* device status */
306
307 bool rx_enabled;
308 bool rx_restart;
309
310 bool tx_enabled;
311 bool tx_active;
312
313 unsigned char signals; /* serial signal states */
314 int init_error; /* initialization error */
315
316 unsigned char *tx_buf;
317 int tx_count;
318
319 char *flag_buf;
320 bool drop_rts_on_tx_done;
321 struct _input_signal_events input_signal_events;
322
323 int dcd_chkcount; /* check counts to prevent */
324 int cts_chkcount; /* too many IRQs if a signal */
325 int dsr_chkcount; /* is floating */
326 int ri_chkcount;
327
328 char *bufs; /* virtual address of DMA buffer lists */
329 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
330
331 unsigned int rbuf_count;
332 struct slgt_desc *rbufs;
333 unsigned int rbuf_current;
334 unsigned int rbuf_index;
335 unsigned int rbuf_fill_index;
336 unsigned short rbuf_fill_count;
337
338 unsigned int tbuf_count;
339 struct slgt_desc *tbufs;
340 unsigned int tbuf_current;
341 unsigned int tbuf_start;
342
343 unsigned char *tmp_rbuf;
344 unsigned int tmp_rbuf_count;
345
346 /* SPPP/Cisco HDLC device parts */
347
348 int netcount;
349 spinlock_t netlock;
350#if SYNCLINK_GENERIC_HDLC
351 struct net_device *netdev;
352#endif
353
354};
355
356static MGSL_PARAMS default_params = {
357 .mode = MGSL_MODE_HDLC,
358 .loopback = 0,
359 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
360 .encoding = HDLC_ENCODING_NRZI_SPACE,
361 .clock_speed = 0,
362 .addr_filter = 0xff,
363 .crc_type = HDLC_CRC_16_CCITT,
364 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
365 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
366 .data_rate = 9600,
367 .data_bits = 8,
368 .stop_bits = 1,
369 .parity = ASYNC_PARITY_NONE
370};
371
372
373#define BH_RECEIVE 1
374#define BH_TRANSMIT 2
375#define BH_STATUS 4
376#define IO_PIN_SHUTDOWN_LIMIT 100
377
378#define DMABUFSIZE 256
379#define DESC_LIST_SIZE 4096
380
381#define MASK_PARITY BIT1
382#define MASK_FRAMING BIT0
383#define MASK_BREAK BIT14
384#define MASK_OVERRUN BIT4
385
386#define GSR 0x00 /* global status */
387#define JCR 0x04 /* JTAG control */
388#define IODR 0x08 /* GPIO direction */
389#define IOER 0x0c /* GPIO interrupt enable */
390#define IOVR 0x10 /* GPIO value */
391#define IOSR 0x14 /* GPIO interrupt status */
392#define TDR 0x80 /* tx data */
393#define RDR 0x80 /* rx data */
394#define TCR 0x82 /* tx control */
395#define TIR 0x84 /* tx idle */
396#define TPR 0x85 /* tx preamble */
397#define RCR 0x86 /* rx control */
398#define VCR 0x88 /* V.24 control */
399#define CCR 0x89 /* clock control */
400#define BDR 0x8a /* baud divisor */
401#define SCR 0x8c /* serial control */
402#define SSR 0x8e /* serial status */
403#define RDCSR 0x90 /* rx DMA control/status */
404#define TDCSR 0x94 /* tx DMA control/status */
405#define RDDAR 0x98 /* rx DMA descriptor address */
406#define TDDAR 0x9c /* tx DMA descriptor address */
407#define XSR 0x40 /* extended sync pattern */
408#define XCR 0x44 /* extended control */
409
410#define RXIDLE BIT14
411#define RXBREAK BIT14
412#define IRQ_TXDATA BIT13
413#define IRQ_TXIDLE BIT12
414#define IRQ_TXUNDER BIT11 /* HDLC */
415#define IRQ_RXDATA BIT10
416#define IRQ_RXIDLE BIT9 /* HDLC */
417#define IRQ_RXBREAK BIT9 /* async */
418#define IRQ_RXOVER BIT8
419#define IRQ_DSR BIT7
420#define IRQ_CTS BIT6
421#define IRQ_DCD BIT5
422#define IRQ_RI BIT4
423#define IRQ_ALL 0x3ff0
424#define IRQ_MASTER BIT0
425
426#define slgt_irq_on(info, mask) \
427 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
428#define slgt_irq_off(info, mask) \
429 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
430
431static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
432static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
433static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
434static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
435static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
436static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
437
438static void msc_set_vcr(struct slgt_info *info);
439
440static int startup(struct slgt_info *info);
441static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
442static void shutdown(struct slgt_info *info);
443static void program_hw(struct slgt_info *info);
444static void change_params(struct slgt_info *info);
445
446static int register_test(struct slgt_info *info);
447static int irq_test(struct slgt_info *info);
448static int loopback_test(struct slgt_info *info);
449static int adapter_test(struct slgt_info *info);
450
451static void reset_adapter(struct slgt_info *info);
452static void reset_port(struct slgt_info *info);
453static void async_mode(struct slgt_info *info);
454static void sync_mode(struct slgt_info *info);
455
456static void rx_stop(struct slgt_info *info);
457static void rx_start(struct slgt_info *info);
458static void reset_rbufs(struct slgt_info *info);
459static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
460static void rdma_reset(struct slgt_info *info);
461static bool rx_get_frame(struct slgt_info *info);
462static bool rx_get_buf(struct slgt_info *info);
463
464static void tx_start(struct slgt_info *info);
465static void tx_stop(struct slgt_info *info);
466static void tx_set_idle(struct slgt_info *info);
467static unsigned int free_tbuf_count(struct slgt_info *info);
468static unsigned int tbuf_bytes(struct slgt_info *info);
469static void reset_tbufs(struct slgt_info *info);
470static void tdma_reset(struct slgt_info *info);
471static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
472
473static void get_signals(struct slgt_info *info);
474static void set_signals(struct slgt_info *info);
475static void enable_loopback(struct slgt_info *info);
476static void set_rate(struct slgt_info *info, u32 data_rate);
477
478static int bh_action(struct slgt_info *info);
479static void bh_handler(struct work_struct *work);
480static void bh_transmit(struct slgt_info *info);
481static void isr_serial(struct slgt_info *info);
482static void isr_rdma(struct slgt_info *info);
483static void isr_txeom(struct slgt_info *info, unsigned short status);
484static void isr_tdma(struct slgt_info *info);
485
486static int alloc_dma_bufs(struct slgt_info *info);
487static void free_dma_bufs(struct slgt_info *info);
488static int alloc_desc(struct slgt_info *info);
489static void free_desc(struct slgt_info *info);
490static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
491static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492
493static int alloc_tmp_rbuf(struct slgt_info *info);
494static void free_tmp_rbuf(struct slgt_info *info);
495
496static void tx_timeout(struct timer_list *t);
497static void rx_timeout(struct timer_list *t);
498
499/*
500 * ioctl handlers
501 */
502static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
503static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
504static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505static int get_txidle(struct slgt_info *info, int __user *idle_mode);
506static int set_txidle(struct slgt_info *info, int idle_mode);
507static int tx_enable(struct slgt_info *info, int enable);
508static int tx_abort(struct slgt_info *info);
509static int rx_enable(struct slgt_info *info, int enable);
510static int modem_input_wait(struct slgt_info *info,int arg);
511static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
512static int tiocmget(struct tty_struct *tty);
513static int tiocmset(struct tty_struct *tty,
514 unsigned int set, unsigned int clear);
515static int set_break(struct tty_struct *tty, int break_state);
516static int get_interface(struct slgt_info *info, int __user *if_mode);
517static int set_interface(struct slgt_info *info, int if_mode);
518static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
519static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521static int get_xsync(struct slgt_info *info, int __user *if_mode);
522static int set_xsync(struct slgt_info *info, int if_mode);
523static int get_xctrl(struct slgt_info *info, int __user *if_mode);
524static int set_xctrl(struct slgt_info *info, int if_mode);
525
526/*
527 * driver functions
528 */
529static void add_device(struct slgt_info *info);
530static void device_init(int adapter_num, struct pci_dev *pdev);
531static int claim_resources(struct slgt_info *info);
532static void release_resources(struct slgt_info *info);
533
534/*
535 * DEBUG OUTPUT CODE
536 */
537#ifndef DBGINFO
538#define DBGINFO(fmt)
539#endif
540#ifndef DBGERR
541#define DBGERR(fmt)
542#endif
543#ifndef DBGBH
544#define DBGBH(fmt)
545#endif
546#ifndef DBGISR
547#define DBGISR(fmt)
548#endif
549
550#ifdef DBGDATA
551static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
552{
553 int i;
554 int linecount;
555 printk("%s %s data:\n",info->device_name, label);
556 while(count) {
557 linecount = (count > 16) ? 16 : count;
558 for(i=0; i < linecount; i++)
559 printk("%02X ",(unsigned char)data[i]);
560 for(;i<17;i++)
561 printk(" ");
562 for(i=0;i<linecount;i++) {
563 if (data[i]>=040 && data[i]<=0176)
564 printk("%c",data[i]);
565 else
566 printk(".");
567 }
568 printk("\n");
569 data += linecount;
570 count -= linecount;
571 }
572}
573#else
574#define DBGDATA(info, buf, size, label)
575#endif
576
577#ifdef DBGTBUF
578static void dump_tbufs(struct slgt_info *info)
579{
580 int i;
581 printk("tbuf_current=%d\n", info->tbuf_current);
582 for (i=0 ; i < info->tbuf_count ; i++) {
583 printk("%d: count=%04X status=%04X\n",
584 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
585 }
586}
587#else
588#define DBGTBUF(info)
589#endif
590
591#ifdef DBGRBUF
592static void dump_rbufs(struct slgt_info *info)
593{
594 int i;
595 printk("rbuf_current=%d\n", info->rbuf_current);
596 for (i=0 ; i < info->rbuf_count ; i++) {
597 printk("%d: count=%04X status=%04X\n",
598 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
599 }
600}
601#else
602#define DBGRBUF(info)
603#endif
604
605static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
606{
607#ifdef SANITY_CHECK
608 if (!info) {
609 printk("null struct slgt_info for (%s) in %s\n", devname, name);
610 return 1;
611 }
612 if (info->magic != MGSL_MAGIC) {
613 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
614 return 1;
615 }
616#else
617 if (!info)
618 return 1;
619#endif
620 return 0;
621}
622
623/**
624 * line discipline callback wrappers
625 *
626 * The wrappers maintain line discipline references
627 * while calling into the line discipline.
628 *
629 * ldisc_receive_buf - pass receive data to line discipline
630 */
631static void ldisc_receive_buf(struct tty_struct *tty,
632 const __u8 *data, char *flags, int count)
633{
634 struct tty_ldisc *ld;
635 if (!tty)
636 return;
637 ld = tty_ldisc_ref(tty);
638 if (ld) {
639 if (ld->ops->receive_buf)
640 ld->ops->receive_buf(tty, data, flags, count);
641 tty_ldisc_deref(ld);
642 }
643}
644
645/* tty callbacks */
646
647static int open(struct tty_struct *tty, struct file *filp)
648{
649 struct slgt_info *info;
650 int retval, line;
651 unsigned long flags;
652
653 line = tty->index;
654 if (line >= slgt_device_count) {
655 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
656 return -ENODEV;
657 }
658
659 info = slgt_device_list;
660 while(info && info->line != line)
661 info = info->next_device;
662 if (sanity_check(info, tty->name, "open"))
663 return -ENODEV;
664 if (info->init_error) {
665 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
666 return -ENODEV;
667 }
668
669 tty->driver_data = info;
670 info->port.tty = tty;
671
672 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
673
674 mutex_lock(&info->port.mutex);
675 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
676
677 spin_lock_irqsave(&info->netlock, flags);
678 if (info->netcount) {
679 retval = -EBUSY;
680 spin_unlock_irqrestore(&info->netlock, flags);
681 mutex_unlock(&info->port.mutex);
682 goto cleanup;
683 }
684 info->port.count++;
685 spin_unlock_irqrestore(&info->netlock, flags);
686
687 if (info->port.count == 1) {
688 /* 1st open on this device, init hardware */
689 retval = startup(info);
690 if (retval < 0) {
691 mutex_unlock(&info->port.mutex);
692 goto cleanup;
693 }
694 }
695 mutex_unlock(&info->port.mutex);
696 retval = block_til_ready(tty, filp, info);
697 if (retval) {
698 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
699 goto cleanup;
700 }
701
702 retval = 0;
703
704cleanup:
705 if (retval) {
706 if (tty->count == 1)
707 info->port.tty = NULL; /* tty layer will release tty struct */
708 if(info->port.count)
709 info->port.count--;
710 }
711
712 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
713 return retval;
714}
715
716static void close(struct tty_struct *tty, struct file *filp)
717{
718 struct slgt_info *info = tty->driver_data;
719
720 if (sanity_check(info, tty->name, "close"))
721 return;
722 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
723
724 if (tty_port_close_start(&info->port, tty, filp) == 0)
725 goto cleanup;
726
727 mutex_lock(&info->port.mutex);
728 if (tty_port_initialized(&info->port))
729 wait_until_sent(tty, info->timeout);
730 flush_buffer(tty);
731 tty_ldisc_flush(tty);
732
733 shutdown(info);
734 mutex_unlock(&info->port.mutex);
735
736 tty_port_close_end(&info->port, tty);
737 info->port.tty = NULL;
738cleanup:
739 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
740}
741
742static void hangup(struct tty_struct *tty)
743{
744 struct slgt_info *info = tty->driver_data;
745 unsigned long flags;
746
747 if (sanity_check(info, tty->name, "hangup"))
748 return;
749 DBGINFO(("%s hangup\n", info->device_name));
750
751 flush_buffer(tty);
752
753 mutex_lock(&info->port.mutex);
754 shutdown(info);
755
756 spin_lock_irqsave(&info->port.lock, flags);
757 info->port.count = 0;
758 info->port.tty = NULL;
759 spin_unlock_irqrestore(&info->port.lock, flags);
760 tty_port_set_active(&info->port, 0);
761 mutex_unlock(&info->port.mutex);
762
763 wake_up_interruptible(&info->port.open_wait);
764}
765
766static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
767{
768 struct slgt_info *info = tty->driver_data;
769 unsigned long flags;
770
771 DBGINFO(("%s set_termios\n", tty->driver->name));
772
773 change_params(info);
774
775 /* Handle transition to B0 status */
776 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
777 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
778 spin_lock_irqsave(&info->lock,flags);
779 set_signals(info);
780 spin_unlock_irqrestore(&info->lock,flags);
781 }
782
783 /* Handle transition away from B0 status */
784 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
785 info->signals |= SerialSignal_DTR;
786 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
787 info->signals |= SerialSignal_RTS;
788 spin_lock_irqsave(&info->lock,flags);
789 set_signals(info);
790 spin_unlock_irqrestore(&info->lock,flags);
791 }
792
793 /* Handle turning off CRTSCTS */
794 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
795 tty->hw_stopped = 0;
796 tx_release(tty);
797 }
798}
799
800static void update_tx_timer(struct slgt_info *info)
801{
802 /*
803 * use worst case speed of 1200bps to calculate transmit timeout
804 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
805 */
806 if (info->params.mode == MGSL_MODE_HDLC) {
807 int timeout = (tbuf_bytes(info) * 7) + 1000;
808 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
809 }
810}
811
812static int write(struct tty_struct *tty,
813 const unsigned char *buf, int count)
814{
815 int ret = 0;
816 struct slgt_info *info = tty->driver_data;
817 unsigned long flags;
818
819 if (sanity_check(info, tty->name, "write"))
820 return -EIO;
821
822 DBGINFO(("%s write count=%d\n", info->device_name, count));
823
824 if (!info->tx_buf || (count > info->max_frame_size))
825 return -EIO;
826
827 if (!count || tty->stopped || tty->hw_stopped)
828 return 0;
829
830 spin_lock_irqsave(&info->lock, flags);
831
832 if (info->tx_count) {
833 /* send accumulated data from send_char() */
834 if (!tx_load(info, info->tx_buf, info->tx_count))
835 goto cleanup;
836 info->tx_count = 0;
837 }
838
839 if (tx_load(info, buf, count))
840 ret = count;
841
842cleanup:
843 spin_unlock_irqrestore(&info->lock, flags);
844 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
845 return ret;
846}
847
848static int put_char(struct tty_struct *tty, unsigned char ch)
849{
850 struct slgt_info *info = tty->driver_data;
851 unsigned long flags;
852 int ret = 0;
853
854 if (sanity_check(info, tty->name, "put_char"))
855 return 0;
856 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
857 if (!info->tx_buf)
858 return 0;
859 spin_lock_irqsave(&info->lock,flags);
860 if (info->tx_count < info->max_frame_size) {
861 info->tx_buf[info->tx_count++] = ch;
862 ret = 1;
863 }
864 spin_unlock_irqrestore(&info->lock,flags);
865 return ret;
866}
867
868static void send_xchar(struct tty_struct *tty, char ch)
869{
870 struct slgt_info *info = tty->driver_data;
871 unsigned long flags;
872
873 if (sanity_check(info, tty->name, "send_xchar"))
874 return;
875 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
876 info->x_char = ch;
877 if (ch) {
878 spin_lock_irqsave(&info->lock,flags);
879 if (!info->tx_enabled)
880 tx_start(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883}
884
885static void wait_until_sent(struct tty_struct *tty, int timeout)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long orig_jiffies, char_time;
889
890 if (!info )
891 return;
892 if (sanity_check(info, tty->name, "wait_until_sent"))
893 return;
894 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
895 if (!tty_port_initialized(&info->port))
896 goto exit;
897
898 orig_jiffies = jiffies;
899
900 /* Set check interval to 1/5 of estimated time to
901 * send a character, and make it at least 1. The check
902 * interval should also be less than the timeout.
903 * Note: use tight timings here to satisfy the NIST-PCTS.
904 */
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923exit:
924 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
925}
926
927static int write_room(struct tty_struct *tty)
928{
929 struct slgt_info *info = tty->driver_data;
930 int ret;
931
932 if (sanity_check(info, tty->name, "write_room"))
933 return 0;
934 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
935 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
936 return ret;
937}
938
939static void flush_chars(struct tty_struct *tty)
940{
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "flush_chars"))
945 return;
946 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
947
948 if (info->tx_count <= 0 || tty->stopped ||
949 tty->hw_stopped || !info->tx_buf)
950 return;
951
952 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
953
954 spin_lock_irqsave(&info->lock,flags);
955 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
956 info->tx_count = 0;
957 spin_unlock_irqrestore(&info->lock,flags);
958}
959
960static void flush_buffer(struct tty_struct *tty)
961{
962 struct slgt_info *info = tty->driver_data;
963 unsigned long flags;
964
965 if (sanity_check(info, tty->name, "flush_buffer"))
966 return;
967 DBGINFO(("%s flush_buffer\n", info->device_name));
968
969 spin_lock_irqsave(&info->lock, flags);
970 info->tx_count = 0;
971 spin_unlock_irqrestore(&info->lock, flags);
972
973 tty_wakeup(tty);
974}
975
976/*
977 * throttle (stop) transmitter
978 */
979static void tx_hold(struct tty_struct *tty)
980{
981 struct slgt_info *info = tty->driver_data;
982 unsigned long flags;
983
984 if (sanity_check(info, tty->name, "tx_hold"))
985 return;
986 DBGINFO(("%s tx_hold\n", info->device_name));
987 spin_lock_irqsave(&info->lock,flags);
988 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
989 tx_stop(info);
990 spin_unlock_irqrestore(&info->lock,flags);
991}
992
993/*
994 * release (start) transmitter
995 */
996static void tx_release(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_release"))
1002 return;
1003 DBGINFO(("%s tx_release\n", info->device_name));
1004 spin_lock_irqsave(&info->lock, flags);
1005 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1006 info->tx_count = 0;
1007 spin_unlock_irqrestore(&info->lock, flags);
1008}
1009
1010/*
1011 * Service an IOCTL request
1012 *
1013 * Arguments
1014 *
1015 * tty pointer to tty instance data
1016 * cmd IOCTL command code
1017 * arg command argument/context
1018 *
1019 * Return 0 if success, otherwise error code
1020 */
1021static int ioctl(struct tty_struct *tty,
1022 unsigned int cmd, unsigned long arg)
1023{
1024 struct slgt_info *info = tty->driver_data;
1025 void __user *argp = (void __user *)arg;
1026 int ret;
1027
1028 if (sanity_check(info, tty->name, "ioctl"))
1029 return -ENODEV;
1030 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1031
1032 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1033 (cmd != TIOCMIWAIT)) {
1034 if (tty_io_error(tty))
1035 return -EIO;
1036 }
1037
1038 switch (cmd) {
1039 case MGSL_IOCWAITEVENT:
1040 return wait_mgsl_event(info, argp);
1041 case TIOCMIWAIT:
1042 return modem_input_wait(info,(int)arg);
1043 case MGSL_IOCSGPIO:
1044 return set_gpio(info, argp);
1045 case MGSL_IOCGGPIO:
1046 return get_gpio(info, argp);
1047 case MGSL_IOCWAITGPIO:
1048 return wait_gpio(info, argp);
1049 case MGSL_IOCGXSYNC:
1050 return get_xsync(info, argp);
1051 case MGSL_IOCSXSYNC:
1052 return set_xsync(info, (int)arg);
1053 case MGSL_IOCGXCTRL:
1054 return get_xctrl(info, argp);
1055 case MGSL_IOCSXCTRL:
1056 return set_xctrl(info, (int)arg);
1057 }
1058 mutex_lock(&info->port.mutex);
1059 switch (cmd) {
1060 case MGSL_IOCGPARAMS:
1061 ret = get_params(info, argp);
1062 break;
1063 case MGSL_IOCSPARAMS:
1064 ret = set_params(info, argp);
1065 break;
1066 case MGSL_IOCGTXIDLE:
1067 ret = get_txidle(info, argp);
1068 break;
1069 case MGSL_IOCSTXIDLE:
1070 ret = set_txidle(info, (int)arg);
1071 break;
1072 case MGSL_IOCTXENABLE:
1073 ret = tx_enable(info, (int)arg);
1074 break;
1075 case MGSL_IOCRXENABLE:
1076 ret = rx_enable(info, (int)arg);
1077 break;
1078 case MGSL_IOCTXABORT:
1079 ret = tx_abort(info);
1080 break;
1081 case MGSL_IOCGSTATS:
1082 ret = get_stats(info, argp);
1083 break;
1084 case MGSL_IOCGIF:
1085 ret = get_interface(info, argp);
1086 break;
1087 case MGSL_IOCSIF:
1088 ret = set_interface(info,(int)arg);
1089 break;
1090 default:
1091 ret = -ENOIOCTLCMD;
1092 }
1093 mutex_unlock(&info->port.mutex);
1094 return ret;
1095}
1096
1097static int get_icount(struct tty_struct *tty,
1098 struct serial_icounter_struct *icount)
1099
1100{
1101 struct slgt_info *info = tty->driver_data;
1102 struct mgsl_icount cnow; /* kernel counter temps */
1103 unsigned long flags;
1104
1105 spin_lock_irqsave(&info->lock,flags);
1106 cnow = info->icount;
1107 spin_unlock_irqrestore(&info->lock,flags);
1108
1109 icount->cts = cnow.cts;
1110 icount->dsr = cnow.dsr;
1111 icount->rng = cnow.rng;
1112 icount->dcd = cnow.dcd;
1113 icount->rx = cnow.rx;
1114 icount->tx = cnow.tx;
1115 icount->frame = cnow.frame;
1116 icount->overrun = cnow.overrun;
1117 icount->parity = cnow.parity;
1118 icount->brk = cnow.brk;
1119 icount->buf_overrun = cnow.buf_overrun;
1120
1121 return 0;
1122}
1123
1124/*
1125 * support for 32 bit ioctl calls on 64 bit systems
1126 */
1127#ifdef CONFIG_COMPAT
1128static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1129{
1130 struct MGSL_PARAMS32 tmp_params;
1131
1132 DBGINFO(("%s get_params32\n", info->device_name));
1133 memset(&tmp_params, 0, sizeof(tmp_params));
1134 tmp_params.mode = (compat_ulong_t)info->params.mode;
1135 tmp_params.loopback = info->params.loopback;
1136 tmp_params.flags = info->params.flags;
1137 tmp_params.encoding = info->params.encoding;
1138 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1139 tmp_params.addr_filter = info->params.addr_filter;
1140 tmp_params.crc_type = info->params.crc_type;
1141 tmp_params.preamble_length = info->params.preamble_length;
1142 tmp_params.preamble = info->params.preamble;
1143 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1144 tmp_params.data_bits = info->params.data_bits;
1145 tmp_params.stop_bits = info->params.stop_bits;
1146 tmp_params.parity = info->params.parity;
1147 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1148 return -EFAULT;
1149 return 0;
1150}
1151
1152static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1153{
1154 struct MGSL_PARAMS32 tmp_params;
1155
1156 DBGINFO(("%s set_params32\n", info->device_name));
1157 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1158 return -EFAULT;
1159
1160 spin_lock(&info->lock);
1161 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1162 info->base_clock = tmp_params.clock_speed;
1163 } else {
1164 info->params.mode = tmp_params.mode;
1165 info->params.loopback = tmp_params.loopback;
1166 info->params.flags = tmp_params.flags;
1167 info->params.encoding = tmp_params.encoding;
1168 info->params.clock_speed = tmp_params.clock_speed;
1169 info->params.addr_filter = tmp_params.addr_filter;
1170 info->params.crc_type = tmp_params.crc_type;
1171 info->params.preamble_length = tmp_params.preamble_length;
1172 info->params.preamble = tmp_params.preamble;
1173 info->params.data_rate = tmp_params.data_rate;
1174 info->params.data_bits = tmp_params.data_bits;
1175 info->params.stop_bits = tmp_params.stop_bits;
1176 info->params.parity = tmp_params.parity;
1177 }
1178 spin_unlock(&info->lock);
1179
1180 program_hw(info);
1181
1182 return 0;
1183}
1184
1185static long slgt_compat_ioctl(struct tty_struct *tty,
1186 unsigned int cmd, unsigned long arg)
1187{
1188 struct slgt_info *info = tty->driver_data;
1189 int rc;
1190
1191 if (sanity_check(info, tty->name, "compat_ioctl"))
1192 return -ENODEV;
1193 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1194
1195 switch (cmd) {
1196 case MGSL_IOCSPARAMS32:
1197 rc = set_params32(info, compat_ptr(arg));
1198 break;
1199
1200 case MGSL_IOCGPARAMS32:
1201 rc = get_params32(info, compat_ptr(arg));
1202 break;
1203
1204 case MGSL_IOCGPARAMS:
1205 case MGSL_IOCSPARAMS:
1206 case MGSL_IOCGTXIDLE:
1207 case MGSL_IOCGSTATS:
1208 case MGSL_IOCWAITEVENT:
1209 case MGSL_IOCGIF:
1210 case MGSL_IOCSGPIO:
1211 case MGSL_IOCGGPIO:
1212 case MGSL_IOCWAITGPIO:
1213 case MGSL_IOCGXSYNC:
1214 case MGSL_IOCGXCTRL:
1215 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1216 break;
1217 default:
1218 rc = ioctl(tty, cmd, arg);
1219 }
1220 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1221 return rc;
1222}
1223#else
1224#define slgt_compat_ioctl NULL
1225#endif /* ifdef CONFIG_COMPAT */
1226
1227/*
1228 * proc fs support
1229 */
1230static inline void line_info(struct seq_file *m, struct slgt_info *info)
1231{
1232 char stat_buf[30];
1233 unsigned long flags;
1234
1235 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1236 info->device_name, info->phys_reg_addr,
1237 info->irq_level, info->max_frame_size);
1238
1239 /* output current serial signal states */
1240 spin_lock_irqsave(&info->lock,flags);
1241 get_signals(info);
1242 spin_unlock_irqrestore(&info->lock,flags);
1243
1244 stat_buf[0] = 0;
1245 stat_buf[1] = 0;
1246 if (info->signals & SerialSignal_RTS)
1247 strcat(stat_buf, "|RTS");
1248 if (info->signals & SerialSignal_CTS)
1249 strcat(stat_buf, "|CTS");
1250 if (info->signals & SerialSignal_DTR)
1251 strcat(stat_buf, "|DTR");
1252 if (info->signals & SerialSignal_DSR)
1253 strcat(stat_buf, "|DSR");
1254 if (info->signals & SerialSignal_DCD)
1255 strcat(stat_buf, "|CD");
1256 if (info->signals & SerialSignal_RI)
1257 strcat(stat_buf, "|RI");
1258
1259 if (info->params.mode != MGSL_MODE_ASYNC) {
1260 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1261 info->icount.txok, info->icount.rxok);
1262 if (info->icount.txunder)
1263 seq_printf(m, " txunder:%d", info->icount.txunder);
1264 if (info->icount.txabort)
1265 seq_printf(m, " txabort:%d", info->icount.txabort);
1266 if (info->icount.rxshort)
1267 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1268 if (info->icount.rxlong)
1269 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1270 if (info->icount.rxover)
1271 seq_printf(m, " rxover:%d", info->icount.rxover);
1272 if (info->icount.rxcrc)
1273 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1274 } else {
1275 seq_printf(m, "\tASYNC tx:%d rx:%d",
1276 info->icount.tx, info->icount.rx);
1277 if (info->icount.frame)
1278 seq_printf(m, " fe:%d", info->icount.frame);
1279 if (info->icount.parity)
1280 seq_printf(m, " pe:%d", info->icount.parity);
1281 if (info->icount.brk)
1282 seq_printf(m, " brk:%d", info->icount.brk);
1283 if (info->icount.overrun)
1284 seq_printf(m, " oe:%d", info->icount.overrun);
1285 }
1286
1287 /* Append serial signal status to end */
1288 seq_printf(m, " %s\n", stat_buf+1);
1289
1290 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1291 info->tx_active,info->bh_requested,info->bh_running,
1292 info->pending_bh);
1293}
1294
1295/* Called to print information about devices
1296 */
1297static int synclink_gt_proc_show(struct seq_file *m, void *v)
1298{
1299 struct slgt_info *info;
1300
1301 seq_puts(m, "synclink_gt driver\n");
1302
1303 info = slgt_device_list;
1304 while( info ) {
1305 line_info(m, info);
1306 info = info->next_device;
1307 }
1308 return 0;
1309}
1310
1311/*
1312 * return count of bytes in transmit buffer
1313 */
1314static int chars_in_buffer(struct tty_struct *tty)
1315{
1316 struct slgt_info *info = tty->driver_data;
1317 int count;
1318 if (sanity_check(info, tty->name, "chars_in_buffer"))
1319 return 0;
1320 count = tbuf_bytes(info);
1321 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1322 return count;
1323}
1324
1325/*
1326 * signal remote device to throttle send data (our receive data)
1327 */
1328static void throttle(struct tty_struct * tty)
1329{
1330 struct slgt_info *info = tty->driver_data;
1331 unsigned long flags;
1332
1333 if (sanity_check(info, tty->name, "throttle"))
1334 return;
1335 DBGINFO(("%s throttle\n", info->device_name));
1336 if (I_IXOFF(tty))
1337 send_xchar(tty, STOP_CHAR(tty));
1338 if (C_CRTSCTS(tty)) {
1339 spin_lock_irqsave(&info->lock,flags);
1340 info->signals &= ~SerialSignal_RTS;
1341 set_signals(info);
1342 spin_unlock_irqrestore(&info->lock,flags);
1343 }
1344}
1345
1346/*
1347 * signal remote device to stop throttling send data (our receive data)
1348 */
1349static void unthrottle(struct tty_struct * tty)
1350{
1351 struct slgt_info *info = tty->driver_data;
1352 unsigned long flags;
1353
1354 if (sanity_check(info, tty->name, "unthrottle"))
1355 return;
1356 DBGINFO(("%s unthrottle\n", info->device_name));
1357 if (I_IXOFF(tty)) {
1358 if (info->x_char)
1359 info->x_char = 0;
1360 else
1361 send_xchar(tty, START_CHAR(tty));
1362 }
1363 if (C_CRTSCTS(tty)) {
1364 spin_lock_irqsave(&info->lock,flags);
1365 info->signals |= SerialSignal_RTS;
1366 set_signals(info);
1367 spin_unlock_irqrestore(&info->lock,flags);
1368 }
1369}
1370
1371/*
1372 * set or clear transmit break condition
1373 * break_state -1=set break condition, 0=clear
1374 */
1375static int set_break(struct tty_struct *tty, int break_state)
1376{
1377 struct slgt_info *info = tty->driver_data;
1378 unsigned short value;
1379 unsigned long flags;
1380
1381 if (sanity_check(info, tty->name, "set_break"))
1382 return -EINVAL;
1383 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1384
1385 spin_lock_irqsave(&info->lock,flags);
1386 value = rd_reg16(info, TCR);
1387 if (break_state == -1)
1388 value |= BIT6;
1389 else
1390 value &= ~BIT6;
1391 wr_reg16(info, TCR, value);
1392 spin_unlock_irqrestore(&info->lock,flags);
1393 return 0;
1394}
1395
1396#if SYNCLINK_GENERIC_HDLC
1397
1398/**
1399 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1400 * set encoding and frame check sequence (FCS) options
1401 *
1402 * dev pointer to network device structure
1403 * encoding serial encoding setting
1404 * parity FCS setting
1405 *
1406 * returns 0 if success, otherwise error code
1407 */
1408static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1409 unsigned short parity)
1410{
1411 struct slgt_info *info = dev_to_port(dev);
1412 unsigned char new_encoding;
1413 unsigned short new_crctype;
1414
1415 /* return error if TTY interface open */
1416 if (info->port.count)
1417 return -EBUSY;
1418
1419 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1420
1421 switch (encoding)
1422 {
1423 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1424 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1425 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1426 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1427 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1428 default: return -EINVAL;
1429 }
1430
1431 switch (parity)
1432 {
1433 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1434 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1435 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1436 default: return -EINVAL;
1437 }
1438
1439 info->params.encoding = new_encoding;
1440 info->params.crc_type = new_crctype;
1441
1442 /* if network interface up, reprogram hardware */
1443 if (info->netcount)
1444 program_hw(info);
1445
1446 return 0;
1447}
1448
1449/**
1450 * called by generic HDLC layer to send frame
1451 *
1452 * skb socket buffer containing HDLC frame
1453 * dev pointer to network device structure
1454 */
1455static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1456 struct net_device *dev)
1457{
1458 struct slgt_info *info = dev_to_port(dev);
1459 unsigned long flags;
1460
1461 DBGINFO(("%s hdlc_xmit\n", dev->name));
1462
1463 if (!skb->len)
1464 return NETDEV_TX_OK;
1465
1466 /* stop sending until this frame completes */
1467 netif_stop_queue(dev);
1468
1469 /* update network statistics */
1470 dev->stats.tx_packets++;
1471 dev->stats.tx_bytes += skb->len;
1472
1473 /* save start time for transmit timeout detection */
1474 netif_trans_update(dev);
1475
1476 spin_lock_irqsave(&info->lock, flags);
1477 tx_load(info, skb->data, skb->len);
1478 spin_unlock_irqrestore(&info->lock, flags);
1479
1480 /* done with socket buffer, so free it */
1481 dev_kfree_skb(skb);
1482
1483 return NETDEV_TX_OK;
1484}
1485
1486/**
1487 * called by network layer when interface enabled
1488 * claim resources and initialize hardware
1489 *
1490 * dev pointer to network device structure
1491 *
1492 * returns 0 if success, otherwise error code
1493 */
1494static int hdlcdev_open(struct net_device *dev)
1495{
1496 struct slgt_info *info = dev_to_port(dev);
1497 int rc;
1498 unsigned long flags;
1499
1500 if (!try_module_get(THIS_MODULE))
1501 return -EBUSY;
1502
1503 DBGINFO(("%s hdlcdev_open\n", dev->name));
1504
1505 /* generic HDLC layer open processing */
1506 rc = hdlc_open(dev);
1507 if (rc)
1508 return rc;
1509
1510 /* arbitrate between network and tty opens */
1511 spin_lock_irqsave(&info->netlock, flags);
1512 if (info->port.count != 0 || info->netcount != 0) {
1513 DBGINFO(("%s hdlc_open busy\n", dev->name));
1514 spin_unlock_irqrestore(&info->netlock, flags);
1515 return -EBUSY;
1516 }
1517 info->netcount=1;
1518 spin_unlock_irqrestore(&info->netlock, flags);
1519
1520 /* claim resources and init adapter */
1521 if ((rc = startup(info)) != 0) {
1522 spin_lock_irqsave(&info->netlock, flags);
1523 info->netcount=0;
1524 spin_unlock_irqrestore(&info->netlock, flags);
1525 return rc;
1526 }
1527
1528 /* assert RTS and DTR, apply hardware settings */
1529 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1530 program_hw(info);
1531
1532 /* enable network layer transmit */
1533 netif_trans_update(dev);
1534 netif_start_queue(dev);
1535
1536 /* inform generic HDLC layer of current DCD status */
1537 spin_lock_irqsave(&info->lock, flags);
1538 get_signals(info);
1539 spin_unlock_irqrestore(&info->lock, flags);
1540 if (info->signals & SerialSignal_DCD)
1541 netif_carrier_on(dev);
1542 else
1543 netif_carrier_off(dev);
1544 return 0;
1545}
1546
1547/**
1548 * called by network layer when interface is disabled
1549 * shutdown hardware and release resources
1550 *
1551 * dev pointer to network device structure
1552 *
1553 * returns 0 if success, otherwise error code
1554 */
1555static int hdlcdev_close(struct net_device *dev)
1556{
1557 struct slgt_info *info = dev_to_port(dev);
1558 unsigned long flags;
1559
1560 DBGINFO(("%s hdlcdev_close\n", dev->name));
1561
1562 netif_stop_queue(dev);
1563
1564 /* shutdown adapter and release resources */
1565 shutdown(info);
1566
1567 hdlc_close(dev);
1568
1569 spin_lock_irqsave(&info->netlock, flags);
1570 info->netcount=0;
1571 spin_unlock_irqrestore(&info->netlock, flags);
1572
1573 module_put(THIS_MODULE);
1574 return 0;
1575}
1576
1577/**
1578 * called by network layer to process IOCTL call to network device
1579 *
1580 * dev pointer to network device structure
1581 * ifr pointer to network interface request structure
1582 * cmd IOCTL command code
1583 *
1584 * returns 0 if success, otherwise error code
1585 */
1586static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1587{
1588 const size_t size = sizeof(sync_serial_settings);
1589 sync_serial_settings new_line;
1590 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1591 struct slgt_info *info = dev_to_port(dev);
1592 unsigned int flags;
1593
1594 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1595
1596 /* return error if TTY interface open */
1597 if (info->port.count)
1598 return -EBUSY;
1599
1600 if (cmd != SIOCWANDEV)
1601 return hdlc_ioctl(dev, ifr, cmd);
1602
1603 memset(&new_line, 0, sizeof(new_line));
1604
1605 switch(ifr->ifr_settings.type) {
1606 case IF_GET_IFACE: /* return current sync_serial_settings */
1607
1608 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1609 if (ifr->ifr_settings.size < size) {
1610 ifr->ifr_settings.size = size; /* data size wanted */
1611 return -ENOBUFS;
1612 }
1613
1614 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1615 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1616 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1617 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1618
1619 switch (flags){
1620 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1621 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1622 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1623 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1624 default: new_line.clock_type = CLOCK_DEFAULT;
1625 }
1626
1627 new_line.clock_rate = info->params.clock_speed;
1628 new_line.loopback = info->params.loopback ? 1:0;
1629
1630 if (copy_to_user(line, &new_line, size))
1631 return -EFAULT;
1632 return 0;
1633
1634 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1635
1636 if(!capable(CAP_NET_ADMIN))
1637 return -EPERM;
1638 if (copy_from_user(&new_line, line, size))
1639 return -EFAULT;
1640
1641 switch (new_line.clock_type)
1642 {
1643 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1644 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1645 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1646 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1647 case CLOCK_DEFAULT: flags = info->params.flags &
1648 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1649 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1650 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1651 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1652 default: return -EINVAL;
1653 }
1654
1655 if (new_line.loopback != 0 && new_line.loopback != 1)
1656 return -EINVAL;
1657
1658 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1659 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1660 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1661 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1662 info->params.flags |= flags;
1663
1664 info->params.loopback = new_line.loopback;
1665
1666 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1667 info->params.clock_speed = new_line.clock_rate;
1668 else
1669 info->params.clock_speed = 0;
1670
1671 /* if network interface up, reprogram hardware */
1672 if (info->netcount)
1673 program_hw(info);
1674 return 0;
1675
1676 default:
1677 return hdlc_ioctl(dev, ifr, cmd);
1678 }
1679}
1680
1681/**
1682 * called by network layer when transmit timeout is detected
1683 *
1684 * dev pointer to network device structure
1685 */
1686static void hdlcdev_tx_timeout(struct net_device *dev)
1687{
1688 struct slgt_info *info = dev_to_port(dev);
1689 unsigned long flags;
1690
1691 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1692
1693 dev->stats.tx_errors++;
1694 dev->stats.tx_aborted_errors++;
1695
1696 spin_lock_irqsave(&info->lock,flags);
1697 tx_stop(info);
1698 spin_unlock_irqrestore(&info->lock,flags);
1699
1700 netif_wake_queue(dev);
1701}
1702
1703/**
1704 * called by device driver when transmit completes
1705 * reenable network layer transmit if stopped
1706 *
1707 * info pointer to device instance information
1708 */
1709static void hdlcdev_tx_done(struct slgt_info *info)
1710{
1711 if (netif_queue_stopped(info->netdev))
1712 netif_wake_queue(info->netdev);
1713}
1714
1715/**
1716 * called by device driver when frame received
1717 * pass frame to network layer
1718 *
1719 * info pointer to device instance information
1720 * buf pointer to buffer contianing frame data
1721 * size count of data bytes in buf
1722 */
1723static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1724{
1725 struct sk_buff *skb = dev_alloc_skb(size);
1726 struct net_device *dev = info->netdev;
1727
1728 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1729
1730 if (skb == NULL) {
1731 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1732 dev->stats.rx_dropped++;
1733 return;
1734 }
1735
1736 skb_put_data(skb, buf, size);
1737
1738 skb->protocol = hdlc_type_trans(skb, dev);
1739
1740 dev->stats.rx_packets++;
1741 dev->stats.rx_bytes += size;
1742
1743 netif_rx(skb);
1744}
1745
1746static const struct net_device_ops hdlcdev_ops = {
1747 .ndo_open = hdlcdev_open,
1748 .ndo_stop = hdlcdev_close,
1749 .ndo_start_xmit = hdlc_start_xmit,
1750 .ndo_do_ioctl = hdlcdev_ioctl,
1751 .ndo_tx_timeout = hdlcdev_tx_timeout,
1752};
1753
1754/**
1755 * called by device driver when adding device instance
1756 * do generic HDLC initialization
1757 *
1758 * info pointer to device instance information
1759 *
1760 * returns 0 if success, otherwise error code
1761 */
1762static int hdlcdev_init(struct slgt_info *info)
1763{
1764 int rc;
1765 struct net_device *dev;
1766 hdlc_device *hdlc;
1767
1768 /* allocate and initialize network and HDLC layer objects */
1769
1770 dev = alloc_hdlcdev(info);
1771 if (!dev) {
1772 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1773 return -ENOMEM;
1774 }
1775
1776 /* for network layer reporting purposes only */
1777 dev->mem_start = info->phys_reg_addr;
1778 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1779 dev->irq = info->irq_level;
1780
1781 /* network layer callbacks and settings */
1782 dev->netdev_ops = &hdlcdev_ops;
1783 dev->watchdog_timeo = 10 * HZ;
1784 dev->tx_queue_len = 50;
1785
1786 /* generic HDLC layer callbacks and settings */
1787 hdlc = dev_to_hdlc(dev);
1788 hdlc->attach = hdlcdev_attach;
1789 hdlc->xmit = hdlcdev_xmit;
1790
1791 /* register objects with HDLC layer */
1792 rc = register_hdlc_device(dev);
1793 if (rc) {
1794 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1795 free_netdev(dev);
1796 return rc;
1797 }
1798
1799 info->netdev = dev;
1800 return 0;
1801}
1802
1803/**
1804 * called by device driver when removing device instance
1805 * do generic HDLC cleanup
1806 *
1807 * info pointer to device instance information
1808 */
1809static void hdlcdev_exit(struct slgt_info *info)
1810{
1811 unregister_hdlc_device(info->netdev);
1812 free_netdev(info->netdev);
1813 info->netdev = NULL;
1814}
1815
1816#endif /* ifdef CONFIG_HDLC */
1817
1818/*
1819 * get async data from rx DMA buffers
1820 */
1821static void rx_async(struct slgt_info *info)
1822{
1823 struct mgsl_icount *icount = &info->icount;
1824 unsigned int start, end;
1825 unsigned char *p;
1826 unsigned char status;
1827 struct slgt_desc *bufs = info->rbufs;
1828 int i, count;
1829 int chars = 0;
1830 int stat;
1831 unsigned char ch;
1832
1833 start = end = info->rbuf_current;
1834
1835 while(desc_complete(bufs[end])) {
1836 count = desc_count(bufs[end]) - info->rbuf_index;
1837 p = bufs[end].buf + info->rbuf_index;
1838
1839 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1840 DBGDATA(info, p, count, "rx");
1841
1842 for(i=0 ; i < count; i+=2, p+=2) {
1843 ch = *p;
1844 icount->rx++;
1845
1846 stat = 0;
1847
1848 status = *(p + 1) & (BIT1 + BIT0);
1849 if (status) {
1850 if (status & BIT1)
1851 icount->parity++;
1852 else if (status & BIT0)
1853 icount->frame++;
1854 /* discard char if tty control flags say so */
1855 if (status & info->ignore_status_mask)
1856 continue;
1857 if (status & BIT1)
1858 stat = TTY_PARITY;
1859 else if (status & BIT0)
1860 stat = TTY_FRAME;
1861 }
1862 tty_insert_flip_char(&info->port, ch, stat);
1863 chars++;
1864 }
1865
1866 if (i < count) {
1867 /* receive buffer not completed */
1868 info->rbuf_index += i;
1869 mod_timer(&info->rx_timer, jiffies + 1);
1870 break;
1871 }
1872
1873 info->rbuf_index = 0;
1874 free_rbufs(info, end, end);
1875
1876 if (++end == info->rbuf_count)
1877 end = 0;
1878
1879 /* if entire list searched then no frame available */
1880 if (end == start)
1881 break;
1882 }
1883
1884 if (chars)
1885 tty_flip_buffer_push(&info->port);
1886}
1887
1888/*
1889 * return next bottom half action to perform
1890 */
1891static int bh_action(struct slgt_info *info)
1892{
1893 unsigned long flags;
1894 int rc;
1895
1896 spin_lock_irqsave(&info->lock,flags);
1897
1898 if (info->pending_bh & BH_RECEIVE) {
1899 info->pending_bh &= ~BH_RECEIVE;
1900 rc = BH_RECEIVE;
1901 } else if (info->pending_bh & BH_TRANSMIT) {
1902 info->pending_bh &= ~BH_TRANSMIT;
1903 rc = BH_TRANSMIT;
1904 } else if (info->pending_bh & BH_STATUS) {
1905 info->pending_bh &= ~BH_STATUS;
1906 rc = BH_STATUS;
1907 } else {
1908 /* Mark BH routine as complete */
1909 info->bh_running = false;
1910 info->bh_requested = false;
1911 rc = 0;
1912 }
1913
1914 spin_unlock_irqrestore(&info->lock,flags);
1915
1916 return rc;
1917}
1918
1919/*
1920 * perform bottom half processing
1921 */
1922static void bh_handler(struct work_struct *work)
1923{
1924 struct slgt_info *info = container_of(work, struct slgt_info, task);
1925 int action;
1926
1927 info->bh_running = true;
1928
1929 while((action = bh_action(info))) {
1930 switch (action) {
1931 case BH_RECEIVE:
1932 DBGBH(("%s bh receive\n", info->device_name));
1933 switch(info->params.mode) {
1934 case MGSL_MODE_ASYNC:
1935 rx_async(info);
1936 break;
1937 case MGSL_MODE_HDLC:
1938 while(rx_get_frame(info));
1939 break;
1940 case MGSL_MODE_RAW:
1941 case MGSL_MODE_MONOSYNC:
1942 case MGSL_MODE_BISYNC:
1943 case MGSL_MODE_XSYNC:
1944 while(rx_get_buf(info));
1945 break;
1946 }
1947 /* restart receiver if rx DMA buffers exhausted */
1948 if (info->rx_restart)
1949 rx_start(info);
1950 break;
1951 case BH_TRANSMIT:
1952 bh_transmit(info);
1953 break;
1954 case BH_STATUS:
1955 DBGBH(("%s bh status\n", info->device_name));
1956 info->ri_chkcount = 0;
1957 info->dsr_chkcount = 0;
1958 info->dcd_chkcount = 0;
1959 info->cts_chkcount = 0;
1960 break;
1961 default:
1962 DBGBH(("%s unknown action\n", info->device_name));
1963 break;
1964 }
1965 }
1966 DBGBH(("%s bh_handler exit\n", info->device_name));
1967}
1968
1969static void bh_transmit(struct slgt_info *info)
1970{
1971 struct tty_struct *tty = info->port.tty;
1972
1973 DBGBH(("%s bh_transmit\n", info->device_name));
1974 if (tty)
1975 tty_wakeup(tty);
1976}
1977
1978static void dsr_change(struct slgt_info *info, unsigned short status)
1979{
1980 if (status & BIT3) {
1981 info->signals |= SerialSignal_DSR;
1982 info->input_signal_events.dsr_up++;
1983 } else {
1984 info->signals &= ~SerialSignal_DSR;
1985 info->input_signal_events.dsr_down++;
1986 }
1987 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1988 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1989 slgt_irq_off(info, IRQ_DSR);
1990 return;
1991 }
1992 info->icount.dsr++;
1993 wake_up_interruptible(&info->status_event_wait_q);
1994 wake_up_interruptible(&info->event_wait_q);
1995 info->pending_bh |= BH_STATUS;
1996}
1997
1998static void cts_change(struct slgt_info *info, unsigned short status)
1999{
2000 if (status & BIT2) {
2001 info->signals |= SerialSignal_CTS;
2002 info->input_signal_events.cts_up++;
2003 } else {
2004 info->signals &= ~SerialSignal_CTS;
2005 info->input_signal_events.cts_down++;
2006 }
2007 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2008 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2009 slgt_irq_off(info, IRQ_CTS);
2010 return;
2011 }
2012 info->icount.cts++;
2013 wake_up_interruptible(&info->status_event_wait_q);
2014 wake_up_interruptible(&info->event_wait_q);
2015 info->pending_bh |= BH_STATUS;
2016
2017 if (tty_port_cts_enabled(&info->port)) {
2018 if (info->port.tty) {
2019 if (info->port.tty->hw_stopped) {
2020 if (info->signals & SerialSignal_CTS) {
2021 info->port.tty->hw_stopped = 0;
2022 info->pending_bh |= BH_TRANSMIT;
2023 return;
2024 }
2025 } else {
2026 if (!(info->signals & SerialSignal_CTS))
2027 info->port.tty->hw_stopped = 1;
2028 }
2029 }
2030 }
2031}
2032
2033static void dcd_change(struct slgt_info *info, unsigned short status)
2034{
2035 if (status & BIT1) {
2036 info->signals |= SerialSignal_DCD;
2037 info->input_signal_events.dcd_up++;
2038 } else {
2039 info->signals &= ~SerialSignal_DCD;
2040 info->input_signal_events.dcd_down++;
2041 }
2042 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2043 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2044 slgt_irq_off(info, IRQ_DCD);
2045 return;
2046 }
2047 info->icount.dcd++;
2048#if SYNCLINK_GENERIC_HDLC
2049 if (info->netcount) {
2050 if (info->signals & SerialSignal_DCD)
2051 netif_carrier_on(info->netdev);
2052 else
2053 netif_carrier_off(info->netdev);
2054 }
2055#endif
2056 wake_up_interruptible(&info->status_event_wait_q);
2057 wake_up_interruptible(&info->event_wait_q);
2058 info->pending_bh |= BH_STATUS;
2059
2060 if (tty_port_check_carrier(&info->port)) {
2061 if (info->signals & SerialSignal_DCD)
2062 wake_up_interruptible(&info->port.open_wait);
2063 else {
2064 if (info->port.tty)
2065 tty_hangup(info->port.tty);
2066 }
2067 }
2068}
2069
2070static void ri_change(struct slgt_info *info, unsigned short status)
2071{
2072 if (status & BIT0) {
2073 info->signals |= SerialSignal_RI;
2074 info->input_signal_events.ri_up++;
2075 } else {
2076 info->signals &= ~SerialSignal_RI;
2077 info->input_signal_events.ri_down++;
2078 }
2079 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2080 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2081 slgt_irq_off(info, IRQ_RI);
2082 return;
2083 }
2084 info->icount.rng++;
2085 wake_up_interruptible(&info->status_event_wait_q);
2086 wake_up_interruptible(&info->event_wait_q);
2087 info->pending_bh |= BH_STATUS;
2088}
2089
2090static void isr_rxdata(struct slgt_info *info)
2091{
2092 unsigned int count = info->rbuf_fill_count;
2093 unsigned int i = info->rbuf_fill_index;
2094 unsigned short reg;
2095
2096 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2097 reg = rd_reg16(info, RDR);
2098 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2099 if (desc_complete(info->rbufs[i])) {
2100 /* all buffers full */
2101 rx_stop(info);
2102 info->rx_restart = 1;
2103 continue;
2104 }
2105 info->rbufs[i].buf[count++] = (unsigned char)reg;
2106 /* async mode saves status byte to buffer for each data byte */
2107 if (info->params.mode == MGSL_MODE_ASYNC)
2108 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2109 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2110 /* buffer full or end of frame */
2111 set_desc_count(info->rbufs[i], count);
2112 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2113 info->rbuf_fill_count = count = 0;
2114 if (++i == info->rbuf_count)
2115 i = 0;
2116 info->pending_bh |= BH_RECEIVE;
2117 }
2118 }
2119
2120 info->rbuf_fill_index = i;
2121 info->rbuf_fill_count = count;
2122}
2123
2124static void isr_serial(struct slgt_info *info)
2125{
2126 unsigned short status = rd_reg16(info, SSR);
2127
2128 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2129
2130 wr_reg16(info, SSR, status); /* clear pending */
2131
2132 info->irq_occurred = true;
2133
2134 if (info->params.mode == MGSL_MODE_ASYNC) {
2135 if (status & IRQ_TXIDLE) {
2136 if (info->tx_active)
2137 isr_txeom(info, status);
2138 }
2139 if (info->rx_pio && (status & IRQ_RXDATA))
2140 isr_rxdata(info);
2141 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2142 info->icount.brk++;
2143 /* process break detection if tty control allows */
2144 if (info->port.tty) {
2145 if (!(status & info->ignore_status_mask)) {
2146 if (info->read_status_mask & MASK_BREAK) {
2147 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2148 if (info->port.flags & ASYNC_SAK)
2149 do_SAK(info->port.tty);
2150 }
2151 }
2152 }
2153 }
2154 } else {
2155 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2156 isr_txeom(info, status);
2157 if (info->rx_pio && (status & IRQ_RXDATA))
2158 isr_rxdata(info);
2159 if (status & IRQ_RXIDLE) {
2160 if (status & RXIDLE)
2161 info->icount.rxidle++;
2162 else
2163 info->icount.exithunt++;
2164 wake_up_interruptible(&info->event_wait_q);
2165 }
2166
2167 if (status & IRQ_RXOVER)
2168 rx_start(info);
2169 }
2170
2171 if (status & IRQ_DSR)
2172 dsr_change(info, status);
2173 if (status & IRQ_CTS)
2174 cts_change(info, status);
2175 if (status & IRQ_DCD)
2176 dcd_change(info, status);
2177 if (status & IRQ_RI)
2178 ri_change(info, status);
2179}
2180
2181static void isr_rdma(struct slgt_info *info)
2182{
2183 unsigned int status = rd_reg32(info, RDCSR);
2184
2185 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2186
2187 /* RDCSR (rx DMA control/status)
2188 *
2189 * 31..07 reserved
2190 * 06 save status byte to DMA buffer
2191 * 05 error
2192 * 04 eol (end of list)
2193 * 03 eob (end of buffer)
2194 * 02 IRQ enable
2195 * 01 reset
2196 * 00 enable
2197 */
2198 wr_reg32(info, RDCSR, status); /* clear pending */
2199
2200 if (status & (BIT5 + BIT4)) {
2201 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2202 info->rx_restart = true;
2203 }
2204 info->pending_bh |= BH_RECEIVE;
2205}
2206
2207static void isr_tdma(struct slgt_info *info)
2208{
2209 unsigned int status = rd_reg32(info, TDCSR);
2210
2211 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2212
2213 /* TDCSR (tx DMA control/status)
2214 *
2215 * 31..06 reserved
2216 * 05 error
2217 * 04 eol (end of list)
2218 * 03 eob (end of buffer)
2219 * 02 IRQ enable
2220 * 01 reset
2221 * 00 enable
2222 */
2223 wr_reg32(info, TDCSR, status); /* clear pending */
2224
2225 if (status & (BIT5 + BIT4 + BIT3)) {
2226 // another transmit buffer has completed
2227 // run bottom half to get more send data from user
2228 info->pending_bh |= BH_TRANSMIT;
2229 }
2230}
2231
2232/*
2233 * return true if there are unsent tx DMA buffers, otherwise false
2234 *
2235 * if there are unsent buffers then info->tbuf_start
2236 * is set to index of first unsent buffer
2237 */
2238static bool unsent_tbufs(struct slgt_info *info)
2239{
2240 unsigned int i = info->tbuf_current;
2241 bool rc = false;
2242
2243 /*
2244 * search backwards from last loaded buffer (precedes tbuf_current)
2245 * for first unsent buffer (desc_count > 0)
2246 */
2247
2248 do {
2249 if (i)
2250 i--;
2251 else
2252 i = info->tbuf_count - 1;
2253 if (!desc_count(info->tbufs[i]))
2254 break;
2255 info->tbuf_start = i;
2256 rc = true;
2257 } while (i != info->tbuf_current);
2258
2259 return rc;
2260}
2261
2262static void isr_txeom(struct slgt_info *info, unsigned short status)
2263{
2264 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2265
2266 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2267 tdma_reset(info);
2268 if (status & IRQ_TXUNDER) {
2269 unsigned short val = rd_reg16(info, TCR);
2270 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2271 wr_reg16(info, TCR, val); /* clear reset bit */
2272 }
2273
2274 if (info->tx_active) {
2275 if (info->params.mode != MGSL_MODE_ASYNC) {
2276 if (status & IRQ_TXUNDER)
2277 info->icount.txunder++;
2278 else if (status & IRQ_TXIDLE)
2279 info->icount.txok++;
2280 }
2281
2282 if (unsent_tbufs(info)) {
2283 tx_start(info);
2284 update_tx_timer(info);
2285 return;
2286 }
2287 info->tx_active = false;
2288
2289 del_timer(&info->tx_timer);
2290
2291 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2292 info->signals &= ~SerialSignal_RTS;
2293 info->drop_rts_on_tx_done = false;
2294 set_signals(info);
2295 }
2296
2297#if SYNCLINK_GENERIC_HDLC
2298 if (info->netcount)
2299 hdlcdev_tx_done(info);
2300 else
2301#endif
2302 {
2303 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2304 tx_stop(info);
2305 return;
2306 }
2307 info->pending_bh |= BH_TRANSMIT;
2308 }
2309 }
2310}
2311
2312static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2313{
2314 struct cond_wait *w, *prev;
2315
2316 /* wake processes waiting for specific transitions */
2317 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2318 if (w->data & changed) {
2319 w->data = state;
2320 wake_up_interruptible(&w->q);
2321 if (prev != NULL)
2322 prev->next = w->next;
2323 else
2324 info->gpio_wait_q = w->next;
2325 } else
2326 prev = w;
2327 }
2328}
2329
2330/* interrupt service routine
2331 *
2332 * irq interrupt number
2333 * dev_id device ID supplied during interrupt registration
2334 */
2335static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2336{
2337 struct slgt_info *info = dev_id;
2338 unsigned int gsr;
2339 unsigned int i;
2340
2341 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2342
2343 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2344 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2345 info->irq_occurred = true;
2346 for(i=0; i < info->port_count ; i++) {
2347 if (info->port_array[i] == NULL)
2348 continue;
2349 spin_lock(&info->port_array[i]->lock);
2350 if (gsr & (BIT8 << i))
2351 isr_serial(info->port_array[i]);
2352 if (gsr & (BIT16 << (i*2)))
2353 isr_rdma(info->port_array[i]);
2354 if (gsr & (BIT17 << (i*2)))
2355 isr_tdma(info->port_array[i]);
2356 spin_unlock(&info->port_array[i]->lock);
2357 }
2358 }
2359
2360 if (info->gpio_present) {
2361 unsigned int state;
2362 unsigned int changed;
2363 spin_lock(&info->lock);
2364 while ((changed = rd_reg32(info, IOSR)) != 0) {
2365 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2366 /* read latched state of GPIO signals */
2367 state = rd_reg32(info, IOVR);
2368 /* clear pending GPIO interrupt bits */
2369 wr_reg32(info, IOSR, changed);
2370 for (i=0 ; i < info->port_count ; i++) {
2371 if (info->port_array[i] != NULL)
2372 isr_gpio(info->port_array[i], changed, state);
2373 }
2374 }
2375 spin_unlock(&info->lock);
2376 }
2377
2378 for(i=0; i < info->port_count ; i++) {
2379 struct slgt_info *port = info->port_array[i];
2380 if (port == NULL)
2381 continue;
2382 spin_lock(&port->lock);
2383 if ((port->port.count || port->netcount) &&
2384 port->pending_bh && !port->bh_running &&
2385 !port->bh_requested) {
2386 DBGISR(("%s bh queued\n", port->device_name));
2387 schedule_work(&port->task);
2388 port->bh_requested = true;
2389 }
2390 spin_unlock(&port->lock);
2391 }
2392
2393 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2394 return IRQ_HANDLED;
2395}
2396
2397static int startup(struct slgt_info *info)
2398{
2399 DBGINFO(("%s startup\n", info->device_name));
2400
2401 if (tty_port_initialized(&info->port))
2402 return 0;
2403
2404 if (!info->tx_buf) {
2405 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2406 if (!info->tx_buf) {
2407 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2408 return -ENOMEM;
2409 }
2410 }
2411
2412 info->pending_bh = 0;
2413
2414 memset(&info->icount, 0, sizeof(info->icount));
2415
2416 /* program hardware for current parameters */
2417 change_params(info);
2418
2419 if (info->port.tty)
2420 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2421
2422 tty_port_set_initialized(&info->port, 1);
2423
2424 return 0;
2425}
2426
2427/*
2428 * called by close() and hangup() to shutdown hardware
2429 */
2430static void shutdown(struct slgt_info *info)
2431{
2432 unsigned long flags;
2433
2434 if (!tty_port_initialized(&info->port))
2435 return;
2436
2437 DBGINFO(("%s shutdown\n", info->device_name));
2438
2439 /* clear status wait queue because status changes */
2440 /* can't happen after shutting down the hardware */
2441 wake_up_interruptible(&info->status_event_wait_q);
2442 wake_up_interruptible(&info->event_wait_q);
2443
2444 del_timer_sync(&info->tx_timer);
2445 del_timer_sync(&info->rx_timer);
2446
2447 kfree(info->tx_buf);
2448 info->tx_buf = NULL;
2449
2450 spin_lock_irqsave(&info->lock,flags);
2451
2452 tx_stop(info);
2453 rx_stop(info);
2454
2455 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2456
2457 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2458 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2459 set_signals(info);
2460 }
2461
2462 flush_cond_wait(&info->gpio_wait_q);
2463
2464 spin_unlock_irqrestore(&info->lock,flags);
2465
2466 if (info->port.tty)
2467 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2468
2469 tty_port_set_initialized(&info->port, 0);
2470}
2471
2472static void program_hw(struct slgt_info *info)
2473{
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&info->lock,flags);
2477
2478 rx_stop(info);
2479 tx_stop(info);
2480
2481 if (info->params.mode != MGSL_MODE_ASYNC ||
2482 info->netcount)
2483 sync_mode(info);
2484 else
2485 async_mode(info);
2486
2487 set_signals(info);
2488
2489 info->dcd_chkcount = 0;
2490 info->cts_chkcount = 0;
2491 info->ri_chkcount = 0;
2492 info->dsr_chkcount = 0;
2493
2494 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2495 get_signals(info);
2496
2497 if (info->netcount ||
2498 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2499 rx_start(info);
2500
2501 spin_unlock_irqrestore(&info->lock,flags);
2502}
2503
2504/*
2505 * reconfigure adapter based on new parameters
2506 */
2507static void change_params(struct slgt_info *info)
2508{
2509 unsigned cflag;
2510 int bits_per_char;
2511
2512 if (!info->port.tty)
2513 return;
2514 DBGINFO(("%s change_params\n", info->device_name));
2515
2516 cflag = info->port.tty->termios.c_cflag;
2517
2518 /* if B0 rate (hangup) specified then negate RTS and DTR */
2519 /* otherwise assert RTS and DTR */
2520 if (cflag & CBAUD)
2521 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2522 else
2523 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2524
2525 /* byte size and parity */
2526
2527 switch (cflag & CSIZE) {
2528 case CS5: info->params.data_bits = 5; break;
2529 case CS6: info->params.data_bits = 6; break;
2530 case CS7: info->params.data_bits = 7; break;
2531 case CS8: info->params.data_bits = 8; break;
2532 default: info->params.data_bits = 7; break;
2533 }
2534
2535 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2536
2537 if (cflag & PARENB)
2538 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2539 else
2540 info->params.parity = ASYNC_PARITY_NONE;
2541
2542 /* calculate number of jiffies to transmit a full
2543 * FIFO (32 bytes) at specified data rate
2544 */
2545 bits_per_char = info->params.data_bits +
2546 info->params.stop_bits + 1;
2547
2548 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2549
2550 if (info->params.data_rate) {
2551 info->timeout = (32*HZ*bits_per_char) /
2552 info->params.data_rate;
2553 }
2554 info->timeout += HZ/50; /* Add .02 seconds of slop */
2555
2556 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2557 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2558
2559 /* process tty input control flags */
2560
2561 info->read_status_mask = IRQ_RXOVER;
2562 if (I_INPCK(info->port.tty))
2563 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2564 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2565 info->read_status_mask |= MASK_BREAK;
2566 if (I_IGNPAR(info->port.tty))
2567 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2568 if (I_IGNBRK(info->port.tty)) {
2569 info->ignore_status_mask |= MASK_BREAK;
2570 /* If ignoring parity and break indicators, ignore
2571 * overruns too. (For real raw support).
2572 */
2573 if (I_IGNPAR(info->port.tty))
2574 info->ignore_status_mask |= MASK_OVERRUN;
2575 }
2576
2577 program_hw(info);
2578}
2579
2580static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2581{
2582 DBGINFO(("%s get_stats\n", info->device_name));
2583 if (!user_icount) {
2584 memset(&info->icount, 0, sizeof(info->icount));
2585 } else {
2586 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2587 return -EFAULT;
2588 }
2589 return 0;
2590}
2591
2592static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2593{
2594 DBGINFO(("%s get_params\n", info->device_name));
2595 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2596 return -EFAULT;
2597 return 0;
2598}
2599
2600static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2601{
2602 unsigned long flags;
2603 MGSL_PARAMS tmp_params;
2604
2605 DBGINFO(("%s set_params\n", info->device_name));
2606 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2607 return -EFAULT;
2608
2609 spin_lock_irqsave(&info->lock, flags);
2610 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2611 info->base_clock = tmp_params.clock_speed;
2612 else
2613 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2614 spin_unlock_irqrestore(&info->lock, flags);
2615
2616 program_hw(info);
2617
2618 return 0;
2619}
2620
2621static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2622{
2623 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2624 if (put_user(info->idle_mode, idle_mode))
2625 return -EFAULT;
2626 return 0;
2627}
2628
2629static int set_txidle(struct slgt_info *info, int idle_mode)
2630{
2631 unsigned long flags;
2632 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2633 spin_lock_irqsave(&info->lock,flags);
2634 info->idle_mode = idle_mode;
2635 if (info->params.mode != MGSL_MODE_ASYNC)
2636 tx_set_idle(info);
2637 spin_unlock_irqrestore(&info->lock,flags);
2638 return 0;
2639}
2640
2641static int tx_enable(struct slgt_info *info, int enable)
2642{
2643 unsigned long flags;
2644 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2645 spin_lock_irqsave(&info->lock,flags);
2646 if (enable) {
2647 if (!info->tx_enabled)
2648 tx_start(info);
2649 } else {
2650 if (info->tx_enabled)
2651 tx_stop(info);
2652 }
2653 spin_unlock_irqrestore(&info->lock,flags);
2654 return 0;
2655}
2656
2657/*
2658 * abort transmit HDLC frame
2659 */
2660static int tx_abort(struct slgt_info *info)
2661{
2662 unsigned long flags;
2663 DBGINFO(("%s tx_abort\n", info->device_name));
2664 spin_lock_irqsave(&info->lock,flags);
2665 tdma_reset(info);
2666 spin_unlock_irqrestore(&info->lock,flags);
2667 return 0;
2668}
2669
2670static int rx_enable(struct slgt_info *info, int enable)
2671{
2672 unsigned long flags;
2673 unsigned int rbuf_fill_level;
2674 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2675 spin_lock_irqsave(&info->lock,flags);
2676 /*
2677 * enable[31..16] = receive DMA buffer fill level
2678 * 0 = noop (leave fill level unchanged)
2679 * fill level must be multiple of 4 and <= buffer size
2680 */
2681 rbuf_fill_level = ((unsigned int)enable) >> 16;
2682 if (rbuf_fill_level) {
2683 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2684 spin_unlock_irqrestore(&info->lock, flags);
2685 return -EINVAL;
2686 }
2687 info->rbuf_fill_level = rbuf_fill_level;
2688 if (rbuf_fill_level < 128)
2689 info->rx_pio = 1; /* PIO mode */
2690 else
2691 info->rx_pio = 0; /* DMA mode */
2692 rx_stop(info); /* restart receiver to use new fill level */
2693 }
2694
2695 /*
2696 * enable[1..0] = receiver enable command
2697 * 0 = disable
2698 * 1 = enable
2699 * 2 = enable or force hunt mode if already enabled
2700 */
2701 enable &= 3;
2702 if (enable) {
2703 if (!info->rx_enabled)
2704 rx_start(info);
2705 else if (enable == 2) {
2706 /* force hunt mode (write 1 to RCR[3]) */
2707 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2708 }
2709 } else {
2710 if (info->rx_enabled)
2711 rx_stop(info);
2712 }
2713 spin_unlock_irqrestore(&info->lock,flags);
2714 return 0;
2715}
2716
2717/*
2718 * wait for specified event to occur
2719 */
2720static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2721{
2722 unsigned long flags;
2723 int s;
2724 int rc=0;
2725 struct mgsl_icount cprev, cnow;
2726 int events;
2727 int mask;
2728 struct _input_signal_events oldsigs, newsigs;
2729 DECLARE_WAITQUEUE(wait, current);
2730
2731 if (get_user(mask, mask_ptr))
2732 return -EFAULT;
2733
2734 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2735
2736 spin_lock_irqsave(&info->lock,flags);
2737
2738 /* return immediately if state matches requested events */
2739 get_signals(info);
2740 s = info->signals;
2741
2742 events = mask &
2743 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2744 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2745 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2746 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2747 if (events) {
2748 spin_unlock_irqrestore(&info->lock,flags);
2749 goto exit;
2750 }
2751
2752 /* save current irq counts */
2753 cprev = info->icount;
2754 oldsigs = info->input_signal_events;
2755
2756 /* enable hunt and idle irqs if needed */
2757 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2758 unsigned short val = rd_reg16(info, SCR);
2759 if (!(val & IRQ_RXIDLE))
2760 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2761 }
2762
2763 set_current_state(TASK_INTERRUPTIBLE);
2764 add_wait_queue(&info->event_wait_q, &wait);
2765
2766 spin_unlock_irqrestore(&info->lock,flags);
2767
2768 for(;;) {
2769 schedule();
2770 if (signal_pending(current)) {
2771 rc = -ERESTARTSYS;
2772 break;
2773 }
2774
2775 /* get current irq counts */
2776 spin_lock_irqsave(&info->lock,flags);
2777 cnow = info->icount;
2778 newsigs = info->input_signal_events;
2779 set_current_state(TASK_INTERRUPTIBLE);
2780 spin_unlock_irqrestore(&info->lock,flags);
2781
2782 /* if no change, wait aborted for some reason */
2783 if (newsigs.dsr_up == oldsigs.dsr_up &&
2784 newsigs.dsr_down == oldsigs.dsr_down &&
2785 newsigs.dcd_up == oldsigs.dcd_up &&
2786 newsigs.dcd_down == oldsigs.dcd_down &&
2787 newsigs.cts_up == oldsigs.cts_up &&
2788 newsigs.cts_down == oldsigs.cts_down &&
2789 newsigs.ri_up == oldsigs.ri_up &&
2790 newsigs.ri_down == oldsigs.ri_down &&
2791 cnow.exithunt == cprev.exithunt &&
2792 cnow.rxidle == cprev.rxidle) {
2793 rc = -EIO;
2794 break;
2795 }
2796
2797 events = mask &
2798 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2799 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2800 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2801 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2802 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2803 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2804 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2805 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2806 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2807 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2808 if (events)
2809 break;
2810
2811 cprev = cnow;
2812 oldsigs = newsigs;
2813 }
2814
2815 remove_wait_queue(&info->event_wait_q, &wait);
2816 set_current_state(TASK_RUNNING);
2817
2818
2819 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2820 spin_lock_irqsave(&info->lock,flags);
2821 if (!waitqueue_active(&info->event_wait_q)) {
2822 /* disable enable exit hunt mode/idle rcvd IRQs */
2823 wr_reg16(info, SCR,
2824 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2825 }
2826 spin_unlock_irqrestore(&info->lock,flags);
2827 }
2828exit:
2829 if (rc == 0)
2830 rc = put_user(events, mask_ptr);
2831 return rc;
2832}
2833
2834static int get_interface(struct slgt_info *info, int __user *if_mode)
2835{
2836 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2837 if (put_user(info->if_mode, if_mode))
2838 return -EFAULT;
2839 return 0;
2840}
2841
2842static int set_interface(struct slgt_info *info, int if_mode)
2843{
2844 unsigned long flags;
2845 unsigned short val;
2846
2847 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2848 spin_lock_irqsave(&info->lock,flags);
2849 info->if_mode = if_mode;
2850
2851 msc_set_vcr(info);
2852
2853 /* TCR (tx control) 07 1=RTS driver control */
2854 val = rd_reg16(info, TCR);
2855 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2856 val |= BIT7;
2857 else
2858 val &= ~BIT7;
2859 wr_reg16(info, TCR, val);
2860
2861 spin_unlock_irqrestore(&info->lock,flags);
2862 return 0;
2863}
2864
2865static int get_xsync(struct slgt_info *info, int __user *xsync)
2866{
2867 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2868 if (put_user(info->xsync, xsync))
2869 return -EFAULT;
2870 return 0;
2871}
2872
2873/*
2874 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2875 *
2876 * sync pattern is contained in least significant bytes of value
2877 * most significant byte of sync pattern is oldest (1st sent/detected)
2878 */
2879static int set_xsync(struct slgt_info *info, int xsync)
2880{
2881 unsigned long flags;
2882
2883 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2884 spin_lock_irqsave(&info->lock, flags);
2885 info->xsync = xsync;
2886 wr_reg32(info, XSR, xsync);
2887 spin_unlock_irqrestore(&info->lock, flags);
2888 return 0;
2889}
2890
2891static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2892{
2893 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2894 if (put_user(info->xctrl, xctrl))
2895 return -EFAULT;
2896 return 0;
2897}
2898
2899/*
2900 * set extended control options
2901 *
2902 * xctrl[31:19] reserved, must be zero
2903 * xctrl[18:17] extended sync pattern length in bytes
2904 * 00 = 1 byte in xsr[7:0]
2905 * 01 = 2 bytes in xsr[15:0]
2906 * 10 = 3 bytes in xsr[23:0]
2907 * 11 = 4 bytes in xsr[31:0]
2908 * xctrl[16] 1 = enable terminal count, 0=disabled
2909 * xctrl[15:0] receive terminal count for fixed length packets
2910 * value is count minus one (0 = 1 byte packet)
2911 * when terminal count is reached, receiver
2912 * automatically returns to hunt mode and receive
2913 * FIFO contents are flushed to DMA buffers with
2914 * end of frame (EOF) status
2915 */
2916static int set_xctrl(struct slgt_info *info, int xctrl)
2917{
2918 unsigned long flags;
2919
2920 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2921 spin_lock_irqsave(&info->lock, flags);
2922 info->xctrl = xctrl;
2923 wr_reg32(info, XCR, xctrl);
2924 spin_unlock_irqrestore(&info->lock, flags);
2925 return 0;
2926}
2927
2928/*
2929 * set general purpose IO pin state and direction
2930 *
2931 * user_gpio fields:
2932 * state each bit indicates a pin state
2933 * smask set bit indicates pin state to set
2934 * dir each bit indicates a pin direction (0=input, 1=output)
2935 * dmask set bit indicates pin direction to set
2936 */
2937static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2938{
2939 unsigned long flags;
2940 struct gpio_desc gpio;
2941 __u32 data;
2942
2943 if (!info->gpio_present)
2944 return -EINVAL;
2945 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2946 return -EFAULT;
2947 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2948 info->device_name, gpio.state, gpio.smask,
2949 gpio.dir, gpio.dmask));
2950
2951 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2952 if (gpio.dmask) {
2953 data = rd_reg32(info, IODR);
2954 data |= gpio.dmask & gpio.dir;
2955 data &= ~(gpio.dmask & ~gpio.dir);
2956 wr_reg32(info, IODR, data);
2957 }
2958 if (gpio.smask) {
2959 data = rd_reg32(info, IOVR);
2960 data |= gpio.smask & gpio.state;
2961 data &= ~(gpio.smask & ~gpio.state);
2962 wr_reg32(info, IOVR, data);
2963 }
2964 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2965
2966 return 0;
2967}
2968
2969/*
2970 * get general purpose IO pin state and direction
2971 */
2972static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973{
2974 struct gpio_desc gpio;
2975 if (!info->gpio_present)
2976 return -EINVAL;
2977 gpio.state = rd_reg32(info, IOVR);
2978 gpio.smask = 0xffffffff;
2979 gpio.dir = rd_reg32(info, IODR);
2980 gpio.dmask = 0xffffffff;
2981 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2982 return -EFAULT;
2983 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2984 info->device_name, gpio.state, gpio.dir));
2985 return 0;
2986}
2987
2988/*
2989 * conditional wait facility
2990 */
2991static void init_cond_wait(struct cond_wait *w, unsigned int data)
2992{
2993 init_waitqueue_head(&w->q);
2994 init_waitqueue_entry(&w->wait, current);
2995 w->data = data;
2996}
2997
2998static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2999{
3000 set_current_state(TASK_INTERRUPTIBLE);
3001 add_wait_queue(&w->q, &w->wait);
3002 w->next = *head;
3003 *head = w;
3004}
3005
3006static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3007{
3008 struct cond_wait *w, *prev;
3009 remove_wait_queue(&cw->q, &cw->wait);
3010 set_current_state(TASK_RUNNING);
3011 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3012 if (w == cw) {
3013 if (prev != NULL)
3014 prev->next = w->next;
3015 else
3016 *head = w->next;
3017 break;
3018 }
3019 }
3020}
3021
3022static void flush_cond_wait(struct cond_wait **head)
3023{
3024 while (*head != NULL) {
3025 wake_up_interruptible(&(*head)->q);
3026 *head = (*head)->next;
3027 }
3028}
3029
3030/*
3031 * wait for general purpose I/O pin(s) to enter specified state
3032 *
3033 * user_gpio fields:
3034 * state - bit indicates target pin state
3035 * smask - set bit indicates watched pin
3036 *
3037 * The wait ends when at least one watched pin enters the specified
3038 * state. When 0 (no error) is returned, user_gpio->state is set to the
3039 * state of all GPIO pins when the wait ends.
3040 *
3041 * Note: Each pin may be a dedicated input, dedicated output, or
3042 * configurable input/output. The number and configuration of pins
3043 * varies with the specific adapter model. Only input pins (dedicated
3044 * or configured) can be monitored with this function.
3045 */
3046static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3047{
3048 unsigned long flags;
3049 int rc = 0;
3050 struct gpio_desc gpio;
3051 struct cond_wait wait;
3052 u32 state;
3053
3054 if (!info->gpio_present)
3055 return -EINVAL;
3056 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3057 return -EFAULT;
3058 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3059 info->device_name, gpio.state, gpio.smask));
3060 /* ignore output pins identified by set IODR bit */
3061 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3062 return -EINVAL;
3063 init_cond_wait(&wait, gpio.smask);
3064
3065 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3066 /* enable interrupts for watched pins */
3067 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3068 /* get current pin states */
3069 state = rd_reg32(info, IOVR);
3070
3071 if (gpio.smask & ~(state ^ gpio.state)) {
3072 /* already in target state */
3073 gpio.state = state;
3074 } else {
3075 /* wait for target state */
3076 add_cond_wait(&info->gpio_wait_q, &wait);
3077 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3078 schedule();
3079 if (signal_pending(current))
3080 rc = -ERESTARTSYS;
3081 else
3082 gpio.state = wait.data;
3083 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3084 remove_cond_wait(&info->gpio_wait_q, &wait);
3085 }
3086
3087 /* disable all GPIO interrupts if no waiting processes */
3088 if (info->gpio_wait_q == NULL)
3089 wr_reg32(info, IOER, 0);
3090 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3091
3092 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3093 rc = -EFAULT;
3094 return rc;
3095}
3096
3097static int modem_input_wait(struct slgt_info *info,int arg)
3098{
3099 unsigned long flags;
3100 int rc;
3101 struct mgsl_icount cprev, cnow;
3102 DECLARE_WAITQUEUE(wait, current);
3103
3104 /* save current irq counts */
3105 spin_lock_irqsave(&info->lock,flags);
3106 cprev = info->icount;
3107 add_wait_queue(&info->status_event_wait_q, &wait);
3108 set_current_state(TASK_INTERRUPTIBLE);
3109 spin_unlock_irqrestore(&info->lock,flags);
3110
3111 for(;;) {
3112 schedule();
3113 if (signal_pending(current)) {
3114 rc = -ERESTARTSYS;
3115 break;
3116 }
3117
3118 /* get new irq counts */
3119 spin_lock_irqsave(&info->lock,flags);
3120 cnow = info->icount;
3121 set_current_state(TASK_INTERRUPTIBLE);
3122 spin_unlock_irqrestore(&info->lock,flags);
3123
3124 /* if no change, wait aborted for some reason */
3125 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3126 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3127 rc = -EIO;
3128 break;
3129 }
3130
3131 /* check for change in caller specified modem input */
3132 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3133 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3134 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3135 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3136 rc = 0;
3137 break;
3138 }
3139
3140 cprev = cnow;
3141 }
3142 remove_wait_queue(&info->status_event_wait_q, &wait);
3143 set_current_state(TASK_RUNNING);
3144 return rc;
3145}
3146
3147/*
3148 * return state of serial control and status signals
3149 */
3150static int tiocmget(struct tty_struct *tty)
3151{
3152 struct slgt_info *info = tty->driver_data;
3153 unsigned int result;
3154 unsigned long flags;
3155
3156 spin_lock_irqsave(&info->lock,flags);
3157 get_signals(info);
3158 spin_unlock_irqrestore(&info->lock,flags);
3159
3160 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3161 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3162 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3163 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3164 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3165 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3166
3167 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3168 return result;
3169}
3170
3171/*
3172 * set modem control signals (DTR/RTS)
3173 *
3174 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3175 * TIOCMSET = set/clear signal values
3176 * value bit mask for command
3177 */
3178static int tiocmset(struct tty_struct *tty,
3179 unsigned int set, unsigned int clear)
3180{
3181 struct slgt_info *info = tty->driver_data;
3182 unsigned long flags;
3183
3184 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3185
3186 if (set & TIOCM_RTS)
3187 info->signals |= SerialSignal_RTS;
3188 if (set & TIOCM_DTR)
3189 info->signals |= SerialSignal_DTR;
3190 if (clear & TIOCM_RTS)
3191 info->signals &= ~SerialSignal_RTS;
3192 if (clear & TIOCM_DTR)
3193 info->signals &= ~SerialSignal_DTR;
3194
3195 spin_lock_irqsave(&info->lock,flags);
3196 set_signals(info);
3197 spin_unlock_irqrestore(&info->lock,flags);
3198 return 0;
3199}
3200
3201static int carrier_raised(struct tty_port *port)
3202{
3203 unsigned long flags;
3204 struct slgt_info *info = container_of(port, struct slgt_info, port);
3205
3206 spin_lock_irqsave(&info->lock,flags);
3207 get_signals(info);
3208 spin_unlock_irqrestore(&info->lock,flags);
3209 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3210}
3211
3212static void dtr_rts(struct tty_port *port, int on)
3213{
3214 unsigned long flags;
3215 struct slgt_info *info = container_of(port, struct slgt_info, port);
3216
3217 spin_lock_irqsave(&info->lock,flags);
3218 if (on)
3219 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3220 else
3221 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3222 set_signals(info);
3223 spin_unlock_irqrestore(&info->lock,flags);
3224}
3225
3226
3227/*
3228 * block current process until the device is ready to open
3229 */
3230static int block_til_ready(struct tty_struct *tty, struct file *filp,
3231 struct slgt_info *info)
3232{
3233 DECLARE_WAITQUEUE(wait, current);
3234 int retval;
3235 bool do_clocal = false;
3236 unsigned long flags;
3237 int cd;
3238 struct tty_port *port = &info->port;
3239
3240 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3241
3242 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3243 /* nonblock mode is set or port is not enabled */
3244 tty_port_set_active(port, 1);
3245 return 0;
3246 }
3247
3248 if (C_CLOCAL(tty))
3249 do_clocal = true;
3250
3251 /* Wait for carrier detect and the line to become
3252 * free (i.e., not in use by the callout). While we are in
3253 * this loop, port->count is dropped by one, so that
3254 * close() knows when to free things. We restore it upon
3255 * exit, either normal or abnormal.
3256 */
3257
3258 retval = 0;
3259 add_wait_queue(&port->open_wait, &wait);
3260
3261 spin_lock_irqsave(&info->lock, flags);
3262 port->count--;
3263 spin_unlock_irqrestore(&info->lock, flags);
3264 port->blocked_open++;
3265
3266 while (1) {
3267 if (C_BAUD(tty) && tty_port_initialized(port))
3268 tty_port_raise_dtr_rts(port);
3269
3270 set_current_state(TASK_INTERRUPTIBLE);
3271
3272 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3273 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3274 -EAGAIN : -ERESTARTSYS;
3275 break;
3276 }
3277
3278 cd = tty_port_carrier_raised(port);
3279 if (do_clocal || cd)
3280 break;
3281
3282 if (signal_pending(current)) {
3283 retval = -ERESTARTSYS;
3284 break;
3285 }
3286
3287 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3288 tty_unlock(tty);
3289 schedule();
3290 tty_lock(tty);
3291 }
3292
3293 set_current_state(TASK_RUNNING);
3294 remove_wait_queue(&port->open_wait, &wait);
3295
3296 if (!tty_hung_up_p(filp))
3297 port->count++;
3298 port->blocked_open--;
3299
3300 if (!retval)
3301 tty_port_set_active(port, 1);
3302
3303 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3304 return retval;
3305}
3306
3307/*
3308 * allocate buffers used for calling line discipline receive_buf
3309 * directly in synchronous mode
3310 * note: add 5 bytes to max frame size to allow appending
3311 * 32-bit CRC and status byte when configured to do so
3312 */
3313static int alloc_tmp_rbuf(struct slgt_info *info)
3314{
3315 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3316 if (info->tmp_rbuf == NULL)
3317 return -ENOMEM;
3318 /* unused flag buffer to satisfy receive_buf calling interface */
3319 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3320 if (!info->flag_buf) {
3321 kfree(info->tmp_rbuf);
3322 info->tmp_rbuf = NULL;
3323 return -ENOMEM;
3324 }
3325 return 0;
3326}
3327
3328static void free_tmp_rbuf(struct slgt_info *info)
3329{
3330 kfree(info->tmp_rbuf);
3331 info->tmp_rbuf = NULL;
3332 kfree(info->flag_buf);
3333 info->flag_buf = NULL;
3334}
3335
3336/*
3337 * allocate DMA descriptor lists.
3338 */
3339static int alloc_desc(struct slgt_info *info)
3340{
3341 unsigned int i;
3342 unsigned int pbufs;
3343
3344 /* allocate memory to hold descriptor lists */
3345 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3346 &info->bufs_dma_addr);
3347 if (info->bufs == NULL)
3348 return -ENOMEM;
3349
3350 info->rbufs = (struct slgt_desc*)info->bufs;
3351 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3352
3353 pbufs = (unsigned int)info->bufs_dma_addr;
3354
3355 /*
3356 * Build circular lists of descriptors
3357 */
3358
3359 for (i=0; i < info->rbuf_count; i++) {
3360 /* physical address of this descriptor */
3361 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3362
3363 /* physical address of next descriptor */
3364 if (i == info->rbuf_count - 1)
3365 info->rbufs[i].next = cpu_to_le32(pbufs);
3366 else
3367 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3368 set_desc_count(info->rbufs[i], DMABUFSIZE);
3369 }
3370
3371 for (i=0; i < info->tbuf_count; i++) {
3372 /* physical address of this descriptor */
3373 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3374
3375 /* physical address of next descriptor */
3376 if (i == info->tbuf_count - 1)
3377 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3378 else
3379 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3380 }
3381
3382 return 0;
3383}
3384
3385static void free_desc(struct slgt_info *info)
3386{
3387 if (info->bufs != NULL) {
3388 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3389 info->bufs = NULL;
3390 info->rbufs = NULL;
3391 info->tbufs = NULL;
3392 }
3393}
3394
3395static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3396{
3397 int i;
3398 for (i=0; i < count; i++) {
3399 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3400 return -ENOMEM;
3401 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3402 }
3403 return 0;
3404}
3405
3406static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3407{
3408 int i;
3409 for (i=0; i < count; i++) {
3410 if (bufs[i].buf == NULL)
3411 continue;
3412 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3413 bufs[i].buf = NULL;
3414 }
3415}
3416
3417static int alloc_dma_bufs(struct slgt_info *info)
3418{
3419 info->rbuf_count = 32;
3420 info->tbuf_count = 32;
3421
3422 if (alloc_desc(info) < 0 ||
3423 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3424 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3425 alloc_tmp_rbuf(info) < 0) {
3426 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3427 return -ENOMEM;
3428 }
3429 reset_rbufs(info);
3430 return 0;
3431}
3432
3433static void free_dma_bufs(struct slgt_info *info)
3434{
3435 if (info->bufs) {
3436 free_bufs(info, info->rbufs, info->rbuf_count);
3437 free_bufs(info, info->tbufs, info->tbuf_count);
3438 free_desc(info);
3439 }
3440 free_tmp_rbuf(info);
3441}
3442
3443static int claim_resources(struct slgt_info *info)
3444{
3445 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3446 DBGERR(("%s reg addr conflict, addr=%08X\n",
3447 info->device_name, info->phys_reg_addr));
3448 info->init_error = DiagStatus_AddressConflict;
3449 goto errout;
3450 }
3451 else
3452 info->reg_addr_requested = true;
3453
3454 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3455 if (!info->reg_addr) {
3456 DBGERR(("%s can't map device registers, addr=%08X\n",
3457 info->device_name, info->phys_reg_addr));
3458 info->init_error = DiagStatus_CantAssignPciResources;
3459 goto errout;
3460 }
3461 return 0;
3462
3463errout:
3464 release_resources(info);
3465 return -ENODEV;
3466}
3467
3468static void release_resources(struct slgt_info *info)
3469{
3470 if (info->irq_requested) {
3471 free_irq(info->irq_level, info);
3472 info->irq_requested = false;
3473 }
3474
3475 if (info->reg_addr_requested) {
3476 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3477 info->reg_addr_requested = false;
3478 }
3479
3480 if (info->reg_addr) {
3481 iounmap(info->reg_addr);
3482 info->reg_addr = NULL;
3483 }
3484}
3485
3486/* Add the specified device instance data structure to the
3487 * global linked list of devices and increment the device count.
3488 */
3489static void add_device(struct slgt_info *info)
3490{
3491 char *devstr;
3492
3493 info->next_device = NULL;
3494 info->line = slgt_device_count;
3495 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3496
3497 if (info->line < MAX_DEVICES) {
3498 if (maxframe[info->line])
3499 info->max_frame_size = maxframe[info->line];
3500 }
3501
3502 slgt_device_count++;
3503
3504 if (!slgt_device_list)
3505 slgt_device_list = info;
3506 else {
3507 struct slgt_info *current_dev = slgt_device_list;
3508 while(current_dev->next_device)
3509 current_dev = current_dev->next_device;
3510 current_dev->next_device = info;
3511 }
3512
3513 if (info->max_frame_size < 4096)
3514 info->max_frame_size = 4096;
3515 else if (info->max_frame_size > 65535)
3516 info->max_frame_size = 65535;
3517
3518 switch(info->pdev->device) {
3519 case SYNCLINK_GT_DEVICE_ID:
3520 devstr = "GT";
3521 break;
3522 case SYNCLINK_GT2_DEVICE_ID:
3523 devstr = "GT2";
3524 break;
3525 case SYNCLINK_GT4_DEVICE_ID:
3526 devstr = "GT4";
3527 break;
3528 case SYNCLINK_AC_DEVICE_ID:
3529 devstr = "AC";
3530 info->params.mode = MGSL_MODE_ASYNC;
3531 break;
3532 default:
3533 devstr = "(unknown model)";
3534 }
3535 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3536 devstr, info->device_name, info->phys_reg_addr,
3537 info->irq_level, info->max_frame_size);
3538
3539#if SYNCLINK_GENERIC_HDLC
3540 hdlcdev_init(info);
3541#endif
3542}
3543
3544static const struct tty_port_operations slgt_port_ops = {
3545 .carrier_raised = carrier_raised,
3546 .dtr_rts = dtr_rts,
3547};
3548
3549/*
3550 * allocate device instance structure, return NULL on failure
3551 */
3552static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3553{
3554 struct slgt_info *info;
3555
3556 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3557
3558 if (!info) {
3559 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3560 driver_name, adapter_num, port_num));
3561 } else {
3562 tty_port_init(&info->port);
3563 info->port.ops = &slgt_port_ops;
3564 info->magic = MGSL_MAGIC;
3565 INIT_WORK(&info->task, bh_handler);
3566 info->max_frame_size = 4096;
3567 info->base_clock = 14745600;
3568 info->rbuf_fill_level = DMABUFSIZE;
3569 info->port.close_delay = 5*HZ/10;
3570 info->port.closing_wait = 30*HZ;
3571 init_waitqueue_head(&info->status_event_wait_q);
3572 init_waitqueue_head(&info->event_wait_q);
3573 spin_lock_init(&info->netlock);
3574 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3575 info->idle_mode = HDLC_TXIDLE_FLAGS;
3576 info->adapter_num = adapter_num;
3577 info->port_num = port_num;
3578
3579 timer_setup(&info->tx_timer, tx_timeout, 0);
3580 timer_setup(&info->rx_timer, rx_timeout, 0);
3581
3582 /* Copy configuration info to device instance data */
3583 info->pdev = pdev;
3584 info->irq_level = pdev->irq;
3585 info->phys_reg_addr = pci_resource_start(pdev,0);
3586
3587 info->bus_type = MGSL_BUS_TYPE_PCI;
3588 info->irq_flags = IRQF_SHARED;
3589
3590 info->init_error = -1; /* assume error, set to 0 on successful init */
3591 }
3592
3593 return info;
3594}
3595
3596static void device_init(int adapter_num, struct pci_dev *pdev)
3597{
3598 struct slgt_info *port_array[SLGT_MAX_PORTS];
3599 int i;
3600 int port_count = 1;
3601
3602 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3603 port_count = 2;
3604 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3605 port_count = 4;
3606
3607 /* allocate device instances for all ports */
3608 for (i=0; i < port_count; ++i) {
3609 port_array[i] = alloc_dev(adapter_num, i, pdev);
3610 if (port_array[i] == NULL) {
3611 for (--i; i >= 0; --i) {
3612 tty_port_destroy(&port_array[i]->port);
3613 kfree(port_array[i]);
3614 }
3615 return;
3616 }
3617 }
3618
3619 /* give copy of port_array to all ports and add to device list */
3620 for (i=0; i < port_count; ++i) {
3621 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3622 add_device(port_array[i]);
3623 port_array[i]->port_count = port_count;
3624 spin_lock_init(&port_array[i]->lock);
3625 }
3626
3627 /* Allocate and claim adapter resources */
3628 if (!claim_resources(port_array[0])) {
3629
3630 alloc_dma_bufs(port_array[0]);
3631
3632 /* copy resource information from first port to others */
3633 for (i = 1; i < port_count; ++i) {
3634 port_array[i]->irq_level = port_array[0]->irq_level;
3635 port_array[i]->reg_addr = port_array[0]->reg_addr;
3636 alloc_dma_bufs(port_array[i]);
3637 }
3638
3639 if (request_irq(port_array[0]->irq_level,
3640 slgt_interrupt,
3641 port_array[0]->irq_flags,
3642 port_array[0]->device_name,
3643 port_array[0]) < 0) {
3644 DBGERR(("%s request_irq failed IRQ=%d\n",
3645 port_array[0]->device_name,
3646 port_array[0]->irq_level));
3647 } else {
3648 port_array[0]->irq_requested = true;
3649 adapter_test(port_array[0]);
3650 for (i=1 ; i < port_count ; i++) {
3651 port_array[i]->init_error = port_array[0]->init_error;
3652 port_array[i]->gpio_present = port_array[0]->gpio_present;
3653 }
3654 }
3655 }
3656
3657 for (i = 0; i < port_count; ++i) {
3658 struct slgt_info *info = port_array[i];
3659 tty_port_register_device(&info->port, serial_driver, info->line,
3660 &info->pdev->dev);
3661 }
3662}
3663
3664static int init_one(struct pci_dev *dev,
3665 const struct pci_device_id *ent)
3666{
3667 if (pci_enable_device(dev)) {
3668 printk("error enabling pci device %p\n", dev);
3669 return -EIO;
3670 }
3671 pci_set_master(dev);
3672 device_init(slgt_device_count, dev);
3673 return 0;
3674}
3675
3676static void remove_one(struct pci_dev *dev)
3677{
3678}
3679
3680static const struct tty_operations ops = {
3681 .open = open,
3682 .close = close,
3683 .write = write,
3684 .put_char = put_char,
3685 .flush_chars = flush_chars,
3686 .write_room = write_room,
3687 .chars_in_buffer = chars_in_buffer,
3688 .flush_buffer = flush_buffer,
3689 .ioctl = ioctl,
3690 .compat_ioctl = slgt_compat_ioctl,
3691 .throttle = throttle,
3692 .unthrottle = unthrottle,
3693 .send_xchar = send_xchar,
3694 .break_ctl = set_break,
3695 .wait_until_sent = wait_until_sent,
3696 .set_termios = set_termios,
3697 .stop = tx_hold,
3698 .start = tx_release,
3699 .hangup = hangup,
3700 .tiocmget = tiocmget,
3701 .tiocmset = tiocmset,
3702 .get_icount = get_icount,
3703 .proc_show = synclink_gt_proc_show,
3704};
3705
3706static void slgt_cleanup(void)
3707{
3708 int rc;
3709 struct slgt_info *info;
3710 struct slgt_info *tmp;
3711
3712 printk(KERN_INFO "unload %s\n", driver_name);
3713
3714 if (serial_driver) {
3715 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3716 tty_unregister_device(serial_driver, info->line);
3717 rc = tty_unregister_driver(serial_driver);
3718 if (rc)
3719 DBGERR(("tty_unregister_driver error=%d\n", rc));
3720 put_tty_driver(serial_driver);
3721 }
3722
3723 /* reset devices */
3724 info = slgt_device_list;
3725 while(info) {
3726 reset_port(info);
3727 info = info->next_device;
3728 }
3729
3730 /* release devices */
3731 info = slgt_device_list;
3732 while(info) {
3733#if SYNCLINK_GENERIC_HDLC
3734 hdlcdev_exit(info);
3735#endif
3736 free_dma_bufs(info);
3737 free_tmp_rbuf(info);
3738 if (info->port_num == 0)
3739 release_resources(info);
3740 tmp = info;
3741 info = info->next_device;
3742 tty_port_destroy(&tmp->port);
3743 kfree(tmp);
3744 }
3745
3746 if (pci_registered)
3747 pci_unregister_driver(&pci_driver);
3748}
3749
3750/*
3751 * Driver initialization entry point.
3752 */
3753static int __init slgt_init(void)
3754{
3755 int rc;
3756
3757 printk(KERN_INFO "%s\n", driver_name);
3758
3759 serial_driver = alloc_tty_driver(MAX_DEVICES);
3760 if (!serial_driver) {
3761 printk("%s can't allocate tty driver\n", driver_name);
3762 return -ENOMEM;
3763 }
3764
3765 /* Initialize the tty_driver structure */
3766
3767 serial_driver->driver_name = slgt_driver_name;
3768 serial_driver->name = tty_dev_prefix;
3769 serial_driver->major = ttymajor;
3770 serial_driver->minor_start = 64;
3771 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3772 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3773 serial_driver->init_termios = tty_std_termios;
3774 serial_driver->init_termios.c_cflag =
3775 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3776 serial_driver->init_termios.c_ispeed = 9600;
3777 serial_driver->init_termios.c_ospeed = 9600;
3778 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3779 tty_set_operations(serial_driver, &ops);
3780 if ((rc = tty_register_driver(serial_driver)) < 0) {
3781 DBGERR(("%s can't register serial driver\n", driver_name));
3782 put_tty_driver(serial_driver);
3783 serial_driver = NULL;
3784 goto error;
3785 }
3786
3787 printk(KERN_INFO "%s, tty major#%d\n",
3788 driver_name, serial_driver->major);
3789
3790 slgt_device_count = 0;
3791 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3792 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3793 goto error;
3794 }
3795 pci_registered = true;
3796
3797 if (!slgt_device_list)
3798 printk("%s no devices found\n",driver_name);
3799
3800 return 0;
3801
3802error:
3803 slgt_cleanup();
3804 return rc;
3805}
3806
3807static void __exit slgt_exit(void)
3808{
3809 slgt_cleanup();
3810}
3811
3812module_init(slgt_init);
3813module_exit(slgt_exit);
3814
3815/*
3816 * register access routines
3817 */
3818
3819#define CALC_REGADDR() \
3820 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3821 if (addr >= 0x80) \
3822 reg_addr += (info->port_num) * 32; \
3823 else if (addr >= 0x40) \
3824 reg_addr += (info->port_num) * 16;
3825
3826static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3827{
3828 CALC_REGADDR();
3829 return readb((void __iomem *)reg_addr);
3830}
3831
3832static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3833{
3834 CALC_REGADDR();
3835 writeb(value, (void __iomem *)reg_addr);
3836}
3837
3838static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3839{
3840 CALC_REGADDR();
3841 return readw((void __iomem *)reg_addr);
3842}
3843
3844static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3845{
3846 CALC_REGADDR();
3847 writew(value, (void __iomem *)reg_addr);
3848}
3849
3850static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3851{
3852 CALC_REGADDR();
3853 return readl((void __iomem *)reg_addr);
3854}
3855
3856static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3857{
3858 CALC_REGADDR();
3859 writel(value, (void __iomem *)reg_addr);
3860}
3861
3862static void rdma_reset(struct slgt_info *info)
3863{
3864 unsigned int i;
3865
3866 /* set reset bit */
3867 wr_reg32(info, RDCSR, BIT1);
3868
3869 /* wait for enable bit cleared */
3870 for(i=0 ; i < 1000 ; i++)
3871 if (!(rd_reg32(info, RDCSR) & BIT0))
3872 break;
3873}
3874
3875static void tdma_reset(struct slgt_info *info)
3876{
3877 unsigned int i;
3878
3879 /* set reset bit */
3880 wr_reg32(info, TDCSR, BIT1);
3881
3882 /* wait for enable bit cleared */
3883 for(i=0 ; i < 1000 ; i++)
3884 if (!(rd_reg32(info, TDCSR) & BIT0))
3885 break;
3886}
3887
3888/*
3889 * enable internal loopback
3890 * TxCLK and RxCLK are generated from BRG
3891 * and TxD is looped back to RxD internally.
3892 */
3893static void enable_loopback(struct slgt_info *info)
3894{
3895 /* SCR (serial control) BIT2=loopback enable */
3896 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3897
3898 if (info->params.mode != MGSL_MODE_ASYNC) {
3899 /* CCR (clock control)
3900 * 07..05 tx clock source (010 = BRG)
3901 * 04..02 rx clock source (010 = BRG)
3902 * 01 auxclk enable (0 = disable)
3903 * 00 BRG enable (1 = enable)
3904 *
3905 * 0100 1001
3906 */
3907 wr_reg8(info, CCR, 0x49);
3908
3909 /* set speed if available, otherwise use default */
3910 if (info->params.clock_speed)
3911 set_rate(info, info->params.clock_speed);
3912 else
3913 set_rate(info, 3686400);
3914 }
3915}
3916
3917/*
3918 * set baud rate generator to specified rate
3919 */
3920static void set_rate(struct slgt_info *info, u32 rate)
3921{
3922 unsigned int div;
3923 unsigned int osc = info->base_clock;
3924
3925 /* div = osc/rate - 1
3926 *
3927 * Round div up if osc/rate is not integer to
3928 * force to next slowest rate.
3929 */
3930
3931 if (rate) {
3932 div = osc/rate;
3933 if (!(osc % rate) && div)
3934 div--;
3935 wr_reg16(info, BDR, (unsigned short)div);
3936 }
3937}
3938
3939static void rx_stop(struct slgt_info *info)
3940{
3941 unsigned short val;
3942
3943 /* disable and reset receiver */
3944 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3945 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3946 wr_reg16(info, RCR, val); /* clear reset bit */
3947
3948 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3949
3950 /* clear pending rx interrupts */
3951 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3952
3953 rdma_reset(info);
3954
3955 info->rx_enabled = false;
3956 info->rx_restart = false;
3957}
3958
3959static void rx_start(struct slgt_info *info)
3960{
3961 unsigned short val;
3962
3963 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3964
3965 /* clear pending rx overrun IRQ */
3966 wr_reg16(info, SSR, IRQ_RXOVER);
3967
3968 /* reset and disable receiver */
3969 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3970 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3971 wr_reg16(info, RCR, val); /* clear reset bit */
3972
3973 rdma_reset(info);
3974 reset_rbufs(info);
3975
3976 if (info->rx_pio) {
3977 /* rx request when rx FIFO not empty */
3978 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3979 slgt_irq_on(info, IRQ_RXDATA);
3980 if (info->params.mode == MGSL_MODE_ASYNC) {
3981 /* enable saving of rx status */
3982 wr_reg32(info, RDCSR, BIT6);
3983 }
3984 } else {
3985 /* rx request when rx FIFO half full */
3986 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3987 /* set 1st descriptor address */
3988 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3989
3990 if (info->params.mode != MGSL_MODE_ASYNC) {
3991 /* enable rx DMA and DMA interrupt */
3992 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3993 } else {
3994 /* enable saving of rx status, rx DMA and DMA interrupt */
3995 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3996 }
3997 }
3998
3999 slgt_irq_on(info, IRQ_RXOVER);
4000
4001 /* enable receiver */
4002 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4003
4004 info->rx_restart = false;
4005 info->rx_enabled = true;
4006}
4007
4008static void tx_start(struct slgt_info *info)
4009{
4010 if (!info->tx_enabled) {
4011 wr_reg16(info, TCR,
4012 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4013 info->tx_enabled = true;
4014 }
4015
4016 if (desc_count(info->tbufs[info->tbuf_start])) {
4017 info->drop_rts_on_tx_done = false;
4018
4019 if (info->params.mode != MGSL_MODE_ASYNC) {
4020 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4021 get_signals(info);
4022 if (!(info->signals & SerialSignal_RTS)) {
4023 info->signals |= SerialSignal_RTS;
4024 set_signals(info);
4025 info->drop_rts_on_tx_done = true;
4026 }
4027 }
4028
4029 slgt_irq_off(info, IRQ_TXDATA);
4030 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4031 /* clear tx idle and underrun status bits */
4032 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4033 } else {
4034 slgt_irq_off(info, IRQ_TXDATA);
4035 slgt_irq_on(info, IRQ_TXIDLE);
4036 /* clear tx idle status bit */
4037 wr_reg16(info, SSR, IRQ_TXIDLE);
4038 }
4039 /* set 1st descriptor address and start DMA */
4040 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4041 wr_reg32(info, TDCSR, BIT2 + BIT0);
4042 info->tx_active = true;
4043 }
4044}
4045
4046static void tx_stop(struct slgt_info *info)
4047{
4048 unsigned short val;
4049
4050 del_timer(&info->tx_timer);
4051
4052 tdma_reset(info);
4053
4054 /* reset and disable transmitter */
4055 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4056 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4057
4058 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4059
4060 /* clear tx idle and underrun status bit */
4061 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4062
4063 reset_tbufs(info);
4064
4065 info->tx_enabled = false;
4066 info->tx_active = false;
4067}
4068
4069static void reset_port(struct slgt_info *info)
4070{
4071 if (!info->reg_addr)
4072 return;
4073
4074 tx_stop(info);
4075 rx_stop(info);
4076
4077 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4078 set_signals(info);
4079
4080 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4081}
4082
4083static void reset_adapter(struct slgt_info *info)
4084{
4085 int i;
4086 for (i=0; i < info->port_count; ++i) {
4087 if (info->port_array[i])
4088 reset_port(info->port_array[i]);
4089 }
4090}
4091
4092static void async_mode(struct slgt_info *info)
4093{
4094 unsigned short val;
4095
4096 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4097 tx_stop(info);
4098 rx_stop(info);
4099
4100 /* TCR (tx control)
4101 *
4102 * 15..13 mode, 010=async
4103 * 12..10 encoding, 000=NRZ
4104 * 09 parity enable
4105 * 08 1=odd parity, 0=even parity
4106 * 07 1=RTS driver control
4107 * 06 1=break enable
4108 * 05..04 character length
4109 * 00=5 bits
4110 * 01=6 bits
4111 * 10=7 bits
4112 * 11=8 bits
4113 * 03 0=1 stop bit, 1=2 stop bits
4114 * 02 reset
4115 * 01 enable
4116 * 00 auto-CTS enable
4117 */
4118 val = 0x4000;
4119
4120 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4121 val |= BIT7;
4122
4123 if (info->params.parity != ASYNC_PARITY_NONE) {
4124 val |= BIT9;
4125 if (info->params.parity == ASYNC_PARITY_ODD)
4126 val |= BIT8;
4127 }
4128
4129 switch (info->params.data_bits)
4130 {
4131 case 6: val |= BIT4; break;
4132 case 7: val |= BIT5; break;
4133 case 8: val |= BIT5 + BIT4; break;
4134 }
4135
4136 if (info->params.stop_bits != 1)
4137 val |= BIT3;
4138
4139 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4140 val |= BIT0;
4141
4142 wr_reg16(info, TCR, val);
4143
4144 /* RCR (rx control)
4145 *
4146 * 15..13 mode, 010=async
4147 * 12..10 encoding, 000=NRZ
4148 * 09 parity enable
4149 * 08 1=odd parity, 0=even parity
4150 * 07..06 reserved, must be 0
4151 * 05..04 character length
4152 * 00=5 bits
4153 * 01=6 bits
4154 * 10=7 bits
4155 * 11=8 bits
4156 * 03 reserved, must be zero
4157 * 02 reset
4158 * 01 enable
4159 * 00 auto-DCD enable
4160 */
4161 val = 0x4000;
4162
4163 if (info->params.parity != ASYNC_PARITY_NONE) {
4164 val |= BIT9;
4165 if (info->params.parity == ASYNC_PARITY_ODD)
4166 val |= BIT8;
4167 }
4168
4169 switch (info->params.data_bits)
4170 {
4171 case 6: val |= BIT4; break;
4172 case 7: val |= BIT5; break;
4173 case 8: val |= BIT5 + BIT4; break;
4174 }
4175
4176 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4177 val |= BIT0;
4178
4179 wr_reg16(info, RCR, val);
4180
4181 /* CCR (clock control)
4182 *
4183 * 07..05 011 = tx clock source is BRG/16
4184 * 04..02 010 = rx clock source is BRG
4185 * 01 0 = auxclk disabled
4186 * 00 1 = BRG enabled
4187 *
4188 * 0110 1001
4189 */
4190 wr_reg8(info, CCR, 0x69);
4191
4192 msc_set_vcr(info);
4193
4194 /* SCR (serial control)
4195 *
4196 * 15 1=tx req on FIFO half empty
4197 * 14 1=rx req on FIFO half full
4198 * 13 tx data IRQ enable
4199 * 12 tx idle IRQ enable
4200 * 11 rx break on IRQ enable
4201 * 10 rx data IRQ enable
4202 * 09 rx break off IRQ enable
4203 * 08 overrun IRQ enable
4204 * 07 DSR IRQ enable
4205 * 06 CTS IRQ enable
4206 * 05 DCD IRQ enable
4207 * 04 RI IRQ enable
4208 * 03 0=16x sampling, 1=8x sampling
4209 * 02 1=txd->rxd internal loopback enable
4210 * 01 reserved, must be zero
4211 * 00 1=master IRQ enable
4212 */
4213 val = BIT15 + BIT14 + BIT0;
4214 /* JCR[8] : 1 = x8 async mode feature available */
4215 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4216 ((info->base_clock < (info->params.data_rate * 16)) ||
4217 (info->base_clock % (info->params.data_rate * 16)))) {
4218 /* use 8x sampling */
4219 val |= BIT3;
4220 set_rate(info, info->params.data_rate * 8);
4221 } else {
4222 /* use 16x sampling */
4223 set_rate(info, info->params.data_rate * 16);
4224 }
4225 wr_reg16(info, SCR, val);
4226
4227 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4228
4229 if (info->params.loopback)
4230 enable_loopback(info);
4231}
4232
4233static void sync_mode(struct slgt_info *info)
4234{
4235 unsigned short val;
4236
4237 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4238 tx_stop(info);
4239 rx_stop(info);
4240
4241 /* TCR (tx control)
4242 *
4243 * 15..13 mode
4244 * 000=HDLC/SDLC
4245 * 001=raw bit synchronous
4246 * 010=asynchronous/isochronous
4247 * 011=monosync byte synchronous
4248 * 100=bisync byte synchronous
4249 * 101=xsync byte synchronous
4250 * 12..10 encoding
4251 * 09 CRC enable
4252 * 08 CRC32
4253 * 07 1=RTS driver control
4254 * 06 preamble enable
4255 * 05..04 preamble length
4256 * 03 share open/close flag
4257 * 02 reset
4258 * 01 enable
4259 * 00 auto-CTS enable
4260 */
4261 val = BIT2;
4262
4263 switch(info->params.mode) {
4264 case MGSL_MODE_XSYNC:
4265 val |= BIT15 + BIT13;
4266 break;
4267 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4268 case MGSL_MODE_BISYNC: val |= BIT15; break;
4269 case MGSL_MODE_RAW: val |= BIT13; break;
4270 }
4271 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4272 val |= BIT7;
4273
4274 switch(info->params.encoding)
4275 {
4276 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4277 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4278 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4279 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4280 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4281 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4282 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4283 }
4284
4285 switch (info->params.crc_type & HDLC_CRC_MASK)
4286 {
4287 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4288 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4289 }
4290
4291 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4292 val |= BIT6;
4293
4294 switch (info->params.preamble_length)
4295 {
4296 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4297 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4298 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4299 }
4300
4301 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4302 val |= BIT0;
4303
4304 wr_reg16(info, TCR, val);
4305
4306 /* TPR (transmit preamble) */
4307
4308 switch (info->params.preamble)
4309 {
4310 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4311 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4312 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4313 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4314 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4315 default: val = 0x7e; break;
4316 }
4317 wr_reg8(info, TPR, (unsigned char)val);
4318
4319 /* RCR (rx control)
4320 *
4321 * 15..13 mode
4322 * 000=HDLC/SDLC
4323 * 001=raw bit synchronous
4324 * 010=asynchronous/isochronous
4325 * 011=monosync byte synchronous
4326 * 100=bisync byte synchronous
4327 * 101=xsync byte synchronous
4328 * 12..10 encoding
4329 * 09 CRC enable
4330 * 08 CRC32
4331 * 07..03 reserved, must be 0
4332 * 02 reset
4333 * 01 enable
4334 * 00 auto-DCD enable
4335 */
4336 val = 0;
4337
4338 switch(info->params.mode) {
4339 case MGSL_MODE_XSYNC:
4340 val |= BIT15 + BIT13;
4341 break;
4342 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4343 case MGSL_MODE_BISYNC: val |= BIT15; break;
4344 case MGSL_MODE_RAW: val |= BIT13; break;
4345 }
4346
4347 switch(info->params.encoding)
4348 {
4349 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4350 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4351 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4352 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4353 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4354 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4355 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4356 }
4357
4358 switch (info->params.crc_type & HDLC_CRC_MASK)
4359 {
4360 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4361 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4362 }
4363
4364 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4365 val |= BIT0;
4366
4367 wr_reg16(info, RCR, val);
4368
4369 /* CCR (clock control)
4370 *
4371 * 07..05 tx clock source
4372 * 04..02 rx clock source
4373 * 01 auxclk enable
4374 * 00 BRG enable
4375 */
4376 val = 0;
4377
4378 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4379 {
4380 // when RxC source is DPLL, BRG generates 16X DPLL
4381 // reference clock, so take TxC from BRG/16 to get
4382 // transmit clock at actual data rate
4383 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4384 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4385 else
4386 val |= BIT6; /* 010, txclk = BRG */
4387 }
4388 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4389 val |= BIT7; /* 100, txclk = DPLL Input */
4390 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4391 val |= BIT5; /* 001, txclk = RXC Input */
4392
4393 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4394 val |= BIT3; /* 010, rxclk = BRG */
4395 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4396 val |= BIT4; /* 100, rxclk = DPLL */
4397 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4398 val |= BIT2; /* 001, rxclk = TXC Input */
4399
4400 if (info->params.clock_speed)
4401 val |= BIT1 + BIT0;
4402
4403 wr_reg8(info, CCR, (unsigned char)val);
4404
4405 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4406 {
4407 // program DPLL mode
4408 switch(info->params.encoding)
4409 {
4410 case HDLC_ENCODING_BIPHASE_MARK:
4411 case HDLC_ENCODING_BIPHASE_SPACE:
4412 val = BIT7; break;
4413 case HDLC_ENCODING_BIPHASE_LEVEL:
4414 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4415 val = BIT7 + BIT6; break;
4416 default: val = BIT6; // NRZ encodings
4417 }
4418 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4419
4420 // DPLL requires a 16X reference clock from BRG
4421 set_rate(info, info->params.clock_speed * 16);
4422 }
4423 else
4424 set_rate(info, info->params.clock_speed);
4425
4426 tx_set_idle(info);
4427
4428 msc_set_vcr(info);
4429
4430 /* SCR (serial control)
4431 *
4432 * 15 1=tx req on FIFO half empty
4433 * 14 1=rx req on FIFO half full
4434 * 13 tx data IRQ enable
4435 * 12 tx idle IRQ enable
4436 * 11 underrun IRQ enable
4437 * 10 rx data IRQ enable
4438 * 09 rx idle IRQ enable
4439 * 08 overrun IRQ enable
4440 * 07 DSR IRQ enable
4441 * 06 CTS IRQ enable
4442 * 05 DCD IRQ enable
4443 * 04 RI IRQ enable
4444 * 03 reserved, must be zero
4445 * 02 1=txd->rxd internal loopback enable
4446 * 01 reserved, must be zero
4447 * 00 1=master IRQ enable
4448 */
4449 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4450
4451 if (info->params.loopback)
4452 enable_loopback(info);
4453}
4454
4455/*
4456 * set transmit idle mode
4457 */
4458static void tx_set_idle(struct slgt_info *info)
4459{
4460 unsigned char val;
4461 unsigned short tcr;
4462
4463 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4464 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4465 */
4466 tcr = rd_reg16(info, TCR);
4467 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4468 /* disable preamble, set idle size to 16 bits */
4469 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4470 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4471 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4472 } else if (!(tcr & BIT6)) {
4473 /* preamble is disabled, set idle size to 8 bits */
4474 tcr &= ~(BIT5 + BIT4);
4475 }
4476 wr_reg16(info, TCR, tcr);
4477
4478 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4479 /* LSB of custom tx idle specified in tx idle register */
4480 val = (unsigned char)(info->idle_mode & 0xff);
4481 } else {
4482 /* standard 8 bit idle patterns */
4483 switch(info->idle_mode)
4484 {
4485 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4486 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4487 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4488 case HDLC_TXIDLE_ZEROS:
4489 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4490 default: val = 0xff;
4491 }
4492 }
4493
4494 wr_reg8(info, TIR, val);
4495}
4496
4497/*
4498 * get state of V24 status (input) signals
4499 */
4500static void get_signals(struct slgt_info *info)
4501{
4502 unsigned short status = rd_reg16(info, SSR);
4503
4504 /* clear all serial signals except RTS and DTR */
4505 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4506
4507 if (status & BIT3)
4508 info->signals |= SerialSignal_DSR;
4509 if (status & BIT2)
4510 info->signals |= SerialSignal_CTS;
4511 if (status & BIT1)
4512 info->signals |= SerialSignal_DCD;
4513 if (status & BIT0)
4514 info->signals |= SerialSignal_RI;
4515}
4516
4517/*
4518 * set V.24 Control Register based on current configuration
4519 */
4520static void msc_set_vcr(struct slgt_info *info)
4521{
4522 unsigned char val = 0;
4523
4524 /* VCR (V.24 control)
4525 *
4526 * 07..04 serial IF select
4527 * 03 DTR
4528 * 02 RTS
4529 * 01 LL
4530 * 00 RL
4531 */
4532
4533 switch(info->if_mode & MGSL_INTERFACE_MASK)
4534 {
4535 case MGSL_INTERFACE_RS232:
4536 val |= BIT5; /* 0010 */
4537 break;
4538 case MGSL_INTERFACE_V35:
4539 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4540 break;
4541 case MGSL_INTERFACE_RS422:
4542 val |= BIT6; /* 0100 */
4543 break;
4544 }
4545
4546 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4547 val |= BIT4;
4548 if (info->signals & SerialSignal_DTR)
4549 val |= BIT3;
4550 if (info->signals & SerialSignal_RTS)
4551 val |= BIT2;
4552 if (info->if_mode & MGSL_INTERFACE_LL)
4553 val |= BIT1;
4554 if (info->if_mode & MGSL_INTERFACE_RL)
4555 val |= BIT0;
4556 wr_reg8(info, VCR, val);
4557}
4558
4559/*
4560 * set state of V24 control (output) signals
4561 */
4562static void set_signals(struct slgt_info *info)
4563{
4564 unsigned char val = rd_reg8(info, VCR);
4565 if (info->signals & SerialSignal_DTR)
4566 val |= BIT3;
4567 else
4568 val &= ~BIT3;
4569 if (info->signals & SerialSignal_RTS)
4570 val |= BIT2;
4571 else
4572 val &= ~BIT2;
4573 wr_reg8(info, VCR, val);
4574}
4575
4576/*
4577 * free range of receive DMA buffers (i to last)
4578 */
4579static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4580{
4581 int done = 0;
4582
4583 while(!done) {
4584 /* reset current buffer for reuse */
4585 info->rbufs[i].status = 0;
4586 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4587 if (i == last)
4588 done = 1;
4589 if (++i == info->rbuf_count)
4590 i = 0;
4591 }
4592 info->rbuf_current = i;
4593}
4594
4595/*
4596 * mark all receive DMA buffers as free
4597 */
4598static void reset_rbufs(struct slgt_info *info)
4599{
4600 free_rbufs(info, 0, info->rbuf_count - 1);
4601 info->rbuf_fill_index = 0;
4602 info->rbuf_fill_count = 0;
4603}
4604
4605/*
4606 * pass receive HDLC frame to upper layer
4607 *
4608 * return true if frame available, otherwise false
4609 */
4610static bool rx_get_frame(struct slgt_info *info)
4611{
4612 unsigned int start, end;
4613 unsigned short status;
4614 unsigned int framesize = 0;
4615 unsigned long flags;
4616 struct tty_struct *tty = info->port.tty;
4617 unsigned char addr_field = 0xff;
4618 unsigned int crc_size = 0;
4619
4620 switch (info->params.crc_type & HDLC_CRC_MASK) {
4621 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4622 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4623 }
4624
4625check_again:
4626
4627 framesize = 0;
4628 addr_field = 0xff;
4629 start = end = info->rbuf_current;
4630
4631 for (;;) {
4632 if (!desc_complete(info->rbufs[end]))
4633 goto cleanup;
4634
4635 if (framesize == 0 && info->params.addr_filter != 0xff)
4636 addr_field = info->rbufs[end].buf[0];
4637
4638 framesize += desc_count(info->rbufs[end]);
4639
4640 if (desc_eof(info->rbufs[end]))
4641 break;
4642
4643 if (++end == info->rbuf_count)
4644 end = 0;
4645
4646 if (end == info->rbuf_current) {
4647 if (info->rx_enabled){
4648 spin_lock_irqsave(&info->lock,flags);
4649 rx_start(info);
4650 spin_unlock_irqrestore(&info->lock,flags);
4651 }
4652 goto cleanup;
4653 }
4654 }
4655
4656 /* status
4657 *
4658 * 15 buffer complete
4659 * 14..06 reserved
4660 * 05..04 residue
4661 * 02 eof (end of frame)
4662 * 01 CRC error
4663 * 00 abort
4664 */
4665 status = desc_status(info->rbufs[end]);
4666
4667 /* ignore CRC bit if not using CRC (bit is undefined) */
4668 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4669 status &= ~BIT1;
4670
4671 if (framesize == 0 ||
4672 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4673 free_rbufs(info, start, end);
4674 goto check_again;
4675 }
4676
4677 if (framesize < (2 + crc_size) || status & BIT0) {
4678 info->icount.rxshort++;
4679 framesize = 0;
4680 } else if (status & BIT1) {
4681 info->icount.rxcrc++;
4682 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4683 framesize = 0;
4684 }
4685
4686#if SYNCLINK_GENERIC_HDLC
4687 if (framesize == 0) {
4688 info->netdev->stats.rx_errors++;
4689 info->netdev->stats.rx_frame_errors++;
4690 }
4691#endif
4692
4693 DBGBH(("%s rx frame status=%04X size=%d\n",
4694 info->device_name, status, framesize));
4695 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4696
4697 if (framesize) {
4698 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4699 framesize -= crc_size;
4700 crc_size = 0;
4701 }
4702
4703 if (framesize > info->max_frame_size + crc_size)
4704 info->icount.rxlong++;
4705 else {
4706 /* copy dma buffer(s) to contiguous temp buffer */
4707 int copy_count = framesize;
4708 int i = start;
4709 unsigned char *p = info->tmp_rbuf;
4710 info->tmp_rbuf_count = framesize;
4711
4712 info->icount.rxok++;
4713
4714 while(copy_count) {
4715 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4716 memcpy(p, info->rbufs[i].buf, partial_count);
4717 p += partial_count;
4718 copy_count -= partial_count;
4719 if (++i == info->rbuf_count)
4720 i = 0;
4721 }
4722
4723 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4724 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4725 framesize++;
4726 }
4727
4728#if SYNCLINK_GENERIC_HDLC
4729 if (info->netcount)
4730 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4731 else
4732#endif
4733 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4734 }
4735 }
4736 free_rbufs(info, start, end);
4737 return true;
4738
4739cleanup:
4740 return false;
4741}
4742
4743/*
4744 * pass receive buffer (RAW synchronous mode) to tty layer
4745 * return true if buffer available, otherwise false
4746 */
4747static bool rx_get_buf(struct slgt_info *info)
4748{
4749 unsigned int i = info->rbuf_current;
4750 unsigned int count;
4751
4752 if (!desc_complete(info->rbufs[i]))
4753 return false;
4754 count = desc_count(info->rbufs[i]);
4755 switch(info->params.mode) {
4756 case MGSL_MODE_MONOSYNC:
4757 case MGSL_MODE_BISYNC:
4758 case MGSL_MODE_XSYNC:
4759 /* ignore residue in byte synchronous modes */
4760 if (desc_residue(info->rbufs[i]))
4761 count--;
4762 break;
4763 }
4764 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4765 DBGINFO(("rx_get_buf size=%d\n", count));
4766 if (count)
4767 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4768 info->flag_buf, count);
4769 free_rbufs(info, i, i);
4770 return true;
4771}
4772
4773static void reset_tbufs(struct slgt_info *info)
4774{
4775 unsigned int i;
4776 info->tbuf_current = 0;
4777 for (i=0 ; i < info->tbuf_count ; i++) {
4778 info->tbufs[i].status = 0;
4779 info->tbufs[i].count = 0;
4780 }
4781}
4782
4783/*
4784 * return number of free transmit DMA buffers
4785 */
4786static unsigned int free_tbuf_count(struct slgt_info *info)
4787{
4788 unsigned int count = 0;
4789 unsigned int i = info->tbuf_current;
4790
4791 do
4792 {
4793 if (desc_count(info->tbufs[i]))
4794 break; /* buffer in use */
4795 ++count;
4796 if (++i == info->tbuf_count)
4797 i=0;
4798 } while (i != info->tbuf_current);
4799
4800 /* if tx DMA active, last zero count buffer is in use */
4801 if (count && (rd_reg32(info, TDCSR) & BIT0))
4802 --count;
4803
4804 return count;
4805}
4806
4807/*
4808 * return number of bytes in unsent transmit DMA buffers
4809 * and the serial controller tx FIFO
4810 */
4811static unsigned int tbuf_bytes(struct slgt_info *info)
4812{
4813 unsigned int total_count = 0;
4814 unsigned int i = info->tbuf_current;
4815 unsigned int reg_value;
4816 unsigned int count;
4817 unsigned int active_buf_count = 0;
4818
4819 /*
4820 * Add descriptor counts for all tx DMA buffers.
4821 * If count is zero (cleared by DMA controller after read),
4822 * the buffer is complete or is actively being read from.
4823 *
4824 * Record buf_count of last buffer with zero count starting
4825 * from current ring position. buf_count is mirror
4826 * copy of count and is not cleared by serial controller.
4827 * If DMA controller is active, that buffer is actively
4828 * being read so add to total.
4829 */
4830 do {
4831 count = desc_count(info->tbufs[i]);
4832 if (count)
4833 total_count += count;
4834 else if (!total_count)
4835 active_buf_count = info->tbufs[i].buf_count;
4836 if (++i == info->tbuf_count)
4837 i = 0;
4838 } while (i != info->tbuf_current);
4839
4840 /* read tx DMA status register */
4841 reg_value = rd_reg32(info, TDCSR);
4842
4843 /* if tx DMA active, last zero count buffer is in use */
4844 if (reg_value & BIT0)
4845 total_count += active_buf_count;
4846
4847 /* add tx FIFO count = reg_value[15..8] */
4848 total_count += (reg_value >> 8) & 0xff;
4849
4850 /* if transmitter active add one byte for shift register */
4851 if (info->tx_active)
4852 total_count++;
4853
4854 return total_count;
4855}
4856
4857/*
4858 * load data into transmit DMA buffer ring and start transmitter if needed
4859 * return true if data accepted, otherwise false (buffers full)
4860 */
4861static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4862{
4863 unsigned short count;
4864 unsigned int i;
4865 struct slgt_desc *d;
4866
4867 /* check required buffer space */
4868 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4869 return false;
4870
4871 DBGDATA(info, buf, size, "tx");
4872
4873 /*
4874 * copy data to one or more DMA buffers in circular ring
4875 * tbuf_start = first buffer for this data
4876 * tbuf_current = next free buffer
4877 *
4878 * Copy all data before making data visible to DMA controller by
4879 * setting descriptor count of the first buffer.
4880 * This prevents an active DMA controller from reading the first DMA
4881 * buffers of a frame and stopping before the final buffers are filled.
4882 */
4883
4884 info->tbuf_start = i = info->tbuf_current;
4885
4886 while (size) {
4887 d = &info->tbufs[i];
4888
4889 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4890 memcpy(d->buf, buf, count);
4891
4892 size -= count;
4893 buf += count;
4894
4895 /*
4896 * set EOF bit for last buffer of HDLC frame or
4897 * for every buffer in raw mode
4898 */
4899 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4900 info->params.mode == MGSL_MODE_RAW)
4901 set_desc_eof(*d, 1);
4902 else
4903 set_desc_eof(*d, 0);
4904
4905 /* set descriptor count for all but first buffer */
4906 if (i != info->tbuf_start)
4907 set_desc_count(*d, count);
4908 d->buf_count = count;
4909
4910 if (++i == info->tbuf_count)
4911 i = 0;
4912 }
4913
4914 info->tbuf_current = i;
4915
4916 /* set first buffer count to make new data visible to DMA controller */
4917 d = &info->tbufs[info->tbuf_start];
4918 set_desc_count(*d, d->buf_count);
4919
4920 /* start transmitter if needed and update transmit timeout */
4921 if (!info->tx_active)
4922 tx_start(info);
4923 update_tx_timer(info);
4924
4925 return true;
4926}
4927
4928static int register_test(struct slgt_info *info)
4929{
4930 static unsigned short patterns[] =
4931 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4932 static unsigned int count = ARRAY_SIZE(patterns);
4933 unsigned int i;
4934 int rc = 0;
4935
4936 for (i=0 ; i < count ; i++) {
4937 wr_reg16(info, TIR, patterns[i]);
4938 wr_reg16(info, BDR, patterns[(i+1)%count]);
4939 if ((rd_reg16(info, TIR) != patterns[i]) ||
4940 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4941 rc = -ENODEV;
4942 break;
4943 }
4944 }
4945 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4946 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4947 return rc;
4948}
4949
4950static int irq_test(struct slgt_info *info)
4951{
4952 unsigned long timeout;
4953 unsigned long flags;
4954 struct tty_struct *oldtty = info->port.tty;
4955 u32 speed = info->params.data_rate;
4956
4957 info->params.data_rate = 921600;
4958 info->port.tty = NULL;
4959
4960 spin_lock_irqsave(&info->lock, flags);
4961 async_mode(info);
4962 slgt_irq_on(info, IRQ_TXIDLE);
4963
4964 /* enable transmitter */
4965 wr_reg16(info, TCR,
4966 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4967
4968 /* write one byte and wait for tx idle */
4969 wr_reg16(info, TDR, 0);
4970
4971 /* assume failure */
4972 info->init_error = DiagStatus_IrqFailure;
4973 info->irq_occurred = false;
4974
4975 spin_unlock_irqrestore(&info->lock, flags);
4976
4977 timeout=100;
4978 while(timeout-- && !info->irq_occurred)
4979 msleep_interruptible(10);
4980
4981 spin_lock_irqsave(&info->lock,flags);
4982 reset_port(info);
4983 spin_unlock_irqrestore(&info->lock,flags);
4984
4985 info->params.data_rate = speed;
4986 info->port.tty = oldtty;
4987
4988 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4989 return info->irq_occurred ? 0 : -ENODEV;
4990}
4991
4992static int loopback_test_rx(struct slgt_info *info)
4993{
4994 unsigned char *src, *dest;
4995 int count;
4996
4997 if (desc_complete(info->rbufs[0])) {
4998 count = desc_count(info->rbufs[0]);
4999 src = info->rbufs[0].buf;
5000 dest = info->tmp_rbuf;
5001
5002 for( ; count ; count-=2, src+=2) {
5003 /* src=data byte (src+1)=status byte */
5004 if (!(*(src+1) & (BIT9 + BIT8))) {
5005 *dest = *src;
5006 dest++;
5007 info->tmp_rbuf_count++;
5008 }
5009 }
5010 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5011 return 1;
5012 }
5013 return 0;
5014}
5015
5016static int loopback_test(struct slgt_info *info)
5017{
5018#define TESTFRAMESIZE 20
5019
5020 unsigned long timeout;
5021 u16 count = TESTFRAMESIZE;
5022 unsigned char buf[TESTFRAMESIZE];
5023 int rc = -ENODEV;
5024 unsigned long flags;
5025
5026 struct tty_struct *oldtty = info->port.tty;
5027 MGSL_PARAMS params;
5028
5029 memcpy(&params, &info->params, sizeof(params));
5030
5031 info->params.mode = MGSL_MODE_ASYNC;
5032 info->params.data_rate = 921600;
5033 info->params.loopback = 1;
5034 info->port.tty = NULL;
5035
5036 /* build and send transmit frame */
5037 for (count = 0; count < TESTFRAMESIZE; ++count)
5038 buf[count] = (unsigned char)count;
5039
5040 info->tmp_rbuf_count = 0;
5041 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5042
5043 /* program hardware for HDLC and enabled receiver */
5044 spin_lock_irqsave(&info->lock,flags);
5045 async_mode(info);
5046 rx_start(info);
5047 tx_load(info, buf, count);
5048 spin_unlock_irqrestore(&info->lock, flags);
5049
5050 /* wait for receive complete */
5051 for (timeout = 100; timeout; --timeout) {
5052 msleep_interruptible(10);
5053 if (loopback_test_rx(info)) {
5054 rc = 0;
5055 break;
5056 }
5057 }
5058
5059 /* verify received frame length and contents */
5060 if (!rc && (info->tmp_rbuf_count != count ||
5061 memcmp(buf, info->tmp_rbuf, count))) {
5062 rc = -ENODEV;
5063 }
5064
5065 spin_lock_irqsave(&info->lock,flags);
5066 reset_adapter(info);
5067 spin_unlock_irqrestore(&info->lock,flags);
5068
5069 memcpy(&info->params, &params, sizeof(info->params));
5070 info->port.tty = oldtty;
5071
5072 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5073 return rc;
5074}
5075
5076static int adapter_test(struct slgt_info *info)
5077{
5078 DBGINFO(("testing %s\n", info->device_name));
5079 if (register_test(info) < 0) {
5080 printk("register test failure %s addr=%08X\n",
5081 info->device_name, info->phys_reg_addr);
5082 } else if (irq_test(info) < 0) {
5083 printk("IRQ test failure %s IRQ=%d\n",
5084 info->device_name, info->irq_level);
5085 } else if (loopback_test(info) < 0) {
5086 printk("loopback test failure %s\n", info->device_name);
5087 }
5088 return info->init_error;
5089}
5090
5091/*
5092 * transmit timeout handler
5093 */
5094static void tx_timeout(struct timer_list *t)
5095{
5096 struct slgt_info *info = from_timer(info, t, tx_timer);
5097 unsigned long flags;
5098
5099 DBGINFO(("%s tx_timeout\n", info->device_name));
5100 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5101 info->icount.txtimeout++;
5102 }
5103 spin_lock_irqsave(&info->lock,flags);
5104 tx_stop(info);
5105 spin_unlock_irqrestore(&info->lock,flags);
5106
5107#if SYNCLINK_GENERIC_HDLC
5108 if (info->netcount)
5109 hdlcdev_tx_done(info);
5110 else
5111#endif
5112 bh_transmit(info);
5113}
5114
5115/*
5116 * receive buffer polling timer
5117 */
5118static void rx_timeout(struct timer_list *t)
5119{
5120 struct slgt_info *info = from_timer(info, t, rx_timer);
5121 unsigned long flags;
5122
5123 DBGINFO(("%s rx_timeout\n", info->device_name));
5124 spin_lock_irqsave(&info->lock, flags);
5125 info->pending_bh |= BH_RECEIVE;
5126 spin_unlock_irqrestore(&info->lock, flags);
5127 bh_handler(&info->task);
5128}
5129