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192.168.1.100 / T800 / cb1584c1e9456de0fa1c18f6c78c38afbbbcb86d / . / src / tinysys / medmcu / drivers / RV33_A / include / encoding.h
blob: 9e5618687fcd14b61a037faea587442e9dd5f83d [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly
9 * prohibited.
10 */
11/* MediaTek Inc. (C) 2018. All rights reserved.
12 *
13 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
14 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
15 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
16 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
19 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
20 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
21 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
22 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY
23 * ACKNOWLEDGES THAT IT IS RECEIVER\'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY
24 * THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK
25 * SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO
26 * RECEIVER\'S SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN
27 * FORUM. RECEIVER\'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK\'S ENTIRE AND
28 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER
29 * WILL BE, AT MEDIATEK\'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE
30 * AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
31 * RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
32 *
33 * The following software/firmware and/or related documentation
34 * ("MediaTek Software") have been modified by MediaTek Inc. All revisions are
35 * subject to any receiver\'s applicable license agreements with MediaTek Inc.
36 */
37
38#ifndef _ENCODING_H_
39#define _ENCODING_H_
40
41#define __track_irq
42#define __two_levels_exception
43
44#define configExtension_F
45//#define configExtension_ACC /* unmark if required */
46#define configExtension_UAM
47
48#define configExtension_FastCTX
49#define __branch_prediction
50
51#ifdef configExtension_F
52#define RNE (0x0 << 5) /* round to nearest, tie to even */
53#define RTZ (0x1 << 5) /* round toward zero */
54#define RDN (0x2 << 5) /* round down */
55#define RUP (0x3 << 5) /* round up */
56#define RMM (0x4 << 5) /* round to nearest, tie to max magnitude */
57#define __rounding_mode RNE
58#endif /* configExtension_F */
59
60#ifdef configExtension_F
61#define F_reg 32
62#define F_fcsr 1
63#define __kstack_ext_reg_F (0x1 << 31)
64#ifdef configExtension_FastCTX
65#define FF
66#endif /* configExtension_FastCTX */
67#else
68#define F_reg 0
69#define F_fcsr 0
70#define __kstack_ext_reg_F 0
71#endif /* configExtension_F */
72#define F_reg_ctx (F_reg + F_fcsr)
73
74#ifdef configExtension_ACC
75#define ACC_reg 4*3
76#define __kstack_ext_reg_ACC (0x1 << 30)
77#ifdef configExtension_FastCTX
78#define FACC
79#endif /* configExtension_FastCTX */
80#else
81#define ACC_reg 0
82#define __kstack_ext_reg_ACC 0
83#endif /* configExtension_ACC */
84#define ACC_reg_ctx ACC_reg
85
86#ifdef configExtension_UAM
87#define UAM_reg 4*3
88#define __kstack_ext_reg_UAM (0x1 << 29)
89#ifdef configExtension_FastCTX
90#define FUAM
91#endif /* configExtension_FastCTX */
92#else
93#define UAM_reg 0
94#define __kstack_ext_reg_UAM 0
95#endif /* configExtension_UAM */
96#define UAM_reg_ctx UAM_reg
97
98
99#ifdef configExtension_HWDLP
100 #define HWDLP_reg 2*3
101 #define HWDLP_lf 1
102 #define __kstack_ext_reg_HWDLP (0x1 << 25)
103 #ifdef configExtension_FastCTX
104 #define FHWDLP
105 #define __kstack_ext_reg_FHWDLP (0x1 << 24)
106 #else
107 #define __kstack_ext_reg_FHWDLP 0
108 #endif /* configExtension_FastCTX */
109#else
110 #define HWDLP_reg 0
111 #define HWDLP_lf 0
112 #define __kstack_ext_reg_HWDLP 0
113 #define __kstack_ext_reg_FHWDLP 0
114#endif /* configExtension_HWDLP */
115#define HWDLP_reg_ctx (HWDLP_reg + HWDLP_lf)
116
117
118#define X_reg 32
119#define X_reg_ctx (X_reg+1)
120
121#define __kstack_ext_reg_value (__kstack_ext_reg_F | __kstack_ext_reg_ACC \
122 | __kstack_ext_reg_UAM)
123
124#define MSTATUS_UIE 0x00000001
125#define MSTATUS_SIE 0x00000002
126#define MSTATUS_HIE 0x00000004
127#define MSTATUS_MIE 0x00000008
128#define MSTATUS_UPIE 0x00000010
129#define MSTATUS_SPIE 0x00000020
130#define MSTATUS_HPIE 0x00000040
131#define MSTATUS_MPIE 0x00000080
132#define MSTATUS_SPP 0x00000100
133#define MSTATUS_HPP 0x00000600
134#define MSTATUS_MPP 0x00001800
135#define MSTATUS_FS 0x00006000
136#define MSTATUS_FS_I 0x00002000
137#define MSTATUS_FS_C 0x00004000
138#define MSTATUS_FS_D 0x00006000
139#define MSTATUS_XS 0x00018000
140#define MSTATUS_XS_I 0x00008000
141#define MSTATUS_XS_C 0x00010000
142#define MSTATUS_XS_D 0x00018000
143#define MSTATUS_MPRV 0x00020000
144#define MSTATUS_PUM 0x00040000
145#define MSTATUS_MXR 0x00080000
146#define MSTATUS_ACS 0x01800000
147#define MSTATUS_ACS_I 0x00800000
148#define MSTATUS_ACS_C 0x01000000
149#define MSTATUS_ACS_D 0x01800000
150#define MSTATUS_UAS 0x06000000
151#define MSTATUS_UAS_I 0x02000000
152#define MSTATUS_UAS_C 0x04000000
153#define MSTATUS_UAS_D 0x06000000
154#define MSTATUS_VM 0x1F000000
155#define MSTATUS32_SD 0x80000000
156#define MSTATUS64_SD 0x8000000000000000
157
158#define SSTATUS_UIE 0x00000001
159#define SSTATUS_SIE 0x00000002
160#define SSTATUS_UPIE 0x00000010
161#define SSTATUS_SPIE 0x00000020
162#define SSTATUS_SPP 0x00000100
163#define SSTATUS_FS 0x00006000
164#define SSTATUS_XS 0x00018000
165#define SSTATUS_PUM 0x00040000
166#define SSTATUS32_SD 0x80000000
167#define SSTATUS64_SD 0x8000000000000000
168
169#define DCSR_XDEBUGVER (3U<<30)
170#define DCSR_NDRESET (1<<29)
171#define DCSR_FULLRESET (1<<28)
172#define DCSR_EBREAKM (1<<15)
173#define DCSR_EBREAKH (1<<14)
174#define DCSR_EBREAKS (1<<13)
175#define DCSR_EBREAKU (1<<12)
176#define DCSR_STOPCYCLE (1<<10)
177#define DCSR_STOPTIME (1<<9)
178#define DCSR_CAUSE (7<<6)
179#define DCSR_DEBUGINT (1<<5)
180#define DCSR_HALT (1<<3)
181#define DCSR_STEP (1<<2)
182#define DCSR_PRV (3<<0)
183
184#define DCSR_CAUSE_NONE 0
185#define DCSR_CAUSE_SWBP 1
186#define DCSR_CAUSE_HWBP 2
187#define DCSR_CAUSE_DEBUGINT 3
188#define DCSR_CAUSE_STEP 4
189#define DCSR_CAUSE_HALT 5
190
191#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
192#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
193#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
194
195#define MCONTROL_SELECT (1<<19)
196#define MCONTROL_TIMING (1<<18)
197#define MCONTROL_ACTION (0x3f<<12)
198#define MCONTROL_CHAIN (1<<11)
199#define MCONTROL_MATCH (0xf<<7)
200#define MCONTROL_M (1<<6)
201#define MCONTROL_H (1<<5)
202#define MCONTROL_S (1<<4)
203#define MCONTROL_U (1<<3)
204#define MCONTROL_EXECUTE (1<<2)
205#define MCONTROL_STORE (1<<1)
206#define MCONTROL_LOAD (1<<0)
207
208#define MCONTROL_TYPE_NONE 0
209#define MCONTROL_TYPE_MATCH 2
210
211#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
212#define MCONTROL_ACTION_DEBUG_MODE 1
213#define MCONTROL_ACTION_TRACE_START 2
214#define MCONTROL_ACTION_TRACE_STOP 3
215#define MCONTROL_ACTION_TRACE_EMIT 4
216
217#define MCONTROL_MATCH_EQUAL 0
218#define MCONTROL_MATCH_NAPOT 1
219#define MCONTROL_MATCH_GE 2
220#define MCONTROL_MATCH_LT 3
221#define MCONTROL_MATCH_MASK_LOW 4
222#define MCONTROL_MATCH_MASK_HIGH 5
223
224#define MIP_SSIP (1 << IRQ_S_SOFT)
225#define MIP_HSIP (1 << IRQ_H_SOFT)
226#define MIP_MSIP (1 << IRQ_M_SOFT)
227#define MIP_STIP (1 << IRQ_S_TIMER)
228#define MIP_HTIP (1 << IRQ_H_TIMER)
229#define MIP_MTIP (1 << IRQ_M_TIMER)
230#define MIP_SEIP (1 << IRQ_S_EXT)
231#define MIP_HEIP (1 << IRQ_H_EXT)
232#define MIP_MEIP (1 << IRQ_M_EXT)
233#define MIP_LTIP (1 << IRQ_L_TIMER)
234#define MIP_AXI (1 << IRQ_AXI)
235#define MIP_LINT_0 (1 << IRQ_LINT_0)
236#define MIP_LINT_1 (1 << IRQ_LINT_1)
237#define MIP_LINT_2 (1 << IRQ_LINT_2)
238#define MIP_LINT_3 (1 << IRQ_LINT_3)
239#define MIP_LINT_4 (1 << IRQ_LINT_4)
240#define MIP_LINT_5 (1 << IRQ_LINT_5)
241#define MIP_LINT_6 (1 << IRQ_LINT_6)
242#define MIP_LINT_7 (1 << IRQ_LINT_7)
243
244#define SIP_SSIP MIP_SSIP
245#define SIP_STIP MIP_STIP
246
247#define PRV_U 0
248#define PRV_S 1
249#define PRV_H 2
250#define PRV_M 3
251
252#define VM_MBARE 0
253#define VM_MBB 1
254#define VM_MBBID 2
255#define VM_SV32 8
256#define VM_SV39 9
257#define VM_SV48 10
258
259#define IRQ_S_SOFT 1
260#define IRQ_H_SOFT 2
261#define IRQ_M_SOFT 3
262#define IRQ_S_TIMER 5
263#define IRQ_H_TIMER 6
264#define IRQ_M_TIMER 7
265#define IRQ_S_EXT 9
266#define IRQ_H_EXT 10
267#define IRQ_M_EXT 11
268#define IRQ_COP 12
269#define IRQ_HOST 13
270#define IRQ_L_TIMER 16
271#define IRQ_AXI 17
272#define IRQ_LINT_0 24
273#define IRQ_LINT_1 25
274#define IRQ_LINT_2 26
275#define IRQ_LINT_3 27
276#define IRQ_LINT_4 28
277#define IRQ_LINT_5 29
278#define IRQ_LINT_6 30
279#define IRQ_LINT_7 31
280
281#define DEFAULT_RSTVEC 0x00001000
282#define DEFAULT_NMIVEC 0x00001004
283#define DEFAULT_MTVEC 0x00001010
284#define CONFIG_STRING_ADDR 0x0000100C
285#define EXT_IO_BASE 0x40000000
286#define DRAM_BASE 0x80000000
287
288/* page table entry (PTE) fields */
289#define PTE_V 0x001 /* Valid */
290#define PTE_R 0x002 /* Read */
291#define PTE_W 0x004 /* Write */
292#define PTE_X 0x008 /* Execute */
293#define PTE_U 0x010 /* User */
294#define PTE_G 0x020 /* Global */
295#define PTE_A 0x040 /* Accessed */
296#define PTE_D 0x080 /* Dirty */
297#define PTE_SOFT 0x300 /* Reserved for Software */
298
299#define PTE_PPN_SHIFT 10
300
301#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
302
303#ifdef __riscv
304
305#ifdef __riscv64
306#define MSTATUS_SD MSTATUS64_SD
307#define SSTATUS_SD SSTATUS64_SD
308#define RISCV_PGLEVEL_BITS 9
309#else
310#define MSTATUS_SD MSTATUS32_SD
311#define SSTATUS_SD SSTATUS32_SD
312#define RISCV_PGLEVEL_BITS 10
313#endif
314#define RISCV_PGSHIFT 12
315#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
316
317#ifndef __ASSEMBLER__
318
319#ifdef __GNUC__
320
321#define read_csr(reg) ({ unsigned long __tmp; \
322 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
323 __tmp; })
324
325#define write_csr(reg, val) ({ \
326 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
327 asm volatile ("csrwi " #reg ", %0" :: "i"(val)); \
328 else \
329 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
330
331#define mrv_read_csr(reg) ({ unsigned long __tmp; \
332 asm volatile("csrr %0, %1" : "=r"(__tmp) : "i"(reg)); \
333 __tmp; })
334
335#define mrv_write_csr(reg, val) ({ \
336 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
337 asm volatile ("csrwi %0, %1" :: "i"(reg), "i"(val)); \
338 else \
339 asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val)); })
340
341#define mrv_set_csr(reg, bit) ({ unsigned long __tmp; \
342 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
343 asm volatile ("csrrsi %0, %1, %2" : "=r"(__tmp) : "i"(reg), "i"(bit)); \
344 else \
345 asm volatile ("csrrs %0, %1, %2" : "=r"(__tmp) : "i"(reg), "r"(bit)); \
346 __tmp; })
347
348#define mrv_clear_csr(reg, bit) ({ unsigned long __tmp; \
349 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
350 asm volatile ("csrrci %0, %1, %2" : "=r"(__tmp) : "i"(reg), "i"(bit)); \
351 else \
352 asm volatile ("csrrc %0, %1, %2" : "=r"(__tmp) : "i"(reg), "r"(bit)); \
353 __tmp; })
354
355#define swap_csr(reg, val) ({ unsigned long __tmp; \
356 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
357 asm volatile ("csrrwi %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
358 else \
359 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
360 __tmp; })
361
362#define set_csr(reg, bit) ({ unsigned long __tmp; \
363 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
364 asm volatile ("csrrsi %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
365 else \
366 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
367 __tmp; })
368
369#define clear_csr(reg, bit) ({ unsigned long __tmp; \
370 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
371 asm volatile ("csrrci %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
372 else \
373 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
374 __tmp; })
375
376#ifndef CFG_MRV_PATCH1
377#define mrv_icache_invalid_all() ({ unsigned long __tmp; \
378 asm volatile("li %0, 0x8\n" "cop %0": "=r"(__tmp)); \
379 })
380
381#define mrv_dcache_invalid_all() ({ unsigned long __tmp; \
382 asm volatile("li %0, 0x18\n" "cop %0": "=r"(__tmp)); \
383 })
384
385#define mrv_icache_invalid_addr(addr) ({ unsigned long __tmp; \
386 asm volatile("addi %0, %1, 0x9\n" "cop %0": "=r"(__tmp): "r"(addr)); \
387 })
388
389#define mrv_dcache_invalid_addr(addr) ({ unsigned long __tmp; \
390 asm volatile("addi %0, %1, 0x19\n" "cop %0": "=r"(__tmp): "r"(addr)); \
391 })
392
393#define mrv_dcache_flush_all() ({ unsigned long __tmp; \
394 asm volatile("li %0, 0x14\n" "cop %0": "=r"(__tmp)); \
395 })
396
397#define mrv_dcache_flush_addr(addr) ({ unsigned long __tmp; \
398 asm volatile("addi %0, %1, 0x15\n" "cop %0": "=r"(__tmp): "r"(addr)); \
399 })
400
401#define mrv_icache_barrier() ({ asm volatile("cop zero"); \
402 })
403
404#define mrv_dcache_barrier() ({ unsigned long __tmp; \
405 asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
406 })
407
408#define mrv_icache_invalid_multi_addr(addr, length) ({ \
409 unsigned long __tmp = addr + 0x9; \
410 unsigned long __end_addr = __tmp + length; \
411 configASSERT(!((addr | length) & 0x1f)); \
412 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
413 : "+r"(__tmp): "r"(__end_addr)); \
414 })
415
416#define mrv_dcache_invalid_multi_addr(addr, length) ({ \
417 unsigned long __tmp = addr + 0x19; \
418 unsigned long __end_addr = __tmp + length; \
419 configASSERT(!((addr | length) & 0x1f)); \
420 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
421 : "+r"(__tmp): "r"(__end_addr)); \
422 })
423
424#define mrv_dcache_flush_multi_addr(addr, length) ({ \
425 unsigned long __tmp = addr + 0x15; \
426 unsigned long __end_addr = __tmp + length; \
427 configASSERT(!((addr | length) & 0x1f)); \
428 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
429 : "+r"(__tmp): "r"(__end_addr)); \
430 })
431#else
432#define mrv_icache_invalid_all() ({ unsigned long __tmp; \
433 unsigned long _flags; \
434 _flags = vPortSetInterruptMask(); \
435 asm volatile("li %0, 0x8\n" "cop %0": "=r"(__tmp)); \
436 vPortClearInterruptMask(_flags); \
437 })
438
439#define mrv_dcache_invalid_all() ({ unsigned long __tmp; \
440 unsigned long _flags; \
441 _flags = vPortSetInterruptMask(); \
442 asm volatile("li %0, 0x18\n" "cop %0": "=r"(__tmp)); \
443 vPortClearInterruptMask(_flags); \
444 })
445
446#define mrv_icache_invalid_addr(addr) ({ unsigned long __tmp; \
447 unsigned long _flags; \
448 _flags = vPortSetInterruptMask(); \
449 asm volatile("addi %0, %1, 0x9\n" "cop %0": "=r"(__tmp): "r"(addr)); \
450 vPortClearInterruptMask(_flags); \
451 })
452
453#define mrv_dcache_invalid_addr(addr) ({ unsigned long __tmp; \
454 unsigned long _flags; \
455 _flags = vPortSetInterruptMask(); \
456 asm volatile("addi %0, %1, 0x19\n" "cop %0": "=r"(__tmp): "r"(addr)); \
457 vPortClearInterruptMask(_flags); \
458 })
459
460#define mrv_dcache_flush_all() ({ unsigned long __tmp; \
461 unsigned long _flags; \
462 _flags = vPortSetInterruptMask(); \
463 asm volatile("li %0, 0x14\n" "cop %0": "=r"(__tmp)); \
464 vPortClearInterruptMask(_flags); \
465 })
466
467#define mrv_dcache_flush_addr(addr) ({ unsigned long __tmp; \
468 unsigned long _flags; \
469 _flags = vPortSetInterruptMask(); \
470 asm volatile("addi %0, %1, 0x15\n" "cop %0": "=r"(__tmp): "r"(addr)); \
471 vPortClearInterruptMask(_flags); \
472 })
473
474#define mrv_icache_barrier() ({ asm volatile("cop zero"); \
475 })
476
477#define mrv_dcache_barrier() ({ unsigned long __tmp; \
478 asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
479 })
480
481#define mrv_icache_invalid_multi_addr(addr, length) ({ \
482 unsigned long __tmp = addr + 0x9; \
483 unsigned long __end_addr = __tmp + length; \
484 unsigned long _flags; \
485 configASSERT(!((addr | length) & 0x1f)); \
486 _flags = vPortSetInterruptMask(); \
487 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
488 : "+r"(__tmp): "r"(__end_addr)); \
489 vPortClearInterruptMask(_flags); \
490 })
491
492#define mrv_dcache_invalid_multi_addr(addr, length) ({ \
493 unsigned long __tmp = addr + 0x19; \
494 unsigned long __end_addr = __tmp + length; \
495 unsigned long _flags; \
496 configASSERT(!((addr | length) & 0x1f)); \
497 _flags = vPortSetInterruptMask(); \
498 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
499 : "+r"(__tmp): "r"(__end_addr)); \
500 vPortClearInterruptMask(_flags); \
501 })
502
503#define mrv_dcache_flush_multi_addr(addr, length) ({ \
504 unsigned long __tmp = addr + 0x15; \
505 unsigned long __end_addr = __tmp + length; \
506 unsigned long _flags; \
507 configASSERT(!((addr | length) & 0x1f)); \
508 _flags = vPortSetInterruptMask(); \
509 asm volatile("1:" "cop %0\n" "addi %0, %0, 0x20\n" "bne %0, %1, 1b\n" \
510 : "+r"(__tmp): "r"(__end_addr)); \
511 vPortClearInterruptMask(_flags); \
512 })
513#endif
514/* fence.i: flush all d-cache + invalid all icache */
515#define mrv_fence_i() \
516{ \
517 asm volatile("fence.i" ::: "memory"); \
518}
519
520/* fence: flush write buffer */
521#define mrv_fence_d() \
522{ \
523 asm volatile("fence" ::: "memory"); \
524}
525
526/* flush pipeline util barrier instr. finished */
527#define mrv_isb() ({ asm volatile("cop zero");})
528
529/* make sure memory r/w is finished */
530#define mrv_dmb() ({ unsigned long __tmp; \
531 asm volatile("li %0, 0x10\n" "cop %0": "=r"(__tmp)); \
532 })
533
534#define CACHE_LINE_SIZE 32
535#define CACHE_LINE_MASK (CACHE_LINE_SIZE - 1)
536#define CACHE_LINE_AND (~CACHE_LINE_MASK)
537#define cache_lower_addr(addr) (addr & CACHE_LINE_AND)
538#define cache_upper_size(addr, size) (((addr & CACHE_LINE_MASK) \
539 + size + CACHE_LINE_MASK) & CACHE_LINE_AND)
540
541#define L1TCM_REGION_RO __attribute__ ((section (".l1tcm_region_ro")))
542#define L1TCM_REGION_RW __attribute__ ((section (".l1tcm_region_rw")))
543
544#ifdef CFG_CACHE_SUPPORT
545#define SRAM_REGION_RO __attribute__ ((section (".sram_except_ro")))
546#define SRAM_REGION_RW __attribute__ ((section (".sram_except_rw")))
547#define SRAM_REGION_BSS __attribute__ ((section (".sram_except_bss")))
548#define SRAM_REGION_VARIABLE __attribute__ ((section (".sram_except_variable")))
549#define SRAM_REGION_FUNCTION __attribute__ ((section (".sram_except_func")))
550#define DRAM_REGION_RO __attribute__ ((section (".dram_region_ro")))
551#define DRAM_REGION_RW __attribute__ ((section (".dram_region_rw")))
552#define DRAM_REGION_BSS __attribute__ ((section (".dram_region_bss")))
553#define DRAM_REGION_VARIABLE __attribute__ ((section (".dram_region_variable")))
554#define DRAM_REGION_FUNCTION __attribute__ ((section (".dram_region_func")))
555
556#else
557#define SRAM_REGION_RO
558#define SRAM_REGION_RW
559#define SRAM_REGION_BSS
560#define SRAM_REGION_VARIABLE
561#define SRAM_REGION_FUNCTION
562#define DRAM_REGION_RO
563#define DRAM_REGION_RW
564#define DRAM_REGION_BSS
565#define DRAM_REGION_VARIABLE
566#define DRAM_REGION_FUNCTION
567#endif
568
569#define rdtime() read_csr(time)
570#define rdcycle() read_csr(cycle)
571#define rdinstret() read_csr(instret)
572
573#endif
574
575#endif
576
577#endif
578
579
580#define CLINT_BASE_ADDR 0x02000000
581#define CLINT_MSIP 0x0000
582#define CLINT_MSIP_size 0x4
583#define CLINT_MTIMECMP 0x4000
584#define CLINT_MTIMECMP_size 0x8
585#define CLINT_MTIME 0xBFF8
586#define CLINT_MTIME_size 0x8
587
588#define CSR_MTIME_BASE 0xbe0
589#define CSR_MTIME_MTMRCTR (CSR_MTIME_BASE + 0x000)
590#define CSR_MTIME_MTMRSTATUS (CSR_MTIME_BASE + 0x001)
591#define CSR_MTIME_MTMRCVR (CSR_MTIME_BASE + 0x002)
592#define CSR_MTIME_MTMRRVR (CSR_MTIME_BASE + 0x003)
593#define CSR_MTIME_MTMRDVR (CSR_MTIME_BASE + 0x004)
594
595/* centralized control enable */
596#define CSR_MCTREN (0x7c0)
597/* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */
598#define CSR_MCTREN_ICACHE 0
599#define CSR_MCTREN_DCACHE 1
600#define CSR_MCTREN_ITCM 2
601#define CSR_MCTREN_DTCM 3
602#define CSR_MCTREN_BTB 4
603#define CSR_MCTREN_RAS 5
604#define CSR_MCTREN_VIC 6
605#define CSR_MCTREN_CG 7
606#define CSR_MCTREN_MPU 8
607
608/* VIC */
609#define CSR_VIC_MICAUSE (0x5c0)
610#define CSR_VIC_MIASWI (0x5c1)
611#define CSR_VIC_MIEMS (0x5c2)
612#define CSR_VIC_MIDBGMASK (0x5c3)
613#define CSR_VIC_MIDBGWAKEUP (0x5c4)
614#define CSR_VIC_MIPEND_G0 (0x5d0)
615#define CSR_VIC_MIPEND_G1 (0x5d1)
616#define CSR_VIC_MIPEND_G2 (0x5d2)
617#define CSR_VIC_MIPEND_G3 (0x5d3)
618#define CSR_VIC_MIPEND_G4 (0x5d4)
619#define CSR_VIC_MIPEND_G5 (0x5d5)
620#define CSR_VIC_MIPEND_G6 (0x5d6)
621#define CSR_VIC_MIPEND_G7 (0x5d7)
622#define CSR_VIC_MIMASK_G0 (0x5d8)
623#define CSR_VIC_MIMASK_G1 (0x5d9)
624#define CSR_VIC_MIMASK_G2 (0x5da)
625#define CSR_VIC_MIMASK_G3 (0x5db)
626#define CSR_VIC_MIMASK_G4 (0x5dc)
627#define CSR_VIC_MIMASK_G5 (0x5dd)
628#define CSR_VIC_MIMASK_G6 (0x5de)
629#define CSR_VIC_MIMASK_G7 (0x5df)
630#define CSR_VIC_MIWAKEUP_G0 (0x5e0)
631#define CSR_VIC_MIWAKEUP_G1 (0x5e1)
632#define CSR_VIC_MIWAKEUP_G2 (0x5e2)
633#define CSR_VIC_MIWAKEUP_G3 (0x5e3)
634#define CSR_VIC_MIWAKEUP_G4 (0x5e4)
635#define CSR_VIC_MIWAKEUP_G5 (0x5e5)
636#define CSR_VIC_MIWAKEUP_G6 (0x5e6)
637#define CSR_VIC_MIWAKEUP_G7 (0x5e7)
638#define CSR_VIC_MILSEL_G0 (0x5e8)
639#define CSR_VIC_MILSEL_G1 (0x5e9)
640#define CSR_VIC_MILSEL_G2 (0x5ea)
641#define CSR_VIC_MILSEL_G3 (0x5eb)
642#define CSR_VIC_MILSEL_G4 (0x5ec)
643#define CSR_VIC_MILSEL_G5 (0x5ed)
644#define CSR_VIC_MILSEL_G6 (0x5ee)
645#define CSR_VIC_MILSEL_G7 (0x5ef)
646#define CSR_VIC_MIEMASK_G0 (0x5f0)
647#define CSR_VIC_MIEMASK_G1 (0x5f1)
648#define CSR_VIC_MIEMASK_G2 (0x5f2)
649#define CSR_VIC_MIEMASK_G3 (0x5f3)
650#define CSR_VIC_MIEMASK_G4 (0x5f4)
651#define CSR_VIC_MIEMASK_G5 (0x5f5)
652#define CSR_VIC_MIEMASK_G6 (0x5f6)
653#define CSR_VIC_MIEMASK_G7 (0x5f7)
654
655#define CSR_MIMABTCAU (0x7c5)
656#define CSR_MIMABTADDR (0x7c6)
657
658/* MPU */
659#define CSR_MPU_ENTRY_EN (0x9c0)
660#define CSR_MPU_LITCM (0x9dc)
661#define CSR_MPU_LDTCM (0x9dd)
662#define CSR_MPU_HITCM (0x9de)
663#define CSR_MPU_HDTCM (0x9df)
664#define CSR_MPU_L00 (0x9e0)
665#define CSR_MPU_L01 (0x9e1)
666#define CSR_MPU_L02 (0x9e2)
667#define CSR_MPU_L03 (0x9e3)
668#define CSR_MPU_L04 (0x9e4)
669#define CSR_MPU_L05 (0x9e5)
670#define CSR_MPU_L06 (0x9e6)
671#define CSR_MPU_L07 (0x9e7)
672#define CSR_MPU_L08 (0x9e8)
673#define CSR_MPU_L09 (0x9e9)
674#define CSR_MPU_L10 (0x9ea)
675#define CSR_MPU_L11 (0x9eb)
676#define CSR_MPU_L12 (0x9ec)
677#define CSR_MPU_L13 (0x9ed)
678#define CSR_MPU_L14 (0x9ee)
679#define CSR_MPU_L15 (0x9ef)
680#define CSR_MPU_LXX_P 5
681#define CSR_MPU_LXX_R 6
682#define CSR_MPU_LXX_W 7
683#define CSR_MPU_LXX_C 8
684#define CSR_MPU_LXX_B 9
685#define CSR_MPU_H00 (0x9f0)
686#define CSR_MPU_H01 (0x9f1)
687#define CSR_MPU_H02 (0x9f2)
688#define CSR_MPU_H03 (0x9f3)
689#define CSR_MPU_H04 (0x9f4)
690#define CSR_MPU_H05 (0x9f5)
691#define CSR_MPU_H06 (0x9f6)
692#define CSR_MPU_H07 (0x9f7)
693#define CSR_MPU_H08 (0x9f8)
694#define CSR_MPU_H09 (0x9f9)
695#define CSR_MPU_H10 (0x9fa)
696#define CSR_MPU_H11 (0x9fb)
697#define CSR_MPU_H12 (0x9fc)
698#define CSR_MPU_H13 (0x9fd)
699#define CSR_MPU_H14 (0x9fe)
700#define CSR_MPU_H15 (0x9ff)
701
702/* PMU */
703#define CSR_PMU_MPMUCTR (0xbc0)
704#define CSR_PMU_MPMUCTR_C 0
705#define CSR_PMU_MPMUCTR_I 1
706#define CSR_PMU_MPMUCTR_H3 2
707#define CSR_PMU_MPMUCTR_H4 3
708#define CSR_PMU_MPMUCTR_H5 4
709#define CSR_PMU_MPMUCTR_H6 5
710#define CSR_PMU_MPMUCTR_H7 6
711
712#define CSR_PMU_MCYCLE (0xb00)
713#define CSR_PMU_MINSTRET (0xb02)
714#define CSR_PMU_MHPMCOUNTER3 (0xb03)
715#define CSR_PMU_MHPMCOUNTER4 (0xb04)
716#define CSR_PMU_MHPMCOUNTER5 (0xb05)
717#define CSR_PMU_MHPMCOUNTER6 (0xb06)
718#define CSR_PMU_MHPMCOUNTER7 (0xb07)
719
720#define CSR_PMU_MCYCLEH (0xb80)
721#define CSR_PMU_MINSTRETH (0xb82)
722#define CSR_PMU_MHPMCOUNTER3H (0xb83)
723#define CSR_PMU_MHPMCOUNTER4H (0xb84)
724#define CSR_PMU_MHPMCOUNTER5H (0xb85)
725#define CSR_PMU_MHPMCOUNTER6H (0xb86)
726#define CSR_PMU_MHPMCOUNTER7H (0xb87)
727
728#define CSR_PMU_MHPMEVENT3 (0x323)
729#define CSR_PMU_MHPMEVENT4 (0x324)
730#define CSR_PMU_MHPMEVENT5 (0x325)
731#define CSR_PMU_MHPMEVENT6 (0x326)
732#define CSR_PMU_MHPMEVENT7 (0x327)
733
734#define CSR_PMU_MPHSWEVENT (0xbc1)
735
736/* CACHE */
737#define CSR_CACHE_ICACHEMSK (0x9c1)
738#define CSR_CACHE_ICACHESTATUS (0x9c2)
739#define CSR_CACHE_ICACHEOP (0x9c3)
740#define CSR_CACHE_I_OP_SEL 4
741#define CSR_CACHE_I_OP_MB 0x0
742#define CSR_CACHE_I_OP_CA 0x4
743#define CSR_CACHE_I_OP_C 0x5
744#define CSR_CACHE_I_OP_IA 0x8
745#define CSR_CACHE_I_OP_I 0x9
746#define CSR_CACHE_I_OP_FA 0xc
747#define CSR_CACHE_I_OP_F 0xd
748#define CSR_CACHE_DCACHEMSK (0x9c4)
749#define CSR_CACHE_DCACHESTATUS (0x9c5)
750#define CSR_CACHE_DCACHEOP (0x9c6)
751#define CSR_CACHE_D_OP_SEL CSR_CACHE_I_OP_SEL
752#define CSR_CACHE_D_OP_MB CSR_CACHE_I_OP_MB
753#define CSR_CACHE_D_OP_CA CSR_CACHE_I_OP_CA
754#define CSR_CACHE_D_OP_C CSR_CACHE_I_OP_C
755#define CSR_CACHE_D_OP_IA CSR_CACHE_I_OP_IA
756#define CSR_CACHE_D_OP_I CSR_CACHE_I_OP_I
757#define CSR_CACHE_D_OP_FA CSR_CACHE_I_OP_FA
758#define CSR_CACHE_D_OP_F CSR_CACHE_I_OP_F
759
760/* Trace Buffer */
761#define CSR_TBUF_MTBUFCTR (0xbd0)
762#define CSR_TBUF_MTBUFCTR_EN 0
763#define CSR_TBUF_MTBUFCTR_M 4
764#define CSR_TBUF_MTBUFCLR (0xbd1)
765#define CSR_TBUF_MTBUFSTR (0xbd2)
766#define CSR_TBUF_MTBUFSTR_WP 4
767#define CSR_TBUF_MTBUFSTR_OF 16
768#define CSR_TBUF_MTBUFRCMD (0xbd3)
769#define CSR_TBUF_MTBUFRCMD_LOG 0
770#define CSR_TBUF_MTBUFRCMD_RP 4
771#define CSR_TBUF_MTBUFRCMD_R 16
772#define CSR_TBUF_MTBUFRDATA (0xbd4)
773
774/* misc */
775#define CSR_UFLAG (0xbff)
776
777#define CSR_TIMER (0xc01)
778#define CSR_TIMERH (0xc81)
779#define CSR_MNPC (0xfc1)
780#define CSR_MVERID0 (0xfc2)
781#define CSR_MVERID1 (0xfc3)
782#define CSR_MVERID2 (0xfc4)
783#define CSR_MDBGBP0 (0x7d0)
784#define CSR_MDBGBP1 (0x7d1)
785#define CSR_MDBGBP2 (0x7d2)
786#define CSR_MDBGBP3 (0x7d3)
787#define CSR_MDBGBPC (0x7d4)
788
789#define CSR_MDBGWPM0 (0x7d8)
790#define CSR_MDBGWPM1 (0x7d9)
791#define CSR_MDBGWPM2 (0x7da)
792#define CSR_MDBGWPM3 (0x7db)
793
794
795#endif
796/* Automatically generated by parse-opcodes */
797#ifndef RISCV_ENCODING_H
798#define RISCV_ENCODING_H
799#define MATCH_BEQ 0x63
800#define MASK_BEQ 0x707f
801#define MATCH_BNE 0x1063
802#define MASK_BNE 0x707f
803#define MATCH_BLT 0x4063
804#define MASK_BLT 0x707f
805#define MATCH_BGE 0x5063
806#define MASK_BGE 0x707f
807#define MATCH_BLTU 0x6063
808#define MASK_BLTU 0x707f
809#define MATCH_BGEU 0x7063
810#define MASK_BGEU 0x707f
811#define MATCH_JALR 0x67
812#define MASK_JALR 0x707f
813#define MATCH_JAL 0x6f
814#define MASK_JAL 0x7f
815#define MATCH_LUI 0x37
816#define MASK_LUI 0x7f
817#define MATCH_AUIPC 0x17
818#define MASK_AUIPC 0x7f
819#define MATCH_ADDI 0x13
820#define MASK_ADDI 0x707f
821#define MATCH_SLLI 0x1013
822#define MASK_SLLI 0xfc00707f
823#define MATCH_SLTI 0x2013
824#define MASK_SLTI 0x707f
825#define MATCH_SLTIU 0x3013
826#define MASK_SLTIU 0x707f
827#define MATCH_XORI 0x4013
828#define MASK_XORI 0x707f
829#define MATCH_SRLI 0x5013
830#define MASK_SRLI 0xfc00707f
831#define MATCH_SRAI 0x40005013
832#define MASK_SRAI 0xfc00707f
833#define MATCH_ORI 0x6013
834#define MASK_ORI 0x707f
835#define MATCH_ANDI 0x7013
836#define MASK_ANDI 0x707f
837#define MATCH_ADD 0x33
838#define MASK_ADD 0xfe00707f
839#define MATCH_SUB 0x40000033
840#define MASK_SUB 0xfe00707f
841#define MATCH_SLL 0x1033
842#define MASK_SLL 0xfe00707f
843#define MATCH_SLT 0x2033
844#define MASK_SLT 0xfe00707f
845#define MATCH_SLTU 0x3033
846#define MASK_SLTU 0xfe00707f
847#define MATCH_XOR 0x4033
848#define MASK_XOR 0xfe00707f
849#define MATCH_SRL 0x5033
850#define MASK_SRL 0xfe00707f
851#define MATCH_SRA 0x40005033
852#define MASK_SRA 0xfe00707f
853#define MATCH_OR 0x6033
854#define MASK_OR 0xfe00707f
855#define MATCH_AND 0x7033
856#define MASK_AND 0xfe00707f
857#define MATCH_ADDIW 0x1b
858#define MASK_ADDIW 0x707f
859#define MATCH_SLLIW 0x101b
860#define MASK_SLLIW 0xfe00707f
861#define MATCH_SRLIW 0x501b
862#define MASK_SRLIW 0xfe00707f
863#define MATCH_SRAIW 0x4000501b
864#define MASK_SRAIW 0xfe00707f
865#define MATCH_ADDW 0x3b
866#define MASK_ADDW 0xfe00707f
867#define MATCH_SUBW 0x4000003b
868#define MASK_SUBW 0xfe00707f
869#define MATCH_SLLW 0x103b
870#define MASK_SLLW 0xfe00707f
871#define MATCH_SRLW 0x503b
872#define MASK_SRLW 0xfe00707f
873#define MATCH_SRAW 0x4000503b
874#define MASK_SRAW 0xfe00707f
875#define MATCH_LB 0x3
876#define MASK_LB 0x707f
877#define MATCH_LH 0x1003
878#define MASK_LH 0x707f
879#define MATCH_LW 0x2003
880#define MASK_LW 0x707f
881#define MATCH_LD 0x3003
882#define MASK_LD 0x707f
883#define MATCH_LBU 0x4003
884#define MASK_LBU 0x707f
885#define MATCH_LHU 0x5003
886#define MASK_LHU 0x707f
887#define MATCH_LWU 0x6003
888#define MASK_LWU 0x707f
889#define MATCH_SB 0x23
890#define MASK_SB 0x707f
891#define MATCH_SH 0x1023
892#define MASK_SH 0x707f
893#define MATCH_SW 0x2023
894#define MASK_SW 0x707f
895#define MATCH_SD 0x3023
896#define MASK_SD 0x707f
897#define MATCH_FENCE 0xf
898#define MASK_FENCE 0x707f
899#define MATCH_FENCE_I 0x100f
900#define MASK_FENCE_I 0x707f
901#define MATCH_MUL 0x2000033
902#define MASK_MUL 0xfe00707f
903#define MATCH_MULH 0x2001033
904#define MASK_MULH 0xfe00707f
905#define MATCH_MULHSU 0x2002033
906#define MASK_MULHSU 0xfe00707f
907#define MATCH_MULHU 0x2003033
908#define MASK_MULHU 0xfe00707f
909#define MATCH_DIV 0x2004033
910#define MASK_DIV 0xfe00707f
911#define MATCH_DIVU 0x2005033
912#define MASK_DIVU 0xfe00707f
913#define MATCH_REM 0x2006033
914#define MASK_REM 0xfe00707f
915#define MATCH_REMU 0x2007033
916#define MASK_REMU 0xfe00707f
917#define MATCH_MULW 0x200003b
918#define MASK_MULW 0xfe00707f
919#define MATCH_DIVW 0x200403b
920#define MASK_DIVW 0xfe00707f
921#define MATCH_DIVUW 0x200503b
922#define MASK_DIVUW 0xfe00707f
923#define MATCH_REMW 0x200603b
924#define MASK_REMW 0xfe00707f
925#define MATCH_REMUW 0x200703b
926#define MASK_REMUW 0xfe00707f
927#define MATCH_AMOADD_W 0x202f
928#define MASK_AMOADD_W 0xf800707f
929#define MATCH_AMOXOR_W 0x2000202f
930#define MASK_AMOXOR_W 0xf800707f
931#define MATCH_AMOOR_W 0x4000202f
932#define MASK_AMOOR_W 0xf800707f
933#define MATCH_AMOAND_W 0x6000202f
934#define MASK_AMOAND_W 0xf800707f
935#define MATCH_AMOMIN_W 0x8000202f
936#define MASK_AMOMIN_W 0xf800707f
937#define MATCH_AMOMAX_W 0xa000202f
938#define MASK_AMOMAX_W 0xf800707f
939#define MATCH_AMOMINU_W 0xc000202f
940#define MASK_AMOMINU_W 0xf800707f
941#define MATCH_AMOMAXU_W 0xe000202f
942#define MASK_AMOMAXU_W 0xf800707f
943#define MATCH_AMOSWAP_W 0x800202f
944#define MASK_AMOSWAP_W 0xf800707f
945#define MATCH_LR_W 0x1000202f
946#define MASK_LR_W 0xf9f0707f
947#define MATCH_SC_W 0x1800202f
948#define MASK_SC_W 0xf800707f
949#define MATCH_AMOADD_D 0x302f
950#define MASK_AMOADD_D 0xf800707f
951#define MATCH_AMOXOR_D 0x2000302f
952#define MASK_AMOXOR_D 0xf800707f
953#define MATCH_AMOOR_D 0x4000302f
954#define MASK_AMOOR_D 0xf800707f
955#define MATCH_AMOAND_D 0x6000302f
956#define MASK_AMOAND_D 0xf800707f
957#define MATCH_AMOMIN_D 0x8000302f
958#define MASK_AMOMIN_D 0xf800707f
959#define MATCH_AMOMAX_D 0xa000302f
960#define MASK_AMOMAX_D 0xf800707f
961#define MATCH_AMOMINU_D 0xc000302f
962#define MASK_AMOMINU_D 0xf800707f
963#define MATCH_AMOMAXU_D 0xe000302f
964#define MASK_AMOMAXU_D 0xf800707f
965#define MATCH_AMOSWAP_D 0x800302f
966#define MASK_AMOSWAP_D 0xf800707f
967#define MATCH_LR_D 0x1000302f
968#define MASK_LR_D 0xf9f0707f
969#define MATCH_SC_D 0x1800302f
970#define MASK_SC_D 0xf800707f
971#define MATCH_ECALL 0x73
972#define MASK_ECALL 0xffffffff
973#define MATCH_EBREAK 0x100073
974#define MASK_EBREAK 0xffffffff
975#define MATCH_URET 0x200073
976#define MASK_URET 0xffffffff
977#define MATCH_SRET 0x10200073
978#define MASK_SRET 0xffffffff
979#define MATCH_HRET 0x20200073
980#define MASK_HRET 0xffffffff
981#define MATCH_MRET 0x30200073
982#define MASK_MRET 0xffffffff
983#define MATCH_DRET 0x7b200073
984#define MASK_DRET 0xffffffff
985#define MATCH_SFENCE_VM 0x10400073
986#define MASK_SFENCE_VM 0xfff07fff
987#define MATCH_WFI 0x10500073
988#define MASK_WFI 0xffffffff
989#define MATCH_CSRRW 0x1073
990#define MASK_CSRRW 0x707f
991#define MATCH_CSRRS 0x2073
992#define MASK_CSRRS 0x707f
993#define MATCH_CSRRC 0x3073
994#define MASK_CSRRC 0x707f
995#define MATCH_CSRRWI 0x5073
996#define MASK_CSRRWI 0x707f
997#define MATCH_CSRRSI 0x6073
998#define MASK_CSRRSI 0x707f
999#define MATCH_CSRRCI 0x7073
1000#define MASK_CSRRCI 0x707f
1001#define MATCH_FADD_S 0x53
1002#define MASK_FADD_S 0xfe00007f
1003#define MATCH_FSUB_S 0x8000053
1004#define MASK_FSUB_S 0xfe00007f
1005#define MATCH_FMUL_S 0x10000053
1006#define MASK_FMUL_S 0xfe00007f
1007#define MATCH_FDIV_S 0x18000053
1008#define MASK_FDIV_S 0xfe00007f
1009#define MATCH_FSGNJ_S 0x20000053
1010#define MASK_FSGNJ_S 0xfe00707f
1011#define MATCH_FSGNJN_S 0x20001053
1012#define MASK_FSGNJN_S 0xfe00707f
1013#define MATCH_FSGNJX_S 0x20002053
1014#define MASK_FSGNJX_S 0xfe00707f
1015#define MATCH_FMIN_S 0x28000053
1016#define MASK_FMIN_S 0xfe00707f
1017#define MATCH_FMAX_S 0x28001053
1018#define MASK_FMAX_S 0xfe00707f
1019#define MATCH_FSQRT_S 0x58000053
1020#define MASK_FSQRT_S 0xfff0007f
1021#define MATCH_FADD_D 0x2000053
1022#define MASK_FADD_D 0xfe00007f
1023#define MATCH_FSUB_D 0xa000053
1024#define MASK_FSUB_D 0xfe00007f
1025#define MATCH_FMUL_D 0x12000053
1026#define MASK_FMUL_D 0xfe00007f
1027#define MATCH_FDIV_D 0x1a000053
1028#define MASK_FDIV_D 0xfe00007f
1029#define MATCH_FSGNJ_D 0x22000053
1030#define MASK_FSGNJ_D 0xfe00707f
1031#define MATCH_FSGNJN_D 0x22001053
1032#define MASK_FSGNJN_D 0xfe00707f
1033#define MATCH_FSGNJX_D 0x22002053
1034#define MASK_FSGNJX_D 0xfe00707f
1035#define MATCH_FMIN_D 0x2a000053
1036#define MASK_FMIN_D 0xfe00707f
1037#define MATCH_FMAX_D 0x2a001053
1038#define MASK_FMAX_D 0xfe00707f
1039#define MATCH_FCVT_S_D 0x40100053
1040#define MASK_FCVT_S_D 0xfff0007f
1041#define MATCH_FCVT_D_S 0x42000053
1042#define MASK_FCVT_D_S 0xfff0007f
1043#define MATCH_FSQRT_D 0x5a000053
1044#define MASK_FSQRT_D 0xfff0007f
1045#define MATCH_FLE_S 0xa0000053
1046#define MASK_FLE_S 0xfe00707f
1047#define MATCH_FLT_S 0xa0001053
1048#define MASK_FLT_S 0xfe00707f
1049#define MATCH_FEQ_S 0xa0002053
1050#define MASK_FEQ_S 0xfe00707f
1051#define MATCH_FLE_D 0xa2000053
1052#define MASK_FLE_D 0xfe00707f
1053#define MATCH_FLT_D 0xa2001053
1054#define MASK_FLT_D 0xfe00707f
1055#define MATCH_FEQ_D 0xa2002053
1056#define MASK_FEQ_D 0xfe00707f
1057#define MATCH_FCVT_W_S 0xc0000053
1058#define MASK_FCVT_W_S 0xfff0007f
1059#define MATCH_FCVT_WU_S 0xc0100053
1060#define MASK_FCVT_WU_S 0xfff0007f
1061#define MATCH_FCVT_L_S 0xc0200053
1062#define MASK_FCVT_L_S 0xfff0007f
1063#define MATCH_FCVT_LU_S 0xc0300053
1064#define MASK_FCVT_LU_S 0xfff0007f
1065#define MATCH_FMV_X_S 0xe0000053
1066#define MASK_FMV_X_S 0xfff0707f
1067#define MATCH_FCLASS_S 0xe0001053
1068#define MASK_FCLASS_S 0xfff0707f
1069#define MATCH_FCVT_W_D 0xc2000053
1070#define MASK_FCVT_W_D 0xfff0007f
1071#define MATCH_FCVT_WU_D 0xc2100053
1072#define MASK_FCVT_WU_D 0xfff0007f
1073#define MATCH_FCVT_L_D 0xc2200053
1074#define MASK_FCVT_L_D 0xfff0007f
1075#define MATCH_FCVT_LU_D 0xc2300053
1076#define MASK_FCVT_LU_D 0xfff0007f
1077#define MATCH_FMV_X_D 0xe2000053
1078#define MASK_FMV_X_D 0xfff0707f
1079#define MATCH_FCLASS_D 0xe2001053
1080#define MASK_FCLASS_D 0xfff0707f
1081#define MATCH_FCVT_S_W 0xd0000053
1082#define MASK_FCVT_S_W 0xfff0007f
1083#define MATCH_FCVT_S_WU 0xd0100053
1084#define MASK_FCVT_S_WU 0xfff0007f
1085#define MATCH_FCVT_S_L 0xd0200053
1086#define MASK_FCVT_S_L 0xfff0007f
1087#define MATCH_FCVT_S_LU 0xd0300053
1088#define MASK_FCVT_S_LU 0xfff0007f
1089#define MATCH_FMV_S_X 0xf0000053
1090#define MASK_FMV_S_X 0xfff0707f
1091#define MATCH_FCVT_D_W 0xd2000053
1092#define MASK_FCVT_D_W 0xfff0007f
1093#define MATCH_FCVT_D_WU 0xd2100053
1094#define MASK_FCVT_D_WU 0xfff0007f
1095#define MATCH_FCVT_D_L 0xd2200053
1096#define MASK_FCVT_D_L 0xfff0007f
1097#define MATCH_FCVT_D_LU 0xd2300053
1098#define MASK_FCVT_D_LU 0xfff0007f
1099#define MATCH_FMV_D_X 0xf2000053
1100#define MASK_FMV_D_X 0xfff0707f
1101#define MATCH_FLW 0x2007
1102#define MASK_FLW 0x707f
1103#define MATCH_FLD 0x3007
1104#define MASK_FLD 0x707f
1105#define MATCH_FSW 0x2027
1106#define MASK_FSW 0x707f
1107#define MATCH_FSD 0x3027
1108#define MASK_FSD 0x707f
1109#define MATCH_FMADD_S 0x43
1110#define MASK_FMADD_S 0x600007f
1111#define MATCH_FMSUB_S 0x47
1112#define MASK_FMSUB_S 0x600007f
1113#define MATCH_FNMSUB_S 0x4b
1114#define MASK_FNMSUB_S 0x600007f
1115#define MATCH_FNMADD_S 0x4f
1116#define MASK_FNMADD_S 0x600007f
1117#define MATCH_FMADD_D 0x2000043
1118#define MASK_FMADD_D 0x600007f
1119#define MATCH_FMSUB_D 0x2000047
1120#define MASK_FMSUB_D 0x600007f
1121#define MATCH_FNMSUB_D 0x200004b
1122#define MASK_FNMSUB_D 0x600007f
1123#define MATCH_FNMADD_D 0x200004f
1124#define MASK_FNMADD_D 0x600007f
1125#define MATCH_C_NOP 0x1
1126#define MASK_C_NOP 0xffff
1127#define MATCH_C_ADDI16SP 0x6101
1128#define MASK_C_ADDI16SP 0xef83
1129#define MATCH_C_JR 0x8002
1130#define MASK_C_JR 0xf07f
1131#define MATCH_C_JALR 0x9002
1132#define MASK_C_JALR 0xf07f
1133#define MATCH_C_EBREAK 0x9002
1134#define MASK_C_EBREAK 0xffff
1135#define MATCH_C_LD 0x6000
1136#define MASK_C_LD 0xe003
1137#define MATCH_C_SD 0xe000
1138#define MASK_C_SD 0xe003
1139#define MATCH_C_ADDIW 0x2001
1140#define MASK_C_ADDIW 0xe003
1141#define MATCH_C_LDSP 0x6002
1142#define MASK_C_LDSP 0xe003
1143#define MATCH_C_SDSP 0xe002
1144#define MASK_C_SDSP 0xe003
1145#define MATCH_C_ADDI4SPN 0x0
1146#define MASK_C_ADDI4SPN 0xe003
1147#define MATCH_C_FLD 0x2000
1148#define MASK_C_FLD 0xe003
1149#define MATCH_C_LW 0x4000
1150#define MASK_C_LW 0xe003
1151#define MATCH_C_FLW 0x6000
1152#define MASK_C_FLW 0xe003
1153#define MATCH_C_FSD 0xa000
1154#define MASK_C_FSD 0xe003
1155#define MATCH_C_SW 0xc000
1156#define MASK_C_SW 0xe003
1157#define MATCH_C_FSW 0xe000
1158#define MASK_C_FSW 0xe003
1159#define MATCH_C_ADDI 0x1
1160#define MASK_C_ADDI 0xe003
1161#define MATCH_C_JAL 0x2001
1162#define MASK_C_JAL 0xe003
1163#define MATCH_C_LI 0x4001
1164#define MASK_C_LI 0xe003
1165#define MATCH_C_LUI 0x6001
1166#define MASK_C_LUI 0xe003
1167#define MATCH_C_SRLI 0x8001
1168#define MASK_C_SRLI 0xec03
1169#define MATCH_C_SRAI 0x8401
1170#define MASK_C_SRAI 0xec03
1171#define MATCH_C_ANDI 0x8801
1172#define MASK_C_ANDI 0xec03
1173#define MATCH_C_SUB 0x8c01
1174#define MASK_C_SUB 0xfc63
1175#define MATCH_C_XOR 0x8c21
1176#define MASK_C_XOR 0xfc63
1177#define MATCH_C_OR 0x8c41
1178#define MASK_C_OR 0xfc63
1179#define MATCH_C_AND 0x8c61
1180#define MASK_C_AND 0xfc63
1181#define MATCH_C_SUBW 0x9c01
1182#define MASK_C_SUBW 0xfc63
1183#define MATCH_C_ADDW 0x9c21
1184#define MASK_C_ADDW 0xfc63
1185#define MATCH_C_J 0xa001
1186#define MASK_C_J 0xe003
1187#define MATCH_C_BEQZ 0xc001
1188#define MASK_C_BEQZ 0xe003
1189#define MATCH_C_BNEZ 0xe001
1190#define MASK_C_BNEZ 0xe003
1191#define MATCH_C_SLLI 0x2
1192#define MASK_C_SLLI 0xe003
1193#define MATCH_C_FLDSP 0x2002
1194#define MASK_C_FLDSP 0xe003
1195#define MATCH_C_LWSP 0x4002
1196#define MASK_C_LWSP 0xe003
1197#define MATCH_C_FLWSP 0x6002
1198#define MASK_C_FLWSP 0xe003
1199#define MATCH_C_MV 0x8002
1200#define MASK_C_MV 0xf003
1201#define MATCH_C_ADD 0x9002
1202#define MASK_C_ADD 0xf003
1203#define MATCH_C_FSDSP 0xa002
1204#define MASK_C_FSDSP 0xe003
1205#define MATCH_C_SWSP 0xc002
1206#define MASK_C_SWSP 0xe003
1207#define MATCH_C_FSWSP 0xe002
1208#define MASK_C_FSWSP 0xe003
1209#define MATCH_CUSTOM0 0xb
1210#define MASK_CUSTOM0 0x707f
1211#define MATCH_CUSTOM0_RS1 0x200b
1212#define MASK_CUSTOM0_RS1 0x707f
1213#define MATCH_CUSTOM0_RS1_RS2 0x300b
1214#define MASK_CUSTOM0_RS1_RS2 0x707f
1215#define MATCH_CUSTOM0_RD 0x400b
1216#define MASK_CUSTOM0_RD 0x707f
1217#define MATCH_CUSTOM0_RD_RS1 0x600b
1218#define MASK_CUSTOM0_RD_RS1 0x707f
1219#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
1220#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
1221#define MATCH_CUSTOM1 0x2b
1222#define MASK_CUSTOM1 0x707f
1223#define MATCH_CUSTOM1_RS1 0x202b
1224#define MASK_CUSTOM1_RS1 0x707f
1225#define MATCH_CUSTOM1_RS1_RS2 0x302b
1226#define MASK_CUSTOM1_RS1_RS2 0x707f
1227#define MATCH_CUSTOM1_RD 0x402b
1228#define MASK_CUSTOM1_RD 0x707f
1229#define MATCH_CUSTOM1_RD_RS1 0x602b
1230#define MASK_CUSTOM1_RD_RS1 0x707f
1231#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
1232#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
1233#define MATCH_CUSTOM2 0x5b
1234#define MASK_CUSTOM2 0x707f
1235#define MATCH_CUSTOM2_RS1 0x205b
1236#define MASK_CUSTOM2_RS1 0x707f
1237#define MATCH_CUSTOM2_RS1_RS2 0x305b
1238#define MASK_CUSTOM2_RS1_RS2 0x707f
1239#define MATCH_CUSTOM2_RD 0x405b
1240#define MASK_CUSTOM2_RD 0x707f
1241#define MATCH_CUSTOM2_RD_RS1 0x605b
1242#define MASK_CUSTOM2_RD_RS1 0x707f
1243#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
1244#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
1245#define MATCH_CUSTOM3 0x7b
1246#define MASK_CUSTOM3 0x707f
1247#define MATCH_CUSTOM3_RS1 0x207b
1248#define MASK_CUSTOM3_RS1 0x707f
1249#define MATCH_CUSTOM3_RS1_RS2 0x307b
1250#define MASK_CUSTOM3_RS1_RS2 0x707f
1251#define MATCH_CUSTOM3_RD 0x407b
1252#define MASK_CUSTOM3_RD 0x707f
1253#define MATCH_CUSTOM3_RD_RS1 0x607b
1254#define MASK_CUSTOM3_RD_RS1 0x707f
1255#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
1256#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
1257#define CSR_FFLAGS 0x1
1258#define CSR_FRM 0x2
1259#define CSR_FCSR 0x3
1260#define CSR_CYCLE 0xc00
1261#define CSR_TIME 0xc01
1262#define CSR_INSTRET 0xc02
1263#define CSR_HPMCOUNTER3 0xc03
1264#define CSR_HPMCOUNTER4 0xc04
1265#define CSR_HPMCOUNTER5 0xc05
1266#define CSR_HPMCOUNTER6 0xc06
1267#define CSR_HPMCOUNTER7 0xc07
1268#define CSR_HPMCOUNTER8 0xc08
1269#define CSR_HPMCOUNTER9 0xc09
1270#define CSR_HPMCOUNTER10 0xc0a
1271#define CSR_HPMCOUNTER11 0xc0b
1272#define CSR_HPMCOUNTER12 0xc0c
1273#define CSR_HPMCOUNTER13 0xc0d
1274#define CSR_HPMCOUNTER14 0xc0e
1275#define CSR_HPMCOUNTER15 0xc0f
1276#define CSR_HPMCOUNTER16 0xc10
1277#define CSR_HPMCOUNTER17 0xc11
1278#define CSR_HPMCOUNTER18 0xc12
1279#define CSR_HPMCOUNTER19 0xc13
1280#define CSR_HPMCOUNTER20 0xc14
1281#define CSR_HPMCOUNTER21 0xc15
1282#define CSR_HPMCOUNTER22 0xc16
1283#define CSR_HPMCOUNTER23 0xc17
1284#define CSR_HPMCOUNTER24 0xc18
1285#define CSR_HPMCOUNTER25 0xc19
1286#define CSR_HPMCOUNTER26 0xc1a
1287#define CSR_HPMCOUNTER27 0xc1b
1288#define CSR_HPMCOUNTER28 0xc1c
1289#define CSR_HPMCOUNTER29 0xc1d
1290#define CSR_HPMCOUNTER30 0xc1e
1291#define CSR_HPMCOUNTER31 0xc1f
1292#define CSR_SSTATUS 0x100
1293#define CSR_SIE 0x104
1294#define CSR_STVEC 0x105
1295#define CSR_SSCRATCH 0x140
1296#define CSR_SEPC 0x141
1297#define CSR_SCAUSE 0x142
1298#define CSR_SBADADDR 0x143
1299#define CSR_SIP 0x144
1300#define CSR_SPTBR 0x180
1301#define CSR_MSTATUS 0x300
1302#define CSR_MISA 0x301
1303#define CSR_MEDELEG 0x302
1304#define CSR_MIDELEG 0x303
1305#define CSR_MIE 0x304
1306#define CSR_MTVEC 0x305
1307#define CSR_MSCRATCH 0x340
1308#define CSR_MEPC 0x341
1309#define CSR_MCAUSE 0x342
1310#define CSR_MTVAL 0x343
1311#define CSR_MIP 0x344
1312#define CSR_TSELECT 0x7a0
1313#define CSR_TDATA1 0x7a1
1314#define CSR_TDATA2 0x7a2
1315#define CSR_TDATA3 0x7a3
1316#define CSR_DCSR 0x7b0
1317#define CSR_DPC 0x7b1
1318#define CSR_DSCRATCH 0x7b2
1319#define CSR_MCYCLE 0xb00
1320#define CSR_MINSTRET 0xb02
1321#define CSR_MHPMCOUNTER3 0xb03
1322#define CSR_MHPMCOUNTER4 0xb04
1323#define CSR_MHPMCOUNTER5 0xb05
1324#define CSR_MHPMCOUNTER6 0xb06
1325#define CSR_MHPMCOUNTER7 0xb07
1326#define CSR_MHPMCOUNTER8 0xb08
1327#define CSR_MHPMCOUNTER9 0xb09
1328#define CSR_MHPMCOUNTER10 0xb0a
1329#define CSR_MHPMCOUNTER11 0xb0b
1330#define CSR_MHPMCOUNTER12 0xb0c
1331#define CSR_MHPMCOUNTER13 0xb0d
1332#define CSR_MHPMCOUNTER14 0xb0e
1333#define CSR_MHPMCOUNTER15 0xb0f
1334#define CSR_MHPMCOUNTER16 0xb10
1335#define CSR_MHPMCOUNTER17 0xb11
1336#define CSR_MHPMCOUNTER18 0xb12
1337#define CSR_MHPMCOUNTER19 0xb13
1338#define CSR_MHPMCOUNTER20 0xb14
1339#define CSR_MHPMCOUNTER21 0xb15
1340#define CSR_MHPMCOUNTER22 0xb16
1341#define CSR_MHPMCOUNTER23 0xb17
1342#define CSR_MHPMCOUNTER24 0xb18
1343#define CSR_MHPMCOUNTER25 0xb19
1344#define CSR_MHPMCOUNTER26 0xb1a
1345#define CSR_MHPMCOUNTER27 0xb1b
1346#define CSR_MHPMCOUNTER28 0xb1c
1347#define CSR_MHPMCOUNTER29 0xb1d
1348#define CSR_MHPMCOUNTER30 0xb1e
1349#define CSR_MHPMCOUNTER31 0xb1f
1350#define CSR_MUCOUNTEREN 0x320
1351#define CSR_MSCOUNTEREN 0x321
1352#define CSR_MHPMEVENT3 0x323
1353#define CSR_MHPMEVENT4 0x324
1354#define CSR_MHPMEVENT5 0x325
1355#define CSR_MHPMEVENT6 0x326
1356#define CSR_MHPMEVENT7 0x327
1357#define CSR_MHPMEVENT8 0x328
1358#define CSR_MHPMEVENT9 0x329
1359#define CSR_MHPMEVENT10 0x32a
1360#define CSR_MHPMEVENT11 0x32b
1361#define CSR_MHPMEVENT12 0x32c
1362#define CSR_MHPMEVENT13 0x32d
1363#define CSR_MHPMEVENT14 0x32e
1364#define CSR_MHPMEVENT15 0x32f
1365#define CSR_MHPMEVENT16 0x330
1366#define CSR_MHPMEVENT17 0x331
1367#define CSR_MHPMEVENT18 0x332
1368#define CSR_MHPMEVENT19 0x333
1369#define CSR_MHPMEVENT20 0x334
1370#define CSR_MHPMEVENT21 0x335
1371#define CSR_MHPMEVENT22 0x336
1372#define CSR_MHPMEVENT23 0x337
1373#define CSR_MHPMEVENT24 0x338
1374#define CSR_MHPMEVENT25 0x339
1375#define CSR_MHPMEVENT26 0x33a
1376#define CSR_MHPMEVENT27 0x33b
1377#define CSR_MHPMEVENT28 0x33c
1378#define CSR_MHPMEVENT29 0x33d
1379#define CSR_MHPMEVENT30 0x33e
1380#define CSR_MHPMEVENT31 0x33f
1381#define CSR_MVENDORID 0xf11
1382#define CSR_MARCHID 0xf12
1383#define CSR_MIMPID 0xf13
1384#define CSR_MHARTID 0xf14
1385#define CSR_CYCLEH 0xc80
1386#define CSR_TIMEH 0xc81
1387#define CSR_INSTRETH 0xc82
1388#define CSR_HPMCOUNTER3H 0xc83
1389#define CSR_HPMCOUNTER4H 0xc84
1390#define CSR_HPMCOUNTER5H 0xc85
1391#define CSR_HPMCOUNTER6H 0xc86
1392#define CSR_HPMCOUNTER7H 0xc87
1393#define CSR_HPMCOUNTER8H 0xc88
1394#define CSR_HPMCOUNTER9H 0xc89
1395#define CSR_HPMCOUNTER10H 0xc8a
1396#define CSR_HPMCOUNTER11H 0xc8b
1397#define CSR_HPMCOUNTER12H 0xc8c
1398#define CSR_HPMCOUNTER13H 0xc8d
1399#define CSR_HPMCOUNTER14H 0xc8e
1400#define CSR_HPMCOUNTER15H 0xc8f
1401#define CSR_HPMCOUNTER16H 0xc90
1402#define CSR_HPMCOUNTER17H 0xc91
1403#define CSR_HPMCOUNTER18H 0xc92
1404#define CSR_HPMCOUNTER19H 0xc93
1405#define CSR_HPMCOUNTER20H 0xc94
1406#define CSR_HPMCOUNTER21H 0xc95
1407#define CSR_HPMCOUNTER22H 0xc96
1408#define CSR_HPMCOUNTER23H 0xc97
1409#define CSR_HPMCOUNTER24H 0xc98
1410#define CSR_HPMCOUNTER25H 0xc99
1411#define CSR_HPMCOUNTER26H 0xc9a
1412#define CSR_HPMCOUNTER27H 0xc9b
1413#define CSR_HPMCOUNTER28H 0xc9c
1414#define CSR_HPMCOUNTER29H 0xc9d
1415#define CSR_HPMCOUNTER30H 0xc9e
1416#define CSR_HPMCOUNTER31H 0xc9f
1417#define CSR_MCYCLEH 0xb80
1418#define CSR_MINSTRETH 0xb82
1419#define CSR_MHPMCOUNTER3H 0xb83
1420#define CSR_MHPMCOUNTER4H 0xb84
1421#define CSR_MHPMCOUNTER5H 0xb85
1422#define CSR_MHPMCOUNTER6H 0xb86
1423#define CSR_MHPMCOUNTER7H 0xb87
1424#define CSR_MHPMCOUNTER8H 0xb88
1425#define CSR_MHPMCOUNTER9H 0xb89
1426#define CSR_MHPMCOUNTER10H 0xb8a
1427#define CSR_MHPMCOUNTER11H 0xb8b
1428#define CSR_MHPMCOUNTER12H 0xb8c
1429#define CSR_MHPMCOUNTER13H 0xb8d
1430#define CSR_MHPMCOUNTER14H 0xb8e
1431#define CSR_MHPMCOUNTER15H 0xb8f
1432#define CSR_MHPMCOUNTER16H 0xb90
1433#define CSR_MHPMCOUNTER17H 0xb91
1434#define CSR_MHPMCOUNTER18H 0xb92
1435#define CSR_MHPMCOUNTER19H 0xb93
1436#define CSR_MHPMCOUNTER20H 0xb94
1437#define CSR_MHPMCOUNTER21H 0xb95
1438#define CSR_MHPMCOUNTER22H 0xb96
1439#define CSR_MHPMCOUNTER23H 0xb97
1440#define CSR_MHPMCOUNTER24H 0xb98
1441#define CSR_MHPMCOUNTER25H 0xb99
1442#define CSR_MHPMCOUNTER26H 0xb9a
1443#define CSR_MHPMCOUNTER27H 0xb9b
1444#define CSR_MHPMCOUNTER28H 0xb9c
1445#define CSR_MHPMCOUNTER29H 0xb9d
1446#define CSR_MHPMCOUNTER30H 0xb9e
1447#define CSR_MHPMCOUNTER31H 0xb9f
1448#define CAUSE_MISALIGNED_FETCH 0x0
1449#define CAUSE_FAULT_FETCH 0x1
1450#define CAUSE_ILLEGAL_INSTRUCTION 0x2
1451#define CAUSE_BREAKPOINT 0x3
1452#define CAUSE_MISALIGNED_LOAD 0x4
1453#define CAUSE_FAULT_LOAD 0x5
1454#define CAUSE_MISALIGNED_STORE 0x6
1455#define CAUSE_FAULT_STORE 0x7
1456#define CAUSE_USER_ECALL 0x8
1457#define CAUSE_SUPERVISOR_ECALL 0x9
1458#define CAUSE_HYPERVISOR_ECALL 0xa
1459#define CAUSE_MACHINE_ECALL 0xb
1460#define CAUSE_FETCH_PAGE_FAULT 0xc
1461#define CAUSE_LOAD_PAGE_FAULT 0xd
1462#define CAUSE_RESERVED 0xe
1463#define CAUSE_STORE_PAGE_FAULT 0xf
1464#endif
1465#ifdef DECLARE_INSN
1466DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
1467 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
1468 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
1469 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
1470 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
1471 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
1472 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
1473 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
1474 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
1475 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
1476 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
1477 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
1478 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
1479 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
1480 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
1481 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
1482 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
1483 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
1484 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
1485 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
1486 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
1487 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
1488 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
1489 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
1490 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
1491 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
1492 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
1493 DECLARE_INSN(or, MATCH_OR, MASK_OR)
1494 DECLARE_INSN(and, MATCH_AND, MASK_AND)
1495 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
1496 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
1497 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
1498 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
1499 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
1500 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
1501 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
1502 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
1503 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
1504 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
1505 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
1506 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
1507 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
1508 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
1509 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
1510 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
1511 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
1512 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
1513 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
1514 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
1515 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
1516 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
1517 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
1518 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
1519 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
1520 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
1521 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
1522 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
1523 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
1524 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
1525 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
1526 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
1527 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
1528 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
1529 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
1530 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
1531 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
1532 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
1533 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
1534 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
1535 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
1536 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
1537 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
1538 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
1539 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
1540 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
1541 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
1542 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
1543 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
1544 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
1545 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
1546 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
1547 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
1548 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
1549 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
1550 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
1551 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
1552 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
1553 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
1554 DECLARE_INSN(uret, MATCH_URET, MASK_URET)
1555 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
1556 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
1557 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
1558 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
1559 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
1560 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
1561 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
1562 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
1563 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
1564 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
1565 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
1566 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
1567 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
1568 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
1569 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
1570 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
1571 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
1572 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
1573 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
1574 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
1575 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
1576 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
1577 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
1578 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
1579 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
1580 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
1581 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
1582 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
1583 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
1584 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
1585 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
1586 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
1587 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
1588 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
1589 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
1590 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
1591 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
1592 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
1593 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
1594 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
1595 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
1596 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
1597 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
1598 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
1599 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
1600 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
1601 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
1602 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
1603 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
1604 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
1605 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
1606 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
1607 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
1608 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
1609 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
1610 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
1611 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
1612 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
1613 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
1614 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
1615 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
1616 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
1617 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
1618 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
1619 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
1620 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
1621 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
1622 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
1623 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
1624 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
1625 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
1626 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
1627 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
1628 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
1629 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
1630 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
1631 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
1632 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
1633 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
1634 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
1635 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
1636 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
1637 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
1638 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
1639 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
1640 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
1641 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
1642 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
1643 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
1644 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
1645 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
1646 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
1647 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
1648 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
1649 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
1650 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
1651 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
1652 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
1653 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
1654 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
1655 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
1656 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
1657 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
1658 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
1659 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
1660 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
1661 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
1662 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
1663 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
1664 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
1665 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
1666 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
1667 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
1668 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
1669 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
1670 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
1671 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
1672 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
1673 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
1674 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
1675 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
1676 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2,
1677 MASK_CUSTOM0_RD_RS1_RS2)
1678 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
1679 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
1680 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
1681 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
1682 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
1683 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2,
1684 MASK_CUSTOM1_RD_RS1_RS2)
1685 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
1686 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
1687 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
1688 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
1689 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
1690 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2,
1691 MASK_CUSTOM2_RD_RS1_RS2)
1692 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
1693 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
1694 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
1695 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
1696 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
1697 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2,
1698 MASK_CUSTOM3_RD_RS1_RS2)
1699#endif
1700#ifdef DECLARE_CSR
1701 DECLARE_CSR(fflags, CSR_FFLAGS)
1702 DECLARE_CSR(frm, CSR_FRM)
1703 DECLARE_CSR(fcsr, CSR_FCSR)
1704 DECLARE_CSR(cycle, CSR_CYCLE)
1705 DECLARE_CSR(time, CSR_TIME)
1706 DECLARE_CSR(instret, CSR_INSTRET)
1707 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
1708 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
1709 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
1710 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
1711 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
1712 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
1713 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
1714 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
1715 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
1716 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
1717 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
1718 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
1719 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
1720 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
1721 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
1722 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
1723 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
1724 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
1725 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
1726 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
1727 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
1728 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
1729 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
1730 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
1731 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
1732 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
1733 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
1734 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
1735 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
1736 DECLARE_CSR(sstatus, CSR_SSTATUS)
1737 DECLARE_CSR(sie, CSR_SIE)
1738 DECLARE_CSR(stvec, CSR_STVEC)
1739 DECLARE_CSR(sscratch, CSR_SSCRATCH)
1740 DECLARE_CSR(sepc, CSR_SEPC)
1741 DECLARE_CSR(scause, CSR_SCAUSE)
1742 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
1743 DECLARE_CSR(sip, CSR_SIP)
1744 DECLARE_CSR(sptbr, CSR_SPTBR)
1745 DECLARE_CSR(mstatus, CSR_MSTATUS)
1746 DECLARE_CSR(misa, CSR_MISA)
1747 DECLARE_CSR(medeleg, CSR_MEDELEG)
1748 DECLARE_CSR(mideleg, CSR_MIDELEG)
1749 DECLARE_CSR(mie, CSR_MIE)
1750 DECLARE_CSR(mtvec, CSR_MTVEC)
1751 DECLARE_CSR(mscratch, CSR_MSCRATCH)
1752 DECLARE_CSR(mepc, CSR_MEPC)
1753 DECLARE_CSR(mcause, CSR_MCAUSE)
1754 DECLARE_CSR(mbadaddr, CSR_MTVAL)
1755 DECLARE_CSR(mip, CSR_MIP)
1756 DECLARE_CSR(tselect, CSR_TSELECT)
1757 DECLARE_CSR(tdata1, CSR_TDATA1)
1758 DECLARE_CSR(tdata2, CSR_TDATA2)
1759 DECLARE_CSR(tdata3, CSR_TDATA3)
1760 DECLARE_CSR(dcsr, CSR_DCSR)
1761 DECLARE_CSR(dpc, CSR_DPC)
1762 DECLARE_CSR(dscratch, CSR_DSCRATCH)
1763 DECLARE_CSR(mcycle, CSR_MCYCLE)
1764 DECLARE_CSR(minstret, CSR_MINSTRET)
1765 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
1766 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
1767 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
1768 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
1769 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
1770 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
1771 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
1772 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
1773 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
1774 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
1775 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
1776 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
1777 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
1778 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
1779 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
1780 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
1781 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
1782 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
1783 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
1784 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
1785 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
1786 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
1787 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
1788 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
1789 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
1790 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
1791 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
1792 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
1793 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
1794 DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
1795 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
1796 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
1797 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
1798 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
1799 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
1800 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
1801 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
1802 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
1803 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
1804 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
1805 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
1806 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
1807 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
1808 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
1809 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
1810 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
1811 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
1812 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
1813 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
1814 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
1815 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
1816 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
1817 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
1818 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
1819 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
1820 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
1821 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
1822 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
1823 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
1824 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
1825 DECLARE_CSR(mvendorid, CSR_MVENDORID)
1826 DECLARE_CSR(marchid, CSR_MARCHID)
1827 DECLARE_CSR(mimpid, CSR_MIMPID)
1828 DECLARE_CSR(mhartid, CSR_MHARTID)
1829 DECLARE_CSR(cycleh, CSR_CYCLEH)
1830 DECLARE_CSR(timeh, CSR_TIMEH)
1831 DECLARE_CSR(instreth, CSR_INSTRETH)
1832 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
1833 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
1834 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
1835 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
1836 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
1837 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
1838 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
1839 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
1840 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
1841 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
1842 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
1843 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
1844 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
1845 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
1846 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
1847 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
1848 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
1849 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
1850 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
1851 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
1852 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
1853 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
1854 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
1855 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
1856 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
1857 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
1858 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
1859 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
1860 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
1861 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
1862 DECLARE_CSR(minstreth, CSR_MINSTRETH)
1863 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
1864 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
1865 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
1866 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
1867 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
1868 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
1869 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
1870 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
1871 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
1872 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
1873 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
1874 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
1875 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
1876 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
1877 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
1878 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
1879 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
1880 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
1881 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
1882 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
1883 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
1884 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
1885 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
1886 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
1887 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
1888 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
1889 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
1890 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
1891 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
1892#endif
1893#ifdef DECLARE_CAUSE
1894 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
1895 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
1896 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
1897 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
1898 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
1899 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
1900 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
1901 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
1902 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
1903 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
1904 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
1905 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
1906#endif