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192.168.1.100 / T800 / d09b27eb97824c3bca5df93e9062ac4c840acccb / . / src / kernel / linux / v4.19 / drivers / ata / ahci.c
blob: fa1c5a4429579c6a8396ed075852c2e33c8135ec [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/driver-api/libata.rst
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <linux/dmi.h>
44#include <linux/gfp.h>
45#include <linux/msi.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
51#include "ahci.h"
52
53#define DRV_NAME "ahci"
54#define DRV_VERSION "3.0"
55
56enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62};
63
64enum board_ids {
65 /* board IDs by feature in alphabetical order */
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_mobile,
69 board_ahci_nomsi,
70 board_ahci_noncq,
71 board_ahci_nosntf,
72 board_ahci_yes_fbs,
73
74 /* board IDs for specific chipsets in alphabetical order */
75 board_ahci_avn,
76 board_ahci_mcp65,
77 board_ahci_mcp77,
78 board_ahci_mcp89,
79 board_ahci_mv,
80 board_ahci_sb600,
81 board_ahci_sb700, /* for SB700 and SB800 */
82 board_ahci_vt8251,
83
84 /*
85 * board IDs for Intel chipsets that support more than 6 ports
86 * *and* end up needing the PCS quirk.
87 */
88 board_ahci_pcs7,
89
90 /* aliases */
91 board_ahci_mcp_linux = board_ahci_mcp65,
92 board_ahci_mcp67 = board_ahci_mcp65,
93 board_ahci_mcp73 = board_ahci_mcp65,
94 board_ahci_mcp79 = board_ahci_mcp77,
95};
96
97static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
98static void ahci_remove_one(struct pci_dev *dev);
99static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
100 unsigned long deadline);
101static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
102 unsigned long deadline);
103static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
104static bool is_mcp89_apple(struct pci_dev *pdev);
105static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
106 unsigned long deadline);
107#ifdef CONFIG_PM
108static int ahci_pci_device_runtime_suspend(struct device *dev);
109static int ahci_pci_device_runtime_resume(struct device *dev);
110#ifdef CONFIG_PM_SLEEP
111static int ahci_pci_device_suspend(struct device *dev);
112static int ahci_pci_device_resume(struct device *dev);
113#endif
114#endif /* CONFIG_PM */
115
116static struct scsi_host_template ahci_sht = {
117 AHCI_SHT("ahci"),
118};
119
120static struct ata_port_operations ahci_vt8251_ops = {
121 .inherits = &ahci_ops,
122 .hardreset = ahci_vt8251_hardreset,
123};
124
125static struct ata_port_operations ahci_p5wdh_ops = {
126 .inherits = &ahci_ops,
127 .hardreset = ahci_p5wdh_hardreset,
128};
129
130static struct ata_port_operations ahci_avn_ops = {
131 .inherits = &ahci_ops,
132 .hardreset = ahci_avn_hardreset,
133};
134
135static const struct ata_port_info ahci_port_info[] = {
136 /* by features */
137 [board_ahci] = {
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
142 },
143 [board_ahci_ign_iferr] = {
144 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
149 },
150 [board_ahci_mobile] = {
151 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_nomsi] = {
158 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
159 .flags = AHCI_FLAG_COMMON,
160 .pio_mask = ATA_PIO4,
161 .udma_mask = ATA_UDMA6,
162 .port_ops = &ahci_ops,
163 },
164 [board_ahci_noncq] = {
165 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
166 .flags = AHCI_FLAG_COMMON,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
170 },
171 [board_ahci_nosntf] = {
172 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
173 .flags = AHCI_FLAG_COMMON,
174 .pio_mask = ATA_PIO4,
175 .udma_mask = ATA_UDMA6,
176 .port_ops = &ahci_ops,
177 },
178 [board_ahci_yes_fbs] = {
179 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
184 },
185 /* by chipsets */
186 [board_ahci_avn] = {
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_avn_ops,
191 },
192 [board_ahci_mcp65] = {
193 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
194 AHCI_HFLAG_YES_NCQ),
195 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
198 .port_ops = &ahci_ops,
199 },
200 [board_ahci_mcp77] = {
201 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
206 },
207 [board_ahci_mcp89] = {
208 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
209 .flags = AHCI_FLAG_COMMON,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &ahci_ops,
213 },
214 [board_ahci_mv] = {
215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
216 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
217 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
218 .pio_mask = ATA_PIO4,
219 .udma_mask = ATA_UDMA6,
220 .port_ops = &ahci_ops,
221 },
222 [board_ahci_sb600] = {
223 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
224 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
225 AHCI_HFLAG_32BIT_ONLY),
226 .flags = AHCI_FLAG_COMMON,
227 .pio_mask = ATA_PIO4,
228 .udma_mask = ATA_UDMA6,
229 .port_ops = &ahci_pmp_retry_srst_ops,
230 },
231 [board_ahci_sb700] = { /* for SB700 and SB800 */
232 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
233 .flags = AHCI_FLAG_COMMON,
234 .pio_mask = ATA_PIO4,
235 .udma_mask = ATA_UDMA6,
236 .port_ops = &ahci_pmp_retry_srst_ops,
237 },
238 [board_ahci_vt8251] = {
239 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
240 .flags = AHCI_FLAG_COMMON,
241 .pio_mask = ATA_PIO4,
242 .udma_mask = ATA_UDMA6,
243 .port_ops = &ahci_vt8251_ops,
244 },
245 [board_ahci_pcs7] = {
246 .flags = AHCI_FLAG_COMMON,
247 .pio_mask = ATA_PIO4,
248 .udma_mask = ATA_UDMA6,
249 .port_ops = &ahci_ops,
250 },
251};
252
253static const struct pci_device_id ahci_pci_tbl[] = {
254 /* Intel */
255 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
256 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
257 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
258 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
259 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
260 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
261 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
262 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
263 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
264 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
265 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
266 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
267 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
268 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
269 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
270 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
271 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
272 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
273 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
276 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
277 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
278 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
281 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
282 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
283 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
284 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
285 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
286 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
287 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
288 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
289 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
290 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
291 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
292 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
293 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
294 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
295 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
316 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
317 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
318 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
319 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
320 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
321 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
322 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
323 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
324 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
325 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
326 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
327 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
329 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
330 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
331 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
332 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
333 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
334 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
335 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
336 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
337 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
338 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
339 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
340 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
341 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
342 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
343 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
344 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
346 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
350 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
351 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
353 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
354 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
359 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
361 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
362 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
367 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
368 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
369 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
370 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
371 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
372 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
373 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
374 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
375 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
376 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
377 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
378 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
379 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
380 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
381 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
382 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
383 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
384 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
385 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
386 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
387 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
388 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
389 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
390 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
391 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
392 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
393 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
394 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
395 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
396 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
397 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
398 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
399 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
400 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
401 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
402 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
403 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
404 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
405 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
406 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
407 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
411 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
412 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
413 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
414 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
415 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
416
417 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
418 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
419 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
420 /* JMicron 362B and 362C have an AHCI function with IDE class code */
421 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
422 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
423 /* May need to update quirk_jmicron_async_suspend() for additions */
424
425 /* ATI */
426 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
427 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
428 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
429 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
430 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
433
434 /* AMD */
435 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
436 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
437 /* AMD is using RAID class only for ahci controllers */
438 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
439 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
440
441 /* VIA */
442 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
443 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
444
445 /* NVIDIA */
446 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
467 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
468 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
469 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
470 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
471 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
472 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
473 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
474 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
475 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
476 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
477 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
478 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
479 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
480 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
481 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
482 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
483 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
484 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
485 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
486 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
487 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
488 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
489 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
490 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
491 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
492 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
493 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
494 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
495 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
496 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
497 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
498 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
499 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
500 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
501 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
502 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
503 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
504 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
505 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
506 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
507 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
508 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
509 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
510 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
511 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
512 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
513 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
514 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
515 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
516 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
517 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
518 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
519 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
520 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
521 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
522 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
523 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
524 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
525 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
526 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
527 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
528 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
529 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
530
531 /* SiS */
532 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
533 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
534 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
535
536 /* ST Microelectronics */
537 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
538
539 /* Marvell */
540 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
541 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
543 .class = PCI_CLASS_STORAGE_SATA_AHCI,
544 .class_mask = 0xffffff,
545 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
547 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
548 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
549 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
550 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
551 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
552 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
553 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
554 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
555 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
556 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
557 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
558 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
559 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
560 .driver_data = board_ahci_yes_fbs },
561 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
562 .driver_data = board_ahci_yes_fbs },
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
564 .driver_data = board_ahci_yes_fbs },
565 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
566 .driver_data = board_ahci_yes_fbs },
567 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
568 .driver_data = board_ahci_yes_fbs },
569 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
570 .driver_data = board_ahci_yes_fbs },
571
572 /* Promise */
573 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
574 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
575
576 /* Asmedia */
577 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
578 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
579 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
580 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
581 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
582 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
583
584 /*
585 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
586 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
587 */
588 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
589 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
590
591 /* Enmotus */
592 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
593
594 /* Generic, PCI class code for AHCI */
595 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
596 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
597
598 { } /* terminate list */
599};
600
601static const struct dev_pm_ops ahci_pci_pm_ops = {
602 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
603 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
604 ahci_pci_device_runtime_resume, NULL)
605};
606
607static struct pci_driver ahci_pci_driver = {
608 .name = DRV_NAME,
609 .id_table = ahci_pci_tbl,
610 .probe = ahci_init_one,
611 .remove = ahci_remove_one,
612 .driver = {
613 .pm = &ahci_pci_pm_ops,
614 },
615};
616
617#if IS_ENABLED(CONFIG_PATA_MARVELL)
618static int marvell_enable;
619#else
620static int marvell_enable = 1;
621#endif
622module_param(marvell_enable, int, 0644);
623MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
624
625static int mobile_lpm_policy = -1;
626module_param(mobile_lpm_policy, int, 0644);
627MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
628
629static void ahci_pci_save_initial_config(struct pci_dev *pdev,
630 struct ahci_host_priv *hpriv)
631{
632 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
633 dev_info(&pdev->dev, "JMB361 has only one port\n");
634 hpriv->force_port_map = 1;
635 }
636
637 /*
638 * Temporary Marvell 6145 hack: PATA port presence
639 * is asserted through the standard AHCI port
640 * presence register, as bit 4 (counting from 0)
641 */
642 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
643 if (pdev->device == 0x6121)
644 hpriv->mask_port_map = 0x3;
645 else
646 hpriv->mask_port_map = 0xf;
647 dev_info(&pdev->dev,
648 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
649 }
650
651 ahci_save_initial_config(&pdev->dev, hpriv);
652}
653
654static void ahci_pci_init_controller(struct ata_host *host)
655{
656 struct ahci_host_priv *hpriv = host->private_data;
657 struct pci_dev *pdev = to_pci_dev(host->dev);
658 void __iomem *port_mmio;
659 u32 tmp;
660 int mv;
661
662 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
663 if (pdev->device == 0x6121)
664 mv = 2;
665 else
666 mv = 4;
667 port_mmio = __ahci_port_base(host, mv);
668
669 writel(0, port_mmio + PORT_IRQ_MASK);
670
671 /* clear port IRQ */
672 tmp = readl(port_mmio + PORT_IRQ_STAT);
673 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
674 if (tmp)
675 writel(tmp, port_mmio + PORT_IRQ_STAT);
676 }
677
678 ahci_init_controller(host);
679}
680
681static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
682 unsigned long deadline)
683{
684 struct ata_port *ap = link->ap;
685 struct ahci_host_priv *hpriv = ap->host->private_data;
686 bool online;
687 int rc;
688
689 DPRINTK("ENTER\n");
690
691 hpriv->stop_engine(ap);
692
693 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
694 deadline, &online, NULL);
695
696 hpriv->start_engine(ap);
697
698 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
699
700 /* vt8251 doesn't clear BSY on signature FIS reception,
701 * request follow-up softreset.
702 */
703 return online ? -EAGAIN : rc;
704}
705
706static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
707 unsigned long deadline)
708{
709 struct ata_port *ap = link->ap;
710 struct ahci_port_priv *pp = ap->private_data;
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
713 struct ata_taskfile tf;
714 bool online;
715 int rc;
716
717 hpriv->stop_engine(ap);
718
719 /* clear D2H reception area to properly wait for D2H FIS */
720 ata_tf_init(link->device, &tf);
721 tf.command = ATA_BUSY;
722 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
723
724 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
725 deadline, &online, NULL);
726
727 hpriv->start_engine(ap);
728
729 /* The pseudo configuration device on SIMG4726 attached to
730 * ASUS P5W-DH Deluxe doesn't send signature FIS after
731 * hardreset if no device is attached to the first downstream
732 * port && the pseudo device locks up on SRST w/ PMP==0. To
733 * work around this, wait for !BSY only briefly. If BSY isn't
734 * cleared, perform CLO and proceed to IDENTIFY (achieved by
735 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
736 *
737 * Wait for two seconds. Devices attached to downstream port
738 * which can't process the following IDENTIFY after this will
739 * have to be reset again. For most cases, this should
740 * suffice while making probing snappish enough.
741 */
742 if (online) {
743 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
744 ahci_check_ready);
745 if (rc)
746 ahci_kick_engine(ap);
747 }
748 return rc;
749}
750
751/*
752 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
753 *
754 * It has been observed with some SSDs that the timing of events in the
755 * link synchronization phase can leave the port in a state that can not
756 * be recovered by a SATA-hard-reset alone. The failing signature is
757 * SStatus.DET stuck at 1 ("Device presence detected but Phy
758 * communication not established"). It was found that unloading and
759 * reloading the driver when this problem occurs allows the drive
760 * connection to be recovered (DET advanced to 0x3). The critical
761 * component of reloading the driver is that the port state machines are
762 * reset by bouncing "port enable" in the AHCI PCS configuration
763 * register. So, reproduce that effect by bouncing a port whenever we
764 * see DET==1 after a reset.
765 */
766static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
767 unsigned long deadline)
768{
769 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
770 struct ata_port *ap = link->ap;
771 struct ahci_port_priv *pp = ap->private_data;
772 struct ahci_host_priv *hpriv = ap->host->private_data;
773 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
774 unsigned long tmo = deadline - jiffies;
775 struct ata_taskfile tf;
776 bool online;
777 int rc, i;
778
779 DPRINTK("ENTER\n");
780
781 hpriv->stop_engine(ap);
782
783 for (i = 0; i < 2; i++) {
784 u16 val;
785 u32 sstatus;
786 int port = ap->port_no;
787 struct ata_host *host = ap->host;
788 struct pci_dev *pdev = to_pci_dev(host->dev);
789
790 /* clear D2H reception area to properly wait for D2H FIS */
791 ata_tf_init(link->device, &tf);
792 tf.command = ATA_BUSY;
793 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
794
795 rc = sata_link_hardreset(link, timing, deadline, &online,
796 ahci_check_ready);
797
798 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
799 (sstatus & 0xf) != 1)
800 break;
801
802 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
803 port);
804
805 pci_read_config_word(pdev, 0x92, &val);
806 val &= ~(1 << port);
807 pci_write_config_word(pdev, 0x92, val);
808 ata_msleep(ap, 1000);
809 val |= 1 << port;
810 pci_write_config_word(pdev, 0x92, val);
811 deadline += tmo;
812 }
813
814 hpriv->start_engine(ap);
815
816 if (online)
817 *class = ahci_dev_classify(ap);
818
819 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
820 return rc;
821}
822
823
824#ifdef CONFIG_PM
825static void ahci_pci_disable_interrupts(struct ata_host *host)
826{
827 struct ahci_host_priv *hpriv = host->private_data;
828 void __iomem *mmio = hpriv->mmio;
829 u32 ctl;
830
831 /* AHCI spec rev1.1 section 8.3.3:
832 * Software must disable interrupts prior to requesting a
833 * transition of the HBA to D3 state.
834 */
835 ctl = readl(mmio + HOST_CTL);
836 ctl &= ~HOST_IRQ_EN;
837 writel(ctl, mmio + HOST_CTL);
838 readl(mmio + HOST_CTL); /* flush */
839}
840
841static int ahci_pci_device_runtime_suspend(struct device *dev)
842{
843 struct pci_dev *pdev = to_pci_dev(dev);
844 struct ata_host *host = pci_get_drvdata(pdev);
845
846 ahci_pci_disable_interrupts(host);
847 return 0;
848}
849
850static int ahci_pci_device_runtime_resume(struct device *dev)
851{
852 struct pci_dev *pdev = to_pci_dev(dev);
853 struct ata_host *host = pci_get_drvdata(pdev);
854 int rc;
855
856 rc = ahci_reset_controller(host);
857 if (rc)
858 return rc;
859 ahci_pci_init_controller(host);
860 return 0;
861}
862
863#ifdef CONFIG_PM_SLEEP
864static int ahci_pci_device_suspend(struct device *dev)
865{
866 struct pci_dev *pdev = to_pci_dev(dev);
867 struct ata_host *host = pci_get_drvdata(pdev);
868 struct ahci_host_priv *hpriv = host->private_data;
869
870 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
871 dev_err(&pdev->dev,
872 "BIOS update required for suspend/resume\n");
873 return -EIO;
874 }
875
876 ahci_pci_disable_interrupts(host);
877 return ata_host_suspend(host, PMSG_SUSPEND);
878}
879
880static int ahci_pci_device_resume(struct device *dev)
881{
882 struct pci_dev *pdev = to_pci_dev(dev);
883 struct ata_host *host = pci_get_drvdata(pdev);
884 int rc;
885
886 /* Apple BIOS helpfully mangles the registers on resume */
887 if (is_mcp89_apple(pdev))
888 ahci_mcp89_apple_enable(pdev);
889
890 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
891 rc = ahci_reset_controller(host);
892 if (rc)
893 return rc;
894
895 ahci_pci_init_controller(host);
896 }
897
898 ata_host_resume(host);
899
900 return 0;
901}
902#endif
903
904#endif /* CONFIG_PM */
905
906static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
907{
908 int rc;
909
910 /*
911 * If the device fixup already set the dma_mask to some non-standard
912 * value, don't extend it here. This happens on STA2X11, for example.
913 */
914 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
915 return 0;
916
917 if (using_dac &&
918 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
919 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
920 if (rc) {
921 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
922 if (rc) {
923 dev_err(&pdev->dev,
924 "64-bit DMA enable failed\n");
925 return rc;
926 }
927 }
928 } else {
929 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
930 if (rc) {
931 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
932 return rc;
933 }
934 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
935 if (rc) {
936 dev_err(&pdev->dev,
937 "32-bit consistent DMA enable failed\n");
938 return rc;
939 }
940 }
941 return 0;
942}
943
944static void ahci_pci_print_info(struct ata_host *host)
945{
946 struct pci_dev *pdev = to_pci_dev(host->dev);
947 u16 cc;
948 const char *scc_s;
949
950 pci_read_config_word(pdev, 0x0a, &cc);
951 if (cc == PCI_CLASS_STORAGE_IDE)
952 scc_s = "IDE";
953 else if (cc == PCI_CLASS_STORAGE_SATA)
954 scc_s = "SATA";
955 else if (cc == PCI_CLASS_STORAGE_RAID)
956 scc_s = "RAID";
957 else
958 scc_s = "unknown";
959
960 ahci_print_info(host, scc_s);
961}
962
963/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
964 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
965 * support PMP and the 4726 either directly exports the device
966 * attached to the first downstream port or acts as a hardware storage
967 * controller and emulate a single ATA device (can be RAID 0/1 or some
968 * other configuration).
969 *
970 * When there's no device attached to the first downstream port of the
971 * 4726, "Config Disk" appears, which is a pseudo ATA device to
972 * configure the 4726. However, ATA emulation of the device is very
973 * lame. It doesn't send signature D2H Reg FIS after the initial
974 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
975 *
976 * The following function works around the problem by always using
977 * hardreset on the port and not depending on receiving signature FIS
978 * afterward. If signature FIS isn't received soon, ATA class is
979 * assumed without follow-up softreset.
980 */
981static void ahci_p5wdh_workaround(struct ata_host *host)
982{
983 static const struct dmi_system_id sysids[] = {
984 {
985 .ident = "P5W DH Deluxe",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR,
988 "ASUSTEK COMPUTER INC"),
989 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
990 },
991 },
992 { }
993 };
994 struct pci_dev *pdev = to_pci_dev(host->dev);
995
996 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
997 dmi_check_system(sysids)) {
998 struct ata_port *ap = host->ports[1];
999
1000 dev_info(&pdev->dev,
1001 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1002
1003 ap->ops = &ahci_p5wdh_ops;
1004 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1005 }
1006}
1007
1008/*
1009 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1010 * booting in BIOS compatibility mode. We restore the registers but not ID.
1011 */
1012static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1013{
1014 u32 val;
1015
1016 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1017
1018 pci_read_config_dword(pdev, 0xf8, &val);
1019 val |= 1 << 0x1b;
1020 /* the following changes the device ID, but appears not to affect function */
1021 /* val = (val & ~0xf0000000) | 0x80000000; */
1022 pci_write_config_dword(pdev, 0xf8, val);
1023
1024 pci_read_config_dword(pdev, 0x54c, &val);
1025 val |= 1 << 0xc;
1026 pci_write_config_dword(pdev, 0x54c, val);
1027
1028 pci_read_config_dword(pdev, 0x4a4, &val);
1029 val &= 0xff;
1030 val |= 0x01060100;
1031 pci_write_config_dword(pdev, 0x4a4, val);
1032
1033 pci_read_config_dword(pdev, 0x54c, &val);
1034 val &= ~(1 << 0xc);
1035 pci_write_config_dword(pdev, 0x54c, val);
1036
1037 pci_read_config_dword(pdev, 0xf8, &val);
1038 val &= ~(1 << 0x1b);
1039 pci_write_config_dword(pdev, 0xf8, val);
1040}
1041
1042static bool is_mcp89_apple(struct pci_dev *pdev)
1043{
1044 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1045 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1046 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1047 pdev->subsystem_device == 0xcb89;
1048}
1049
1050/* only some SB600 ahci controllers can do 64bit DMA */
1051static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1052{
1053 static const struct dmi_system_id sysids[] = {
1054 /*
1055 * The oldest version known to be broken is 0901 and
1056 * working is 1501 which was released on 2007-10-26.
1057 * Enable 64bit DMA on 1501 and anything newer.
1058 *
1059 * Please read bko#9412 for more info.
1060 */
1061 {
1062 .ident = "ASUS M2A-VM",
1063 .matches = {
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "ASUSTeK Computer INC."),
1066 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1067 },
1068 .driver_data = "20071026", /* yyyymmdd */
1069 },
1070 /*
1071 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1072 * support 64bit DMA.
1073 *
1074 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1075 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1076 * This spelling mistake was fixed in BIOS version 1.5, so
1077 * 1.5 and later have the Manufacturer as
1078 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1079 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1080 *
1081 * BIOS versions earlier than 1.9 had a Board Product Name
1082 * DMI field of "MS-7376". This was changed to be
1083 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1084 * match on DMI_BOARD_NAME of "MS-7376".
1085 */
1086 {
1087 .ident = "MSI K9A2 Platinum",
1088 .matches = {
1089 DMI_MATCH(DMI_BOARD_VENDOR,
1090 "MICRO-STAR INTER"),
1091 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1092 },
1093 },
1094 /*
1095 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1096 * 64bit DMA.
1097 *
1098 * This board also had the typo mentioned above in the
1099 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1100 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1101 */
1102 {
1103 .ident = "MSI K9AGM2",
1104 .matches = {
1105 DMI_MATCH(DMI_BOARD_VENDOR,
1106 "MICRO-STAR INTER"),
1107 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1108 },
1109 },
1110 /*
1111 * All BIOS versions for the Asus M3A support 64bit DMA.
1112 * (all release versions from 0301 to 1206 were tested)
1113 */
1114 {
1115 .ident = "ASUS M3A",
1116 .matches = {
1117 DMI_MATCH(DMI_BOARD_VENDOR,
1118 "ASUSTeK Computer INC."),
1119 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1120 },
1121 },
1122 { }
1123 };
1124 const struct dmi_system_id *match;
1125 int year, month, date;
1126 char buf[9];
1127
1128 match = dmi_first_match(sysids);
1129 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1130 !match)
1131 return false;
1132
1133 if (!match->driver_data)
1134 goto enable_64bit;
1135
1136 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1137 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1138
1139 if (strcmp(buf, match->driver_data) >= 0)
1140 goto enable_64bit;
1141 else {
1142 dev_warn(&pdev->dev,
1143 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1144 match->ident);
1145 return false;
1146 }
1147
1148enable_64bit:
1149 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1150 return true;
1151}
1152
1153static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1154{
1155 static const struct dmi_system_id broken_systems[] = {
1156 {
1157 .ident = "HP Compaq nx6310",
1158 .matches = {
1159 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1160 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1161 },
1162 /* PCI slot number of the controller */
1163 .driver_data = (void *)0x1FUL,
1164 },
1165 {
1166 .ident = "HP Compaq 6720s",
1167 .matches = {
1168 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1169 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1170 },
1171 /* PCI slot number of the controller */
1172 .driver_data = (void *)0x1FUL,
1173 },
1174
1175 { } /* terminate list */
1176 };
1177 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1178
1179 if (dmi) {
1180 unsigned long slot = (unsigned long)dmi->driver_data;
1181 /* apply the quirk only to on-board controllers */
1182 return slot == PCI_SLOT(pdev->devfn);
1183 }
1184
1185 return false;
1186}
1187
1188static bool ahci_broken_suspend(struct pci_dev *pdev)
1189{
1190 static const struct dmi_system_id sysids[] = {
1191 /*
1192 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1193 * to the harddisk doesn't become online after
1194 * resuming from STR. Warn and fail suspend.
1195 *
1196 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1197 *
1198 * Use dates instead of versions to match as HP is
1199 * apparently recycling both product and version
1200 * strings.
1201 *
1202 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1203 */
1204 {
1205 .ident = "dv4",
1206 .matches = {
1207 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1208 DMI_MATCH(DMI_PRODUCT_NAME,
1209 "HP Pavilion dv4 Notebook PC"),
1210 },
1211 .driver_data = "20090105", /* F.30 */
1212 },
1213 {
1214 .ident = "dv5",
1215 .matches = {
1216 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1217 DMI_MATCH(DMI_PRODUCT_NAME,
1218 "HP Pavilion dv5 Notebook PC"),
1219 },
1220 .driver_data = "20090506", /* F.16 */
1221 },
1222 {
1223 .ident = "dv6",
1224 .matches = {
1225 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1226 DMI_MATCH(DMI_PRODUCT_NAME,
1227 "HP Pavilion dv6 Notebook PC"),
1228 },
1229 .driver_data = "20090423", /* F.21 */
1230 },
1231 {
1232 .ident = "HDX18",
1233 .matches = {
1234 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1235 DMI_MATCH(DMI_PRODUCT_NAME,
1236 "HP HDX18 Notebook PC"),
1237 },
1238 .driver_data = "20090430", /* F.23 */
1239 },
1240 /*
1241 * Acer eMachines G725 has the same problem. BIOS
1242 * V1.03 is known to be broken. V3.04 is known to
1243 * work. Between, there are V1.06, V2.06 and V3.03
1244 * that we don't have much idea about. For now,
1245 * blacklist anything older than V3.04.
1246 *
1247 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1248 */
1249 {
1250 .ident = "G725",
1251 .matches = {
1252 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1253 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1254 },
1255 .driver_data = "20091216", /* V3.04 */
1256 },
1257 { } /* terminate list */
1258 };
1259 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1260 int year, month, date;
1261 char buf[9];
1262
1263 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1264 return false;
1265
1266 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1267 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1268
1269 return strcmp(buf, dmi->driver_data) < 0;
1270}
1271
1272static bool ahci_broken_lpm(struct pci_dev *pdev)
1273{
1274 static const struct dmi_system_id sysids[] = {
1275 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1276 {
1277 .matches = {
1278 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1279 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1280 },
1281 .driver_data = "20180406", /* 1.31 */
1282 },
1283 {
1284 .matches = {
1285 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1286 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1287 },
1288 .driver_data = "20180420", /* 1.28 */
1289 },
1290 {
1291 .matches = {
1292 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1293 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1294 },
1295 .driver_data = "20180315", /* 1.33 */
1296 },
1297 {
1298 .matches = {
1299 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1300 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1301 },
1302 /*
1303 * Note date based on release notes, 2.35 has been
1304 * reported to be good, but I've been unable to get
1305 * a hold of the reporter to get the DMI BIOS date.
1306 * TODO: fix this.
1307 */
1308 .driver_data = "20180310", /* 2.35 */
1309 },
1310 { } /* terminate list */
1311 };
1312 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1313 int year, month, date;
1314 char buf[9];
1315
1316 if (!dmi)
1317 return false;
1318
1319 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1320 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1321
1322 return strcmp(buf, dmi->driver_data) < 0;
1323}
1324
1325static bool ahci_broken_online(struct pci_dev *pdev)
1326{
1327#define ENCODE_BUSDEVFN(bus, slot, func) \
1328 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1329 static const struct dmi_system_id sysids[] = {
1330 /*
1331 * There are several gigabyte boards which use
1332 * SIMG5723s configured as hardware RAID. Certain
1333 * 5723 firmware revisions shipped there keep the link
1334 * online but fail to answer properly to SRST or
1335 * IDENTIFY when no device is attached downstream
1336 * causing libata to retry quite a few times leading
1337 * to excessive detection delay.
1338 *
1339 * As these firmwares respond to the second reset try
1340 * with invalid device signature, considering unknown
1341 * sig as offline works around the problem acceptably.
1342 */
1343 {
1344 .ident = "EP45-DQ6",
1345 .matches = {
1346 DMI_MATCH(DMI_BOARD_VENDOR,
1347 "Gigabyte Technology Co., Ltd."),
1348 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1349 },
1350 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1351 },
1352 {
1353 .ident = "EP45-DS5",
1354 .matches = {
1355 DMI_MATCH(DMI_BOARD_VENDOR,
1356 "Gigabyte Technology Co., Ltd."),
1357 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1358 },
1359 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1360 },
1361 { } /* terminate list */
1362 };
1363#undef ENCODE_BUSDEVFN
1364 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1365 unsigned int val;
1366
1367 if (!dmi)
1368 return false;
1369
1370 val = (unsigned long)dmi->driver_data;
1371
1372 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1373}
1374
1375static bool ahci_broken_devslp(struct pci_dev *pdev)
1376{
1377 /* device with broken DEVSLP but still showing SDS capability */
1378 static const struct pci_device_id ids[] = {
1379 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1380 {}
1381 };
1382
1383 return pci_match_id(ids, pdev);
1384}
1385
1386#ifdef CONFIG_ATA_ACPI
1387static void ahci_gtf_filter_workaround(struct ata_host *host)
1388{
1389 static const struct dmi_system_id sysids[] = {
1390 /*
1391 * Aspire 3810T issues a bunch of SATA enable commands
1392 * via _GTF including an invalid one and one which is
1393 * rejected by the device. Among the successful ones
1394 * is FPDMA non-zero offset enable which when enabled
1395 * only on the drive side leads to NCQ command
1396 * failures. Filter it out.
1397 */
1398 {
1399 .ident = "Aspire 3810T",
1400 .matches = {
1401 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1402 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1403 },
1404 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1405 },
1406 { }
1407 };
1408 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1409 unsigned int filter;
1410 int i;
1411
1412 if (!dmi)
1413 return;
1414
1415 filter = (unsigned long)dmi->driver_data;
1416 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1417 filter, dmi->ident);
1418
1419 for (i = 0; i < host->n_ports; i++) {
1420 struct ata_port *ap = host->ports[i];
1421 struct ata_link *link;
1422 struct ata_device *dev;
1423
1424 ata_for_each_link(link, ap, EDGE)
1425 ata_for_each_dev(dev, link, ALL)
1426 dev->gtf_filter |= filter;
1427 }
1428}
1429#else
1430static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1431{}
1432#endif
1433
1434/*
1435 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1436 * as DUMMY, or detected but eventually get a "link down" and never get up
1437 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1438 * port_map may hold a value of 0x00.
1439 *
1440 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1441 * and can significantly reduce the occurrence of the problem.
1442 *
1443 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1444 */
1445static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1446 struct pci_dev *pdev)
1447{
1448 static const struct dmi_system_id sysids[] = {
1449 {
1450 .ident = "Acer Switch Alpha 12",
1451 .matches = {
1452 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1453 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1454 },
1455 },
1456 { }
1457 };
1458
1459 if (dmi_check_system(sysids)) {
1460 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1461 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1462 hpriv->port_map = 0x7;
1463 hpriv->cap = 0xC734FF02;
1464 }
1465 }
1466}
1467
1468#ifdef CONFIG_ARM64
1469/*
1470 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1471 * Workaround is to make sure all pending IRQs are served before leaving
1472 * handler.
1473 */
1474static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1475{
1476 struct ata_host *host = dev_instance;
1477 struct ahci_host_priv *hpriv;
1478 unsigned int rc = 0;
1479 void __iomem *mmio;
1480 u32 irq_stat, irq_masked;
1481 unsigned int handled = 1;
1482
1483 VPRINTK("ENTER\n");
1484 hpriv = host->private_data;
1485 mmio = hpriv->mmio;
1486 irq_stat = readl(mmio + HOST_IRQ_STAT);
1487 if (!irq_stat)
1488 return IRQ_NONE;
1489
1490 do {
1491 irq_masked = irq_stat & hpriv->port_map;
1492 spin_lock(&host->lock);
1493 rc = ahci_handle_port_intr(host, irq_masked);
1494 if (!rc)
1495 handled = 0;
1496 writel(irq_stat, mmio + HOST_IRQ_STAT);
1497 irq_stat = readl(mmio + HOST_IRQ_STAT);
1498 spin_unlock(&host->lock);
1499 } while (irq_stat);
1500 VPRINTK("EXIT\n");
1501
1502 return IRQ_RETVAL(handled);
1503}
1504#endif
1505
1506static void ahci_remap_check(struct pci_dev *pdev, int bar,
1507 struct ahci_host_priv *hpriv)
1508{
1509 int i, count = 0;
1510 u32 cap;
1511
1512 /*
1513 * Check if this device might have remapped nvme devices.
1514 */
1515 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1516 pci_resource_len(pdev, bar) < SZ_512K ||
1517 bar != AHCI_PCI_BAR_STANDARD ||
1518 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1519 return;
1520
1521 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1522 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1523 if ((cap & (1 << i)) == 0)
1524 continue;
1525 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1526 != PCI_CLASS_STORAGE_EXPRESS)
1527 continue;
1528
1529 /* We've found a remapped device */
1530 count++;
1531 }
1532
1533 if (!count)
1534 return;
1535
1536 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1537 dev_warn(&pdev->dev,
1538 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1539
1540 /*
1541 * Don't rely on the msi-x capability in the remap case,
1542 * share the legacy interrupt across ahci and remapped devices.
1543 */
1544 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1545}
1546
1547static int ahci_get_irq_vector(struct ata_host *host, int port)
1548{
1549 return pci_irq_vector(to_pci_dev(host->dev), port);
1550}
1551
1552static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1553 struct ahci_host_priv *hpriv)
1554{
1555 int nvec;
1556
1557 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1558 return -ENODEV;
1559
1560 /*
1561 * If number of MSIs is less than number of ports then Sharing Last
1562 * Message mode could be enforced. In this case assume that advantage
1563 * of multipe MSIs is negated and use single MSI mode instead.
1564 */
1565 if (n_ports > 1) {
1566 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1567 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1568 if (nvec > 0) {
1569 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1570 hpriv->get_irq_vector = ahci_get_irq_vector;
1571 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1572 return nvec;
1573 }
1574
1575 /*
1576 * Fallback to single MSI mode if the controller
1577 * enforced MRSM mode.
1578 */
1579 printk(KERN_INFO
1580 "ahci: MRSM is on, fallback to single MSI\n");
1581 pci_free_irq_vectors(pdev);
1582 }
1583 }
1584
1585 /*
1586 * If the host is not capable of supporting per-port vectors, fall
1587 * back to single MSI before finally attempting single MSI-X.
1588 */
1589 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1590 if (nvec == 1)
1591 return nvec;
1592 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1593}
1594
1595static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1596 struct ahci_host_priv *hpriv)
1597{
1598 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1599
1600
1601 /* Ignore processing for non mobile platforms */
1602 if (!(hpriv->flags & AHCI_HFLAG_IS_MOBILE))
1603 return;
1604
1605 /* user modified policy via module param */
1606 if (mobile_lpm_policy != -1) {
1607 policy = mobile_lpm_policy;
1608 goto update_policy;
1609 }
1610
1611#ifdef CONFIG_ACPI
1612 if (policy > ATA_LPM_MED_POWER &&
1613 (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1614 if (hpriv->cap & HOST_CAP_PART)
1615 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1616 else if (hpriv->cap & HOST_CAP_SSC)
1617 policy = ATA_LPM_MIN_POWER;
1618 }
1619#endif
1620
1621update_policy:
1622 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1623 ap->target_lpm_policy = policy;
1624}
1625
1626static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1627{
1628 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1629 u16 tmp16;
1630
1631 /*
1632 * Only apply the 6-port PCS quirk for known legacy platforms.
1633 */
1634 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1635 return;
1636
1637 /* Skip applying the quirk on Denverton and beyond */
1638 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1639 return;
1640
1641 /*
1642 * port_map is determined from PORTS_IMPL PCI register which is
1643 * implemented as write or write-once register. If the register
1644 * isn't programmed, ahci automatically generates it from number
1645 * of ports, which is good enough for PCS programming. It is
1646 * otherwise expected that platform firmware enables the ports
1647 * before the OS boots.
1648 */
1649 pci_read_config_word(pdev, PCS_6, &tmp16);
1650 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1651 tmp16 |= hpriv->port_map;
1652 pci_write_config_word(pdev, PCS_6, tmp16);
1653 }
1654}
1655
1656static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1657{
1658 unsigned int board_id = ent->driver_data;
1659 struct ata_port_info pi = ahci_port_info[board_id];
1660 const struct ata_port_info *ppi[] = { &pi, NULL };
1661 struct device *dev = &pdev->dev;
1662 struct ahci_host_priv *hpriv;
1663 struct ata_host *host;
1664 int n_ports, i, rc;
1665 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1666
1667 VPRINTK("ENTER\n");
1668
1669 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1670
1671 ata_print_version_once(&pdev->dev, DRV_VERSION);
1672
1673 /* The AHCI driver can only drive the SATA ports, the PATA driver
1674 can drive them all so if both drivers are selected make sure
1675 AHCI stays out of the way */
1676 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1677 return -ENODEV;
1678
1679 /* Apple BIOS on MCP89 prevents us using AHCI */
1680 if (is_mcp89_apple(pdev))
1681 ahci_mcp89_apple_enable(pdev);
1682
1683 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1684 * At the moment, we can only use the AHCI mode. Let the users know
1685 * that for SAS drives they're out of luck.
1686 */
1687 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1688 dev_info(&pdev->dev,
1689 "PDC42819 can only drive SATA devices with this driver\n");
1690
1691 /* Some devices use non-standard BARs */
1692 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1693 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1694 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1695 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1696 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1697 if (pdev->device == 0xa01c)
1698 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1699 if (pdev->device == 0xa084)
1700 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1701 }
1702
1703 /* acquire resources */
1704 rc = pcim_enable_device(pdev);
1705 if (rc)
1706 return rc;
1707
1708 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1709 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1710 u8 map;
1711
1712 /* ICH6s share the same PCI ID for both piix and ahci
1713 * modes. Enabling ahci mode while MAP indicates
1714 * combined mode is a bad idea. Yield to ata_piix.
1715 */
1716 pci_read_config_byte(pdev, ICH_MAP, &map);
1717 if (map & 0x3) {
1718 dev_info(&pdev->dev,
1719 "controller is in combined mode, can't enable AHCI mode\n");
1720 return -ENODEV;
1721 }
1722 }
1723
1724 /* AHCI controllers often implement SFF compatible interface.
1725 * Grab all PCI BARs just in case.
1726 */
1727 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1728 if (rc == -EBUSY)
1729 pcim_pin_device(pdev);
1730 if (rc)
1731 return rc;
1732
1733 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1734 if (!hpriv)
1735 return -ENOMEM;
1736 hpriv->flags |= (unsigned long)pi.private_data;
1737
1738 /* MCP65 revision A1 and A2 can't do MSI */
1739 if (board_id == board_ahci_mcp65 &&
1740 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1741 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1742
1743 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1744 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1745 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1746
1747 /* only some SB600s can do 64bit DMA */
1748 if (ahci_sb600_enable_64bit(pdev))
1749 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1750
1751 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1752
1753 /* detect remapped nvme devices */
1754 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1755
1756 /* must set flag prior to save config in order to take effect */
1757 if (ahci_broken_devslp(pdev))
1758 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1759
1760#ifdef CONFIG_ARM64
1761 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1762 hpriv->irq_handler = ahci_thunderx_irq_handler;
1763#endif
1764
1765 /* save initial config */
1766 ahci_pci_save_initial_config(pdev, hpriv);
1767
1768 /*
1769 * If platform firmware failed to enable ports, try to enable
1770 * them here.
1771 */
1772 ahci_intel_pcs_quirk(pdev, hpriv);
1773
1774 /* prepare host */
1775 if (hpriv->cap & HOST_CAP_NCQ) {
1776 pi.flags |= ATA_FLAG_NCQ;
1777 /*
1778 * Auto-activate optimization is supposed to be
1779 * supported on all AHCI controllers indicating NCQ
1780 * capability, but it seems to be broken on some
1781 * chipsets including NVIDIAs.
1782 */
1783 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1784 pi.flags |= ATA_FLAG_FPDMA_AA;
1785
1786 /*
1787 * All AHCI controllers should be forward-compatible
1788 * with the new auxiliary field. This code should be
1789 * conditionalized if any buggy AHCI controllers are
1790 * encountered.
1791 */
1792 pi.flags |= ATA_FLAG_FPDMA_AUX;
1793 }
1794
1795 if (hpriv->cap & HOST_CAP_PMP)
1796 pi.flags |= ATA_FLAG_PMP;
1797
1798 ahci_set_em_messages(hpriv, &pi);
1799
1800 if (ahci_broken_system_poweroff(pdev)) {
1801 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1802 dev_info(&pdev->dev,
1803 "quirky BIOS, skipping spindown on poweroff\n");
1804 }
1805
1806 if (ahci_broken_lpm(pdev)) {
1807 pi.flags |= ATA_FLAG_NO_LPM;
1808 dev_warn(&pdev->dev,
1809 "BIOS update required for Link Power Management support\n");
1810 }
1811
1812 if (ahci_broken_suspend(pdev)) {
1813 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1814 dev_warn(&pdev->dev,
1815 "BIOS update required for suspend/resume\n");
1816 }
1817
1818 if (ahci_broken_online(pdev)) {
1819 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1820 dev_info(&pdev->dev,
1821 "online status unreliable, applying workaround\n");
1822 }
1823
1824
1825 /* Acer SA5-271 workaround modifies private_data */
1826 acer_sa5_271_workaround(hpriv, pdev);
1827
1828 /* CAP.NP sometimes indicate the index of the last enabled
1829 * port, at other times, that of the last possible port, so
1830 * determining the maximum port number requires looking at
1831 * both CAP.NP and port_map.
1832 */
1833 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1834
1835 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1836 if (!host)
1837 return -ENOMEM;
1838 host->private_data = hpriv;
1839
1840 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1841 /* legacy intx interrupts */
1842 pci_intx(pdev, 1);
1843 }
1844 hpriv->irq = pci_irq_vector(pdev, 0);
1845
1846 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1847 host->flags |= ATA_HOST_PARALLEL_SCAN;
1848 else
1849 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1850
1851 if (pi.flags & ATA_FLAG_EM)
1852 ahci_reset_em(host);
1853
1854 for (i = 0; i < host->n_ports; i++) {
1855 struct ata_port *ap = host->ports[i];
1856
1857 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1858 ata_port_pbar_desc(ap, ahci_pci_bar,
1859 0x100 + ap->port_no * 0x80, "port");
1860
1861 /* set enclosure management message type */
1862 if (ap->flags & ATA_FLAG_EM)
1863 ap->em_message_type = hpriv->em_msg_type;
1864
1865 ahci_update_initial_lpm_policy(ap, hpriv);
1866
1867 /* disabled/not-implemented port */
1868 if (!(hpriv->port_map & (1 << i)))
1869 ap->ops = &ata_dummy_port_ops;
1870 }
1871
1872 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1873 ahci_p5wdh_workaround(host);
1874
1875 /* apply gtf filter quirk */
1876 ahci_gtf_filter_workaround(host);
1877
1878 /* initialize adapter */
1879 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1880 if (rc)
1881 return rc;
1882
1883 rc = ahci_reset_controller(host);
1884 if (rc)
1885 return rc;
1886
1887 ahci_pci_init_controller(host);
1888 ahci_pci_print_info(host);
1889
1890 pci_set_master(pdev);
1891
1892 rc = ahci_host_activate(host, &ahci_sht);
1893 if (rc)
1894 return rc;
1895
1896 pm_runtime_put_noidle(&pdev->dev);
1897 return 0;
1898}
1899
1900static void ahci_remove_one(struct pci_dev *pdev)
1901{
1902 pm_runtime_get_noresume(&pdev->dev);
1903 ata_pci_remove_one(pdev);
1904}
1905
1906module_pci_driver(ahci_pci_driver);
1907
1908MODULE_AUTHOR("Jeff Garzik");
1909MODULE_DESCRIPTION("AHCI SATA low-level driver");
1910MODULE_LICENSE("GPL");
1911MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1912MODULE_VERSION(DRV_VERSION);