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192.168.1.100 / T800 / dbb8a26ec6904f3325225f3fba85191f4e3ac1ff / . / meta-sdk / meta / meta-lynqSDK-T800 / recipes-kernel / linux / files / mt2735.dtsi
blob: 19f1b9bdd5ad6353cab0480d5af42f7b0362751c [file] [log] [blame]
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 */
5
6/dts-v1/;
7#include <generated/autoconf.h>
8
9#include <dt-bindings/clock/mt6890-clk.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/mt2735-pinfunc.h>
13#include <dt-bindings/memory/mt6880-larb-port.h>
14#include <dt-bindings/power/mt6890-power.h>
15#include <dt-bindings/reset/ti-syscon.h>
16#include <dt-bindings/soc/mediatek,boot-mode.h>
17#include <dt-bindings/spmi/spmi.h>
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/phy/phy.h>
21#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
22#include <dt-bindings/iio/mt635x-auxadc.h>
23#include <dt-bindings/gce/mt6890-gce.h>
24#include <dt-bindings/thermal/thermal.h>
25/ {
26 model = "MT6890";
27 compatible = "mediatek,MT6890";
28 interrupt-parent = <&gic>;
29 #address-cells = <2>;
30 #size-cells = <2>;
31
32 /* chosen */
33 chosen: chosen {
34 bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
35 vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
36 firmware_class.path=/vendor/firmware \
37 page_owner=on";
38 };
39
40 psci {
41 compatible = "arm,psci-0.2";
42 method = "smc";
43 };
44
45 gpio_leds {
46 compatible = "gpio-leds";
47 led0 {
48 label = "led9501:red:sim";
49 gpios = <&pio 209 GPIO_ACTIVE_HIGH>;
50 linux,default-trigger = "none";
51 default-state = "off";
52 };
53 led1 {
54 label = "led9502:red:cellular-stat";
55 gpios = <&pio 210 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger = "none";
57 default-state = "off";
58 };
59 led2 {
60 label = "led9504:red:cellular-data";
61 gpios = <&pio 211 GPIO_ACTIVE_HIGH>;
62 linux,default-trigger = "none";
63 default-state = "off";
64 };
65 led3 {
66 label = "led9505:red:cellular-rat";
67 gpios = <&pio 212 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "none";
69 default-state = "off";
70 };
71 led4 {
72 label = "led9506:red:cellular-ims";
73 gpios = <&pio 213 GPIO_ACTIVE_HIGH>;
74 linux,default-trigger = "none";
75 default-state = "off";
76 };
77 };
78
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
82 opp0 {
83 opp-hz = /bits/ 64 <500000000>;
84 opp-microvolt = <650000>;
85 };
86 opp1 {
87 opp-hz = /bits/ 64 <600000000>;
88 opp-microvolt = <650000>;
89 };
90 opp2 {
91 opp-hz = /bits/ 64 <684000000>;
92 opp-microvolt = <668750>;
93 };
94 opp3 {
95 opp-hz = /bits/ 64 <768000000>;
96 opp-microvolt = <687500>;
97 };
98 opp4 {
99 opp-hz = /bits/ 64 <820000000>;
100 opp-microvolt = <700000>;
101 };
102 opp5 {
103 opp-hz = /bits/ 64 <937000000>;
104 opp-microvolt = <725000>;
105 };
106 opp6 {
107 opp-hz = /bits/ 64 <1060000000>;
108 opp-microvolt = <750000>;
109 };
110 opp7 {
111 opp-hz = /bits/ 64 <1134000000>;
112 opp-microvolt = <768750>;
113 };
114 opp8 {
115 opp-hz = /bits/ 64 <1275000000>;
116 opp-microvolt = <800000>;
117 };
118 opp9 {
119 opp-hz = /bits/ 64 <1387000000>;
120 opp-microvolt = <825000>;
121 };
122 opp10 {
123 opp-hz = /bits/ 64 <1500000000>;
124 opp-microvolt = <850000>;
125 };
126 opp11 {
127 opp-hz = /bits/ 64 <1666000000>;
128 opp-microvolt = <900000>;
129 };
130 opp12 {
131 opp-hz = /bits/ 64 <1750000000>;
132 opp-microvolt = <925000>;
133 };
134 opp13 {
135 opp-hz = /bits/ 64 <1833000000>;
136 opp-microvolt = <950000>;
137 };
138 opp14 {
139 opp-hz = /bits/ 64 <1916000000>;
140 opp-microvolt = <975000>;
141 };
142 opp15 {
143 opp-hz = /bits/ 64 <2000000000>;
144 opp-microvolt = <1000000>;
145 };
146 };
147
148 cpus {
149 #address-cells = <1>;
150 #size-cells = <0>;
151
152 cpu0: cpu@0 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a55";
155 reg = <0x0000>;
156 enable-method = "psci";
157 clock-frequency = <1701000000>;
158 operating-points-v2 = <&cluster0_opp>;
159 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
160 dynamic-power-coefficient = <85>;
161 #cooling-cells = <2>;
162 };
163
164 cpu1: cpu@001 {
165 device_type = "cpu";
166 compatible = "arm,cortex-a55";
167 reg = <0x0100>;
168 enable-method = "psci";
169 clock-frequency = <1701000000>;
170 operating-points-v2 = <&cluster0_opp>;
171 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
172 dynamic-power-coefficient = <85>;
173 #cooling-cells = <2>;
174 };
175
176 cpu2: cpu@002 {
177 device_type = "cpu";
178 compatible = "arm,cortex-a55";
179 reg = <0x0200>;
180 enable-method = "psci";
181 clock-frequency = <1701000000>;
182 operating-points-v2 = <&cluster0_opp>;
183 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
184 dynamic-power-coefficient = <85>;
185 #cooling-cells = <2>;
186 };
187
188 cpu3: cpu@003 {
189 device_type = "cpu";
190 compatible = "arm,cortex-a55";
191 reg = <0x0300>;
192 enable-method = "psci";
193 clock-frequency = <1701000000>;
194 operating-points-v2 = <&cluster0_opp>;
195 cpu-idle-states = <&cpuoff_l &clusteroff_l>;
196 dynamic-power-coefficient = <85>;
197 #cooling-cells = <2>;
198 };
199
200 cpu-map {
201 cluster0 {
202 core0 {
203 cpu = <&cpu0>;
204 };
205 core1 {
206 cpu = <&cpu1>;
207 };
208 core2 {
209 cpu = <&cpu2>;
210 };
211 core3 {
212 cpu = <&cpu3>;
213 };
214 };
215 };
216
217 idle-states {
218 entry-method = "arm,psci";
219 cpuoff_l: cpuoff_l {
220 compatible = "mediatek,idle-state";
221 arm,psci-suspend-param = <0x00010001>;
222 local-timer-stop;
223 entry-latency-us = <50>;
224 exit-latency-us = <100>;
225 min-residency-us = <1600>;
226 };
227 clusteroff_l: clusteroff_l {
228 compatible = "mediatek,idle-state";
229 arm,psci-suspend-param = <0x01010001>;
230 local-timer-stop;
231 entry-latency-us = <100>;
232 exit-latency-us = <250>;
233 min-residency-us = <2100>;
234 };
235 mcusysoff: mcusysoff {
236 compatible = "mediatek,idle-state";
237 arm,psci-suspend-param = <0x01010002>;
238 local-timer-stop;
239 entry-latency-us = <300>;
240 exit-latency-us = <1200>;
241 min-residency-us = <2600>;
242 };
243 };
244
245 };
246
247 pmu {
248 compatible = "arm,armv8-pmuv3";
249 interrupt-parent = <&gic>;
250 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
251 };
252
253 dsu-pmu-0 {
254 compatible = "arm,dsu-pmu";
255 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
256 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
257 };
258
259 dvfsp: dvfsp@0011bc00 {
260 compatible = "mediatek,mcupm-dvfsp";
261 reg = <0 0x0011bc00 0 0x1400>;
262 nvmem = <&efuse>;
263 nvmem-names = "mtk_efuse";
264 nvmem-cells = <&efuse_segment>;
265 nvmem-cell-names = "efuse_segment_cell";
266 };
267
268 leakage@1100b000 {
269 compatible = "mediatek,leakage";
270 reg = <0 0x1100b000 0 0x1000>;
271 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
272 nvmem = <&efuse>;
273 nvmem-names = "mtk_efuse";
274 nvmem-cells = <&efuse_segment>;
275 nvmem-cell-names = "efuse_segment_cell";
276 n-domain = <7>;
277 domain = "LL", "CCI", "VCORE", "MODEM_NR", "VSRAM_CPULL", "VSRAM_MODEM", "VCORE_OFF";
278 LL = <750 30 0x224 0 0 1>;
279 CCI = <750 30 0x220 24 0 1>;
280 VCORE = <750 30 0x21C 16 0 1>;
281 MODEM_NR = <825 30 0x21C 8 0 1>;
282 VSRAM_CPULL = <750 30 0X228 16 0 1>;
283 VSRAM_MODEM = <825 30 0X22C 0 0 1>;
284 VCORE_OFF = <550 30 0x224 16 0 1>;
285 };
286
287 memory {
288 device_type = "memory";
289#if defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 1024)
290 reg = <0 0x40000000 0 0x40000000>;
291#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 896)
292 reg = <0 0x40000000 0 0x38000000>;
293#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 768)
294 reg = <0 0x40000000 0 0x30000000>;
295#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 640)
296 reg = <0 0x40000000 0 0x28000000>;
297#else
298 reg = <0 0x40000000 0 0x20000000>;
299#endif
300 };
301
302 wed: wed@15010000 {
303 compatible = "mediatek,wed";
304 wed_num = <2>;
305 /* add this property for wed get the pci slot number. */
306 pci_slot_map = <0>, <1>;
307 reg = <0 0x15010000 0 0x1000>,
308 <0 0x15011000 0 0x1000>;
309 interrupt-parent = <&gic>;
310 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
312 };
313
314 wed2: wed2@15011000 {
315 compatible = "mediatek,wed2";
316 wed_num = <2>;
317 reg = <0 0x15010000 0 0x1000>,
318 <0 0x15011000 0 0x1000>;
319 interrupt-parent = <&gic>;
320 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
322 };
323
324 wdma: wdma@15102800 {
325 compatible = "mediatek,wed-wdma";
326 reg = <0 0x15102800 0 0x400>,
327 <0 0x15102c00 0 0x400>;
328 interrupt-parent = <&gic>;
329 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
335 };
336
337 ap2woccif: ap2woccif@151A9000 {
338 compatible = "mediatek,ap2woccif";
339 reg = <0 0x151a9000 0 0x1000>,
340 <0 0x151ab000 0 0x1000>;
341 interrupt-parent = <&gic>;
342 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
344 };
345
346 wocpu_sysram: wocpu@15180000 {
347 compatible = "mediatek,wocpu_sysram";
348 reg = <0 0x15180000 0 0x8000>;
349 shared = <1>;
350 };
351
352 wocpu_dlm: wocpu_dlm@1518E000 {
353 compatible = "mediatek,wocpu_dlm";
354 reg = <0 0x1518E000 0 0x2000>,
355 <0 0x15192000 0 0x2000>;
356
357 resets = <&ethsysrst 0>;
358 reset-names = "wocpu_rst";
359 };
360
361 cpu_boot: wocpu_boot@15194000 {
362 compatible = "mediatek,wocpu_boot";
363 reg = <0 0x15194000 0 0x1000>;
364 };
365
366 pcie_mirror: pcie_mirror@10201000 {
367 compatible = "mediatek,pcie-mirror";
368 reg = <0 0x10201000 0 0x1000>;
369 };
370
371 reserved_memory: reserved-memory {
372 #address-cells = <2>;
373 #size-cells = <2>;
374 ranges;
375
376 reserve-memory-atf {
377 compatible = "mediatek,reserve-memory-atf";
378 no-map;
379 reg = <0 0x42FC0000 0 0x1FA000>;
380 };
381
382 reserve-memory-mcupm_share {
383 compatible = "mediatek,reserve-memory-mcupm_share";
384 no-map;
385 status = "okay";
386#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
387 reg = <0 0x42290000 0 0x210000>; /* 2M + 64K */
388#else
389 reg = <0 0x42290000 0 0x610000>; /* 6M + 64K */
390#endif
391 };
392
393 reserve-memory-sspm_share {
394 compatible = "mediatek,reserve-memory-sspm_share";
395 no-map;
396 status = "okay";
397#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
398 reg = <0 0x429A0000 0 0x210000>; /* 2M + 64K */
399#else
400 reg = <0 0x429A0000 0 0x610000>; /* 6M + 64K */
401#endif
402 };
403
404 gps_mem: gps-reserve-memory {
405 compatible = "mediatek,gps-reserve-memory";
406 no-map;
407 reg = <0 0x432ca000 0 0x60000>; /* 384KB */
408 };
409
410 reserved-memory-pstore {
411 compatible = "ramoops";
412 reg = <0x0 0x4332a000 0x0 0xe0000>;
413 record-size = <0x1000>;
414 console-size = <0x40000>;
415 ftrace-size = <0x1000>;
416 pmsg-size = <0x10000>;
417 };
418
419 reserved-memory-aee {
420 reg = <0x0 0x4340a000 0x0 0x100000>;
421 compatible = "mediatek,aee-lk";
422 };
423
424 reserved-memory-minirdump {
425 reg = <0x0 0x4350a000 0x0 0x10000>;
426 no-map;
427 compatible = "mediatek,minirdump";
428 };
429
430 reserved-memory-ram_console {
431 reg = <0x0 0x4351a000 0x0 0x10000>;
432 no-map;
433 compatible = "mediatek,ram_console";
434 };
435
436 reserved-memory-log_store {
437 reg = <0x0 0x4352a000 0x0 0x40000>;
438 compatible = "mediatek,log_store";
439 };
440
441 wocpu0_emi: wocpu0_emi@50000000 {
442 compatible = "mediatek,wocpu0_emi";
443 no-map;
444 reg = <0 0x50000000 0 0x80000>;
445 shared = <0>;
446 };
447
448 wocpu1_emi: wocpu1_emi@50040000 {
449 compatible = "mediatek,wocpu1_emi";
450 no-map;
451 reg = <0 0x50080000 0 0x80000>;
452 shared = <0>;
453 };
454
455 wocpu_data: wocpu_data@50100000 {
456 compatible = "mediatek,wocpu_data";
457 no-map;
458 reg = <0 0x50100000 0 0x180000>;
459 shared = <1>;
460 };
461 };
462
463 gic: interrupt-controller {
464 compatible = "arm,gic-v3";
465 #interrupt-cells = <3>;
466 #address-cells = <2>;
467 #size-cells = <2>;
468 #redistributor-regions = <1>;
469 interrupt-parent = <&gic>;
470 interrupt-controller;
471 reg = <0 0x0c000000 0 0x40000>, // distributor
472 <0 0x0c040000 0 0x200000>; // redistributor
473 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
474 };
475
476 clkao: clkao {
477 compatible = "simple-bus";
478 };
479
480 clocks {
481 clk_null: clk_null {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 clock-frequency = <0>;
485 };
486
487 clk10m: clk10m {
488 compatible = "fixed-clock";
489 #clock-cells = <0>;
490 clock-frequency = <10000000>;
491 };
492
493 clk26m: clk26m {
494 compatible = "fixed-clock";
495 #clock-cells = <0>;
496 clock-frequency = <26000000>;
497 };
498
499 clk12m: clk12m {
500 compatible = "fixed-clock";
501 #clock-cells = <0>;
502 clock-frequency = <12000000>;
503 };
504
505 clk32k: clk32k {
506 compatible = "fixed-clock";
507 #clock-cells = <0>;
508 clock-frequency = <32000>;
509 };
510
511 clk13m: clk13m {
512 compatible = "fixed-clock";
513 #clock-cells = <0>;
514 clock-frequency = <13000000>;
515 };
516
517 ulposc: ulposc {
518 compatible = "fixed-clock";
519 #clock-cells = <0>;
520 clock-frequency = <260000000>;
521 };
522 };
523
524 topckgen_clk: syscon@10000000 {
525 compatible = "mediatek,mt6890-topckgen", "syscon";
526 reg = <0 0x10000000 0 0x1000>;
527 #clock-cells = <1>;
528 };
529
530 apmixedsys_clk: syscon@1000c000 {
531 compatible = "mediatek,mt6890-apmixedsys", "syscon";
532 reg = <0 0x1000c000 0 0xe00>;
533 #clock-cells=<1>;
534 };
535
536 dbgsys_dem_clk: syscon@0d0a0000 {
537 compatible = "mediatek,mt6890-dbgsys_dem", "syscon";
538 reg = <0 0x0d0a0000 0 0x1000>;
539 #clock-cells = <1>;
540 };
541
542 infracfg_ao_clk: syscon@10001000 {
543 compatible = "mediatek,mt6890-infracfg_ao", "syscon";
544 reg = <0 0x10001000 0 0x1000>;
545 #clock-cells = <1>;
546 };
547
548 pericfg_clk: syscon@10003000 {
549 compatible = "mediatek,mt6890-pericfg", "syscon";
550 reg = <0 0x10003000 0 0x1000>;
551 #clock-cells = <1>;
552 };
553
554 scpsys: power-controller@10006000 {
555 compatible = "mediatek,mt6890-scpsys", "syscon";
556 reg = <0 0x10006000 0 0x1000>;
557 #power-domain-cells = <1>;
558 infracfg = <&infracfg_ao_clk>;
559 clocks = <&topckgen_clk CLK_TOP_MM_SEL>,
560 <&topckgen_clk CLK_TOP_MFG_SEL>,
561 <&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
562 <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
563 <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
564 <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
565 <&topckgen_clk CLK_TOP_EIP97_SEL>,
566 <&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>;
567 clock-names = "mm",
568 "mfg",
569 "snps_eth_312p5m_sel",
570 "snps_eth_250m_sel",
571 "snps_ptp_sel",
572 "snps_rmii_sel",
573 "eip97_sel",
574 "audio";
575 /*status="disabled";*/
576 };
577
578 gce_clk: syscon@10228000 {
579 compatible = "mediatek,mt6890-gce", "syscon";
580 reg = <0 0x10228000 0 0x1000>;
581 #clock-cells = <1>;
582 };
583
584 audsys_clk: syscon@11210000 {
585 compatible = "mediatek,mt6890-audsys", "syscon";
586 reg = <0 0x11210000 0 0x1000>;
587 #clock-cells = <1>;
588 };
589
590 imp_iic_wrap_e_clk: syscon@11c46000 {
591 compatible = "mediatek,mt6890-imp_iic_wrap_e", "syscon";
592 reg = <0 0x11c46000 0 0x1000>;
593 #clock-cells = <1>;
594 };
595
596 mfgsys_clk: syscon@13fbf000 {
597 compatible = "mediatek,mt6890-mfgsys", "syscon";
598 reg = <0 0x13fbf000 0 0x1000>;
599 #clock-cells = <1>;
600 };
601
602 mmsys_config_clk: syson@14000000 {
603 compatible = "mediatek,mt6890-mmsys_config", "syscon";
604 reg = <0 0x14000000 0 0x1000>;
605 #clock-cells = <1>;
606 };
607
608 mtk_lpm: mtk_lpm {
609 compatible = "mediatek,mtk-lpm";
610 #address-cells = <2>;
611 #size-cells = <2>;
612 ranges;
613 suspend-method = "system";
614 irq-remain = <&edge_keypad &edge_mdwdt>;
615 resource-ctrl = <&bus26m &infra &syspll>,
616 <&dram_s0 &dram_s1>;
617 constraints = <&rc_bus26m &rc_syspll &rc_dram>;
618
619 lpm_sysram: lpm_sysram@0011b500 {
620 compatible = "mediatek,lpm-sysram";
621 reg = <0 0x0011b500 0 0x300>;
622 };
623
624 irq-remain-list {
625 edge_keypad: edge_keypad {
626 target = <&keypad>;
627 value = <1 0 0 0x4>;
628 };
629 edge_mdwdt: edge_mdwdt {
630 target = <&mddriver>;
631 value = <1 0 0 0x02000000>;
632 };
633 };
634 resource-ctrl-list {
635 bus26m: bus26m {
636 id = <0x00000000>;
637 value = <0>;
638 };
639 infra: infra {
640 id = <0x00000001>;
641 value = <0>;
642 };
643 syspll: syspll {
644 id = <0x00000002>;
645 value = <0>;
646 };
647 dram_s0: dram_s0 {
648 id = <0x00000003>;
649 value = <0>;
650 };
651 dram_s1: dram_s1 {
652 id = <0x00000004>;
653 value = <0>;
654 };
655 };
656 constraint-list {
657 rc_bus26m: rc_bus26m {
658 id = <0x00000000>;
659 value = <1>;
660 };
661 rc_syspll: rc_syspll {
662 id = <0x00000001>;
663 value = <1>;
664 };
665 rc_dram: rc_dram {
666 id = <0x00000002>;
667 value = <1>;
668 };
669 };
670 };
671
672 cpupm_sysram: cpupm-sysram@0011b000 {
673 compatible = "mediatek,cpupm-sysram";
674 reg = <0 0x0011b000 0 0x500>;
675 };
676
677 mcusys_ctrl: mcusys-ctrl@0c53a000 {
678 compatible = "mediatek,mcusys-ctrl";
679 reg = <0 0x0c53a000 0 0x1000>;
680 };
681
682 tboard_thermistor1: thermal-ntc1 {
683 compatible = "mediatek,mt6880-board-ntc";
684 #thermal-sensor-cells = <0>;
685 reg = <0 0x1001C0D4 0 0x4>; /* TIA DATA T0 */
686 pmic_auxadc = <&pmic_auxadc>;
687 temperature-lookup-table = <
688 (-40000) 4397119
689 (-39000) 4092874
690 (-38000) 3811717
691 (-37000) 3551749
692 (-36000) 3311236
693 (-35000) 3088599
694 (-34000) 2882396
695 (-33000) 2691310
696 (-32000) 2514137
697 (-31000) 2349778
698 (-30000) 2197225
699 (-29000) 2055558
700 (-28000) 1923932
701 (-27000) 1801573
702 (-26000) 1687773
703 (-25000) 1581881
704 (-24000) 1483100
705 (-23000) 1391113
706 (-22000) 1305413
707 (-21000) 1225531
708 (-20000) 1151037
709 (-19000) 1081535
710 (-18000) 1016661
711 (-17000) 956080
712 (-16000) 899481
713 (-15000) 846579
714 (-14000) 797111
715 (-13000) 750834
716 (-12000) 707524
717 (-11000) 666972
718 (-10000) 628988
719 (-9000) 593342
720 (-8000) 559931
721 (-7000) 528602
722 (-6000) 499212
723 (-5000) 471632
724 (-4000) 445772
725 (-3000) 421480
726 (-2000) 398652
727 (-1000) 377193
728 0 357012
729 1000 338006
730 2000 320122
731 3000 303287
732 4000 287434
733 5000 272500
734 6000 258426
735 7000 245160
736 8000 232649
737 9000 220847
738 10000 209710
739 11000 199196
740 12000 189268
741 13000 179890
742 14000 171027
743 15000 162651
744 16000 154726
745 17000 147232
746 18000 140142
747 19000 133432
748 20000 127080
749 21000 121066
750 22000 115368
751 23000 109970
752 24000 104852
753 25000 100000
754 26000 95398
755 27000 91032
756 28000 86889
757 29000 82956
758 30000 79222
759 31000 75675
760 32000 72306
761 33000 69104
762 34000 66061
763 35000 63167
764 36000 60415
765 37000 57797
766 38000 55306
767 39000 52934
768 40000 50677
769 41000 48528
770 42000 46482
771 43000 44533
772 44000 42675
773 45000 40904
774 46000 39213
775 47000 37601
776 48000 36063
777 49000 34595
778 50000 33195
779 51000 31859
780 52000 30584
781 53000 29366
782 54000 28203
783 55000 27091
784 56000 26028
785 57000 25013
786 58000 24042
787 59000 23113
788 60000 22224
789 61000 21374
790 62000 20560
791 63000 19782
792 64000 19036
793 65000 18322
794 66000 17640
795 67000 16986
796 68000 16360
797 69000 15759
798 70000 15184
799 71000 14631
800 72000 14100
801 73000 13591
802 74000 13103
803 75000 12635
804 76000 12187
805 77000 11756
806 78000 11343
807 79000 10946
808 80000 10565
809 81000 10199
810 82000 9847
811 83000 9509
812 84000 9184
813 85000 8872
814 86000 8572
815 87000 8283
816 88000 8005
817 89000 7738
818 90000 7481
819 91000 7234
820 92000 6997
821 93000 6769
822 94000 6548
823 95000 6337
824 96000 6132
825 97000 5934
826 98000 5744
827 99000 5561
828 100000 5384
829 101000 5214
830 102000 5051
831 103000 4893
832 104000 4741
833 105000 4594
834 106000 4453
835 107000 4316
836 108000 4184
837 109000 4057
838 110000 3934
839 111000 3816
840 112000 3701
841 113000 3591
842 114000 3484
843 115000 3380
844 116000 3281
845 117000 3185
846 118000 3093
847 119000 3003
848 120000 2916
849 121000 2832
850 122000 2751
851 123000 2672
852 124000 2596
853 125000 2522>;
854 };
855
856 tboard_thermistor2: thermal-ntc2 {
857 compatible = "mediatek,mt6880-board-ntc";
858 #thermal-sensor-cells = <0>;
859 reg = <0 0x1001C0D8 0 0x4>; /* TIA DATA T1 */
860 pmic_auxadc = <&pmic_auxadc>;
861 temperature-lookup-table = <
862 (-40000) 4397119
863 (-39000) 4092874
864 (-38000) 3811717
865 (-37000) 3551749
866 (-36000) 3311236
867 (-35000) 3088599
868 (-34000) 2882396
869 (-33000) 2691310
870 (-32000) 2514137
871 (-31000) 2349778
872 (-30000) 2197225
873 (-29000) 2055558
874 (-28000) 1923932
875 (-27000) 1801573
876 (-26000) 1687773
877 (-25000) 1581881
878 (-24000) 1483100
879 (-23000) 1391113
880 (-22000) 1305413
881 (-21000) 1225531
882 (-20000) 1151037
883 (-19000) 1081535
884 (-18000) 1016661
885 (-17000) 956080
886 (-16000) 899481
887 (-15000) 846579
888 (-14000) 797111
889 (-13000) 750834
890 (-12000) 707524
891 (-11000) 666972
892 (-10000) 628988
893 (-9000) 593342
894 (-8000) 559931
895 (-7000) 528602
896 (-6000) 499212
897 (-5000) 471632
898 (-4000) 445772
899 (-3000) 421480
900 (-2000) 398652
901 (-1000) 377193
902 0 357012
903 1000 338006
904 2000 320122
905 3000 303287
906 4000 287434
907 5000 272500
908 6000 258426
909 7000 245160
910 8000 232649
911 9000 220847
912 10000 209710
913 11000 199196
914 12000 189268
915 13000 179890
916 14000 171027
917 15000 162651
918 16000 154726
919 17000 147232
920 18000 140142
921 19000 133432
922 20000 127080
923 21000 121066
924 22000 115368
925 23000 109970
926 24000 104852
927 25000 100000
928 26000 95398
929 27000 91032
930 28000 86889
931 29000 82956
932 30000 79222
933 31000 75675
934 32000 72306
935 33000 69104
936 34000 66061
937 35000 63167
938 36000 60415
939 37000 57797
940 38000 55306
941 39000 52934
942 40000 50677
943 41000 48528
944 42000 46482
945 43000 44533
946 44000 42675
947 45000 40904
948 46000 39213
949 47000 37601
950 48000 36063
951 49000 34595
952 50000 33195
953 51000 31859
954 52000 30584
955 53000 29366
956 54000 28203
957 55000 27091
958 56000 26028
959 57000 25013
960 58000 24042
961 59000 23113
962 60000 22224
963 61000 21374
964 62000 20560
965 63000 19782
966 64000 19036
967 65000 18322
968 66000 17640
969 67000 16986
970 68000 16360
971 69000 15759
972 70000 15184
973 71000 14631
974 72000 14100
975 73000 13591
976 74000 13103
977 75000 12635
978 76000 12187
979 77000 11756
980 78000 11343
981 79000 10946
982 80000 10565
983 81000 10199
984 82000 9847
985 83000 9509
986 84000 9184
987 85000 8872
988 86000 8572
989 87000 8283
990 88000 8005
991 89000 7738
992 90000 7481
993 91000 7234
994 92000 6997
995 93000 6769
996 94000 6548
997 95000 6337
998 96000 6132
999 97000 5934
1000 98000 5744
1001 99000 5561
1002 100000 5384
1003 101000 5214
1004 102000 5051
1005 103000 4893
1006 104000 4741
1007 105000 4594
1008 106000 4453
1009 107000 4316
1010 108000 4184
1011 109000 4057
1012 110000 3934
1013 111000 3816
1014 112000 3701
1015 113000 3591
1016 114000 3484
1017 115000 3380
1018 116000 3281
1019 117000 3185
1020 118000 3093
1021 119000 3003
1022 120000 2916
1023 121000 2832
1024 122000 2751
1025 123000 2672
1026 124000 2596
1027 125000 2522>;
1028 };
1029
1030 tboard_thermistor3: thermal-ntc3 {
1031 compatible = "mediatek,mt6880-board-ntc";
1032 #thermal-sensor-cells = <0>;
1033 reg = <0 0x1001C0DC 0 0x4>; /* TIA DATA T2 */
1034 pmic_auxadc = <&pmic_auxadc>;
1035 temperature-lookup-table = <
1036 (-40000) 4397119
1037 (-39000) 4092874
1038 (-38000) 3811717
1039 (-37000) 3551749
1040 (-36000) 3311236
1041 (-35000) 3088599
1042 (-34000) 2882396
1043 (-33000) 2691310
1044 (-32000) 2514137
1045 (-31000) 2349778
1046 (-30000) 2197225
1047 (-29000) 2055558
1048 (-28000) 1923932
1049 (-27000) 1801573
1050 (-26000) 1687773
1051 (-25000) 1581881
1052 (-24000) 1483100
1053 (-23000) 1391113
1054 (-22000) 1305413
1055 (-21000) 1225531
1056 (-20000) 1151037
1057 (-19000) 1081535
1058 (-18000) 1016661
1059 (-17000) 956080
1060 (-16000) 899481
1061 (-15000) 846579
1062 (-14000) 797111
1063 (-13000) 750834
1064 (-12000) 707524
1065 (-11000) 666972
1066 (-10000) 628988
1067 (-9000) 593342
1068 (-8000) 559931
1069 (-7000) 528602
1070 (-6000) 499212
1071 (-5000) 471632
1072 (-4000) 445772
1073 (-3000) 421480
1074 (-2000) 398652
1075 (-1000) 377193
1076 0 357012
1077 1000 338006
1078 2000 320122
1079 3000 303287
1080 4000 287434
1081 5000 272500
1082 6000 258426
1083 7000 245160
1084 8000 232649
1085 9000 220847
1086 10000 209710
1087 11000 199196
1088 12000 189268
1089 13000 179890
1090 14000 171027
1091 15000 162651
1092 16000 154726
1093 17000 147232
1094 18000 140142
1095 19000 133432
1096 20000 127080
1097 21000 121066
1098 22000 115368
1099 23000 109970
1100 24000 104852
1101 25000 100000
1102 26000 95398
1103 27000 91032
1104 28000 86889
1105 29000 82956
1106 30000 79222
1107 31000 75675
1108 32000 72306
1109 33000 69104
1110 34000 66061
1111 35000 63167
1112 36000 60415
1113 37000 57797
1114 38000 55306
1115 39000 52934
1116 40000 50677
1117 41000 48528
1118 42000 46482
1119 43000 44533
1120 44000 42675
1121 45000 40904
1122 46000 39213
1123 47000 37601
1124 48000 36063
1125 49000 34595
1126 50000 33195
1127 51000 31859
1128 52000 30584
1129 53000 29366
1130 54000 28203
1131 55000 27091
1132 56000 26028
1133 57000 25013
1134 58000 24042
1135 59000 23113
1136 60000 22224
1137 61000 21374
1138 62000 20560
1139 63000 19782
1140 64000 19036
1141 65000 18322
1142 66000 17640
1143 67000 16986
1144 68000 16360
1145 69000 15759
1146 70000 15184
1147 71000 14631
1148 72000 14100
1149 73000 13591
1150 74000 13103
1151 75000 12635
1152 76000 12187
1153 77000 11756
1154 78000 11343
1155 79000 10946
1156 80000 10565
1157 81000 10199
1158 82000 9847
1159 83000 9509
1160 84000 9184
1161 85000 8872
1162 86000 8572
1163 87000 8283
1164 88000 8005
1165 89000 7738
1166 90000 7481
1167 91000 7234
1168 92000 6997
1169 93000 6769
1170 94000 6548
1171 95000 6337
1172 96000 6132
1173 97000 5934
1174 98000 5744
1175 99000 5561
1176 100000 5384
1177 101000 5214
1178 102000 5051
1179 103000 4893
1180 104000 4741
1181 105000 4594
1182 106000 4453
1183 107000 4316
1184 108000 4184
1185 109000 4057
1186 110000 3934
1187 111000 3816
1188 112000 3701
1189 113000 3591
1190 114000 3484
1191 115000 3380
1192 116000 3281
1193 117000 3185
1194 118000 3093
1195 119000 3003
1196 120000 2916
1197 121000 2832
1198 122000 2751
1199 123000 2672
1200 124000 2596
1201 125000 2522>;
1202 };
1203
1204 tboard_thermistor4: thermal-ntc4 {
1205 compatible = "mediatek,mt6880-board-ntc";
1206 #thermal-sensor-cells = <0>;
1207 reg = <0 0x1001C0E0 0 0x4>; /* TIA DATA T3 */
1208 pmic_auxadc = <&pmic_auxadc>;
1209 temperature-lookup-table = <
1210 (-40000) 4397119
1211 (-39000) 4092874
1212 (-38000) 3811717
1213 (-37000) 3551749
1214 (-36000) 3311236
1215 (-35000) 3088599
1216 (-34000) 2882396
1217 (-33000) 2691310
1218 (-32000) 2514137
1219 (-31000) 2349778
1220 (-30000) 2197225
1221 (-29000) 2055558
1222 (-28000) 1923932
1223 (-27000) 1801573
1224 (-26000) 1687773
1225 (-25000) 1581881
1226 (-24000) 1483100
1227 (-23000) 1391113
1228 (-22000) 1305413
1229 (-21000) 1225531
1230 (-20000) 1151037
1231 (-19000) 1081535
1232 (-18000) 1016661
1233 (-17000) 956080
1234 (-16000) 899481
1235 (-15000) 846579
1236 (-14000) 797111
1237 (-13000) 750834
1238 (-12000) 707524
1239 (-11000) 666972
1240 (-10000) 628988
1241 (-9000) 593342
1242 (-8000) 559931
1243 (-7000) 528602
1244 (-6000) 499212
1245 (-5000) 471632
1246 (-4000) 445772
1247 (-3000) 421480
1248 (-2000) 398652
1249 (-1000) 377193
1250 0 357012
1251 1000 338006
1252 2000 320122
1253 3000 303287
1254 4000 287434
1255 5000 272500
1256 6000 258426
1257 7000 245160
1258 8000 232649
1259 9000 220847
1260 10000 209710
1261 11000 199196
1262 12000 189268
1263 13000 179890
1264 14000 171027
1265 15000 162651
1266 16000 154726
1267 17000 147232
1268 18000 140142
1269 19000 133432
1270 20000 127080
1271 21000 121066
1272 22000 115368
1273 23000 109970
1274 24000 104852
1275 25000 100000
1276 26000 95398
1277 27000 91032
1278 28000 86889
1279 29000 82956
1280 30000 79222
1281 31000 75675
1282 32000 72306
1283 33000 69104
1284 34000 66061
1285 35000 63167
1286 36000 60415
1287 37000 57797
1288 38000 55306
1289 39000 52934
1290 40000 50677
1291 41000 48528
1292 42000 46482
1293 43000 44533
1294 44000 42675
1295 45000 40904
1296 46000 39213
1297 47000 37601
1298 48000 36063
1299 49000 34595
1300 50000 33195
1301 51000 31859
1302 52000 30584
1303 53000 29366
1304 54000 28203
1305 55000 27091
1306 56000 26028
1307 57000 25013
1308 58000 24042
1309 59000 23113
1310 60000 22224
1311 61000 21374
1312 62000 20560
1313 63000 19782
1314 64000 19036
1315 65000 18322
1316 66000 17640
1317 67000 16986
1318 68000 16360
1319 69000 15759
1320 70000 15184
1321 71000 14631
1322 72000 14100
1323 73000 13591
1324 74000 13103
1325 75000 12635
1326 76000 12187
1327 77000 11756
1328 78000 11343
1329 79000 10946
1330 80000 10565
1331 81000 10199
1332 82000 9847
1333 83000 9509
1334 84000 9184
1335 85000 8872
1336 86000 8572
1337 87000 8283
1338 88000 8005
1339 89000 7738
1340 90000 7481
1341 91000 7234
1342 92000 6997
1343 93000 6769
1344 94000 6548
1345 95000 6337
1346 96000 6132
1347 97000 5934
1348 98000 5744
1349 99000 5561
1350 100000 5384
1351 101000 5214
1352 102000 5051
1353 103000 4893
1354 104000 4741
1355 105000 4594
1356 106000 4453
1357 107000 4316
1358 108000 4184
1359 109000 4057
1360 110000 3934
1361 111000 3816
1362 112000 3701
1363 113000 3591
1364 114000 3484
1365 115000 3380
1366 116000 3281
1367 117000 3185
1368 118000 3093
1369 119000 3003
1370 120000 2916
1371 121000 2832
1372 122000 2751
1373 123000 2672
1374 124000 2596
1375 125000 2522>;
1376 };
1377
1378 trm: thermal_risk_monitor {
1379 compatible = "mediatek,mt6880-trm";
1380 };
1381
1382 pmic_temp: pmic_temp {
1383 compatible = "mediatek,mt6330-pmic-temp";
1384 io-channels =
1385 <&pmic_auxadc AUXADC_CHIP_TEMP>;
1386 io-channel-names =
1387 "pmic_chip_temp";
1388
1389 #thermal-sensor-cells = <0>;
1390 nvmem-cells = <&thermal_efuse_data1>;
1391 nvmem-cell-names = "t_e_data1@6c";
1392 pmic_temp,cali_factor = <1681>;
1393 pmic_temp,iio_chan = <0>;
1394 };
1395
1396 pmic_vcore: pmic_vcore {
1397 compatible = "mediatek,mt6330-pmic-temp";
1398 io-channels =
1399 <&pmic_auxadc AUXADC_VCORE_TEMP>;
1400 io-channel-names =
1401 "pmic_buck1_temp";
1402
1403 #thermal-sensor-cells = <0>;
1404 nvmem-cells = <&thermal_efuse_data1>;
1405 nvmem-cell-names = "t_e_data1@6c";
1406 pmic_temp,cali_factor = <1863>;
1407 pmic_temp,iio_chan = <1>;
1408 };
1409
1410 pmic_vproc: pmic_vproc {
1411 compatible = "mediatek,mt6330-pmic-temp";
1412 io-channels =
1413 <&pmic_auxadc AUXADC_VPROC_TEMP>;
1414 io-channel-names =
1415 "pmic_buck2_temp";
1416 #thermal-sensor-cells = <0>;
1417 nvmem-cells = <&thermal_efuse_data1>;
1418 nvmem-cell-names = "t_e_data1@6c";
1419 pmic_temp,cali_factor = <1863>;
1420 pmic_temp,iio_chan = <2>;
1421 };
1422
1423 pmic_vgpu: pmic_vgpu {
1424 compatible = "mediatek,mt6330-pmic-temp";
1425 io-channels =
1426 <&pmic_auxadc AUXADC_VGPU_TEMP>;
1427 io-channel-names =
1428 "pmic_buck3_temp";
1429 #thermal-sensor-cells = <0>;
1430 nvmem-cells = <&thermal_efuse_data1>;
1431 nvmem-cell-names = "t_e_data1@6c";
1432 pmic_temp,cali_factor = <1863>;
1433 pmic_temp,iio_chan = <3>;
1434 };
1435
1436 md_rf_ic: md-rf-ic {
1437 compatible = "mediatek,md-rf";
1438 #thermal-sensor-cells = <0>;
1439 };
1440
1441 md_cooler_mutt: mutt {
1442 compatible = "mediatek,mt6297-md-cooler-mutt";
1443 mutt_pa1: mutt-pa1 {
1444 id = <0>;
1445 #cooling-cells = <2>;
1446 };
1447 mutt_pa1_no_ims: mutt-pa1-no-ims {
1448 id = <0>;
1449 #cooling-cells = <2>;
1450 };
1451 mutt_pa2: mutt-pa2 {
1452 id = <1>;
1453 #cooling-cells = <2>;
1454 };
1455 mutt_pa2_no_ims: mutt-pa2-no-ims {
1456 id = <1>;
1457 #cooling-cells = <2>;
1458 };
1459 };
1460 md_cooler_tx_pwr: tx-pwr {
1461 compatible = "mediatek,md-cooler-tx-pwr";
1462 tx_pwr_pa1: tx-pwr-pa1 {
1463 id = <0>;
1464 #cooling-cells = <2>;
1465 };
1466 tx_pwr_pa2: tx-pwr-pa2 {
1467 id = <1>;
1468 #cooling-cells = <2>;
1469 };
1470 };
1471 md_cooler_scg_off: scg-off {
1472 compatible = "mediatek,md-cooler-scg-off";
1473 scg_off_pa2: scg-off-pa2 {
1474 id = <1>;
1475 #cooling-cells = <2>;
1476 };
1477 };
1478
1479 thermal-zones {
1480 soc_max {
1481 polling-delay = <100>; /* milliseconds */
1482 polling-delay-passive = <50>; /* milliseconds */
1483 thermal-sensors = <&lvts 0>;
1484 sustainable-power = <1700>;
1485
1486 trips {
1487 threshold: trip-point@0 {
1488 temperature = <85000>;
1489 hysteresis = <2000>;
1490 type = "passive";
1491 };
1492
1493 ipa_target: trip-point@1 {
1494 temperature = <95000>;
1495 hysteresis = <2000>;
1496 type = "passive";
1497 };
1498
1499 soc_max_crit: soc_max_crit@0 {
1500 temperature = <115000>;
1501 hysteresis = <2000>;
1502 type = "critical";
1503 };
1504 };
1505
1506 cooling-maps {
1507 map0 {
1508 trip = <&ipa_target>;
1509 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1510 contribution = <1024>;
1511 };
1512
1513 map1 {
1514 trip = <&ipa_target>;
1515 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1516 contribution = <1024>;
1517 };
1518 };
1519 };
1520
1521 cpu_little0 {
1522 polling-delay = <0>; /* milliseconds */
1523 polling-delay-passive = <0>; /* milliseconds */
1524 thermal-sensors = <&lvts 1>;
1525 };
1526
1527 cpu_little1 {
1528 polling-delay = <0>; /* milliseconds */
1529 polling-delay-passive = <0>; /* milliseconds */
1530 thermal-sensors = <&lvts 2>;
1531 };
1532
1533 cpu_little2 {
1534 polling-delay = <0>; /* milliseconds */
1535 polling-delay-passive = <0>; /* milliseconds */
1536 thermal-sensors = <&lvts 3>;
1537 };
1538
1539 cpu_little3 {
1540 polling-delay = <0>; /* milliseconds */
1541 polling-delay-passive = <0>; /* milliseconds */
1542 thermal-sensors = <&lvts 4>;
1543 };
1544
1545 gpu0 {
1546 polling-delay = <0>; /* milliseconds */
1547 polling-delay-passive = <0>; /* milliseconds */
1548 thermal-sensors = <&lvts 5>;
1549 };
1550
1551 gpu1 {
1552 polling-delay = <0>; /* milliseconds */
1553 polling-delay-passive = <0>; /* milliseconds */
1554 thermal-sensors = <&lvts 6>;
1555 };
1556
1557 dramc {
1558 polling-delay = <0>; /* milliseconds */
1559 polling-delay-passive = <0>; /* milliseconds */
1560 thermal-sensors = <&lvts 7>;
1561 };
1562
1563 mmsys {
1564 polling-delay = <0>; /* milliseconds */
1565 polling-delay-passive = <0>; /* milliseconds */
1566 thermal-sensors = <&lvts 8>;
1567 };
1568
1569 md_5g {
1570 polling-delay = <0>; /* milliseconds */
1571 polling-delay-passive = <0>; /* milliseconds */
1572 thermal-sensors = <&lvts 9>;
1573 };
1574
1575 md_4g {
1576 polling-delay = <0>; /* milliseconds */
1577 polling-delay-passive = <0>; /* milliseconds */
1578 thermal-sensors = <&lvts 10>;
1579 };
1580
1581 md_3g {
1582 polling-delay = <0>; /* milliseconds */
1583 polling-delay-passive = <0>; /* milliseconds */
1584 thermal-sensors = <&lvts 11>;
1585 };
1586
1587 soc_dram_ntc {
1588 polling-delay = <1000>; /* milliseconds */
1589 polling-delay-passive = <1000>; /* milliseconds */
1590 thermal-sensors = <&tboard_thermistor1>;
1591
1592 trips {
1593 soc_dram_ntc_crit: soc_dram_ntc_crit@0 {
1594 temperature = <100000>;
1595 hysteresis = <2000>;
1596 type = "critical";
1597 };
1598 };
1599 };
1600
1601 nrpa_ntc {
1602 polling-delay = <1000>; /* milliseconds */
1603 polling-delay-passive = <1000>; /* milliseconds */
1604 thermal-sensors = <&tboard_thermistor2>;
1605
1606 trips {
1607 nrpa_ntc_target: nrpa_ntc_trip@0 {
1608 temperature = <82000>;
1609 hysteresis = <2000>;
1610 type = "passive";
1611 };
1612 nrpa_ntc_no_ims: nrpa_ntc_trip@1 {
1613 temperature = <90000>;
1614 hysteresis = <2000>;
1615 type = "passive";
1616 };
1617 };
1618 cooling-maps {
1619 map0 {
1620 trip = <&nrpa_ntc_target>;
1621 cooling-device = <&mutt_pa2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1622 };
1623 map1 {
1624 trip = <&nrpa_ntc_no_ims>;
1625 cooling-device = <&mutt_pa2_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1626 };
1627 };
1628 };
1629
1630 ltepa_ntc {
1631 polling-delay = <1000>; /* milliseconds */
1632 polling-delay-passive = <1000>; /* milliseconds */
1633 thermal-sensors = <&tboard_thermistor3>;
1634
1635 trips {
1636 ltepa_ntc_target: ltepa_ntc_trip@0 {
1637 temperature = <82000>;
1638 hysteresis = <2000>;
1639 type = "passive";
1640 };
1641 ltepa_ntc_no_ims: ltepa_ntc_trip@1 {
1642 temperature = <90000>;
1643 hysteresis = <2000>;
1644 type = "passive";
1645 };
1646 ltepa_ntc_crit: ltepa_ntc_trip@2 {
1647 temperature = <100000>;
1648 hysteresis = <2000>;
1649 type = "critical";
1650 };
1651 };
1652 cooling-maps {
1653 map0 {
1654 trip = <&ltepa_ntc_target>;
1655 cooling-device = <&mutt_pa1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1656 };
1657 map1 {
1658 trip = <&ltepa_ntc_no_ims>;
1659 cooling-device = <&mutt_pa1_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1660 };
1661 };
1662 };
1663
1664 rf_ntc {
1665 polling-delay = <1000>; /* milliseconds */
1666 polling-delay-passive = <1000>; /* milliseconds */
1667 thermal-sensors = <&tboard_thermistor4>;
1668
1669 trips {
1670 rf_ntc_crit: rf_ntc_crit@0 {
1671 temperature = <100000>;
1672 hysteresis = <2000>;
1673 type = "critical";
1674 };
1675 };
1676 };
1677
1678 pmic {
1679 polling-delay = <1000>; /* milliseconds */
1680 polling-delay-passive = <1000>; /* milliseconds */
1681 thermal-sensors = <&pmic_temp>;
1682
1683 trips {
1684 pmic_temp_crit: pmic_temp_crit@0 {
1685 temperature = <125000>;
1686 hysteresis = <2000>;
1687 type = "critical";
1688 };
1689 };
1690 };
1691 pmic_vcore {
1692 polling-delay = <0>; /* milliseconds */
1693 polling-delay-passive = <0>; /* milliseconds */
1694 thermal-sensors = <&pmic_vcore>;
1695 };
1696 pmic_vproc {
1697 polling-delay = <0>; /* milliseconds */
1698 polling-delay-passive = <0>; /* milliseconds */
1699 thermal-sensors = <&pmic_vproc>;
1700 };
1701 pmic_vgpu {
1702 polling-delay = <0>; /* milliseconds */
1703 polling-delay-passive = <0>; /* milliseconds */
1704 thermal-sensors = <&pmic_vgpu>;
1705 };
1706
1707 md_rf {
1708 polling-delay = <1000>; /* milliseconds */
1709 polling-delay-passive = <1000>; /* milliseconds */
1710 thermal-sensors = <&md_rf_ic>;
1711
1712 trips {
1713 md_rf_crit: md_rf_crit@0 {
1714 temperature = <117000>;
1715 hysteresis = <2000>;
1716 type = "critical";
1717 };
1718 };
1719 };
1720 conn_gps {
1721 polling-delay = <1000>; /* milliseconds */
1722 polling-delay-passive = <1000>; /* milliseconds */
1723 thermal-sensors = <&consys>;
1724
1725 trips {
1726 consys_max_crit: consys_max_crit@0 {
1727 temperature = <117000>;
1728 hysteresis = <2000>;
1729 type = "critical";
1730 };
1731 };
1732 };
1733 };
1734
1735 chipid@08000000 {
1736 compatible = "mediatek,chipid";
1737 reg = <0 0x08000000 0 0x0004>,
1738 <0 0x08000004 0 0x0004>,
1739 <0 0x08000008 0 0x0004>,
1740 <0 0x0800000c 0 0x0004>;
1741 };
1742
1743 dbgtop@1000d000 {
1744 compatible = "mediatek,dbgtop";
1745 reg = <0 0x1000d000 0 0x1000>;
1746 };
1747
1748 mcupm@0C540000 {
1749 compatible = "mediatek,mcupm";
1750 reg =<0 0x0C540000 0 0x22000>,
1751
1752 <0 0x0c55fb00 0 0xa0>,
1753 <0 0x0c562004 0 0x4>,
1754 <0 0x0c562018 0 0x4>,
1755 <0 0x0c562000 0 0x4>,
1756 <0 0x0c562010 0 0x4>,
1757
1758 <0 0x0c55fba0 0 0xa0>,
1759 <0 0x0c562004 0 0x4>,
1760 <0 0x0c562018 0 0x4>,
1761 <0 0x0c562000 0 0x4>,
1762 <0 0x0c562010 0 0x4>,
1763
1764 <0 0x0c55fc40 0 0xa0>,
1765 <0 0x0c562004 0 0x4>,
1766 <0 0x0c562018 0 0x4>,
1767 <0 0x0c562000 0 0x4>,
1768 <0 0x0c562010 0 0x4>,
1769
1770 <0 0x0c55fce0 0 0xa0>,
1771 <0 0x0c562004 0 0x4>,
1772 <0 0x0c562018 0 0x4>,
1773 <0 0x0c562000 0 0x4>,
1774 <0 0x0c562010 0 0x4>,
1775
1776 <0 0x0c55fd80 0 0xa0>,
1777 <0 0x0c562004 0 0x4>,
1778 <0 0x0c562018 0 0x4>,
1779 <0 0x0c562000 0 0x4>,
1780 <0 0x0c562010 0 0x4>,
1781
1782 <0 0x0c55fe20 0 0xa0>,
1783 <0 0x0c562004 0 0x4>,
1784 <0 0x0c562018 0 0x4>,
1785 <0 0x0c562000 0 0x4>,
1786 <0 0x0c562010 0 0x4>,
1787
1788 <0 0x0c55fec0 0 0xa0>,
1789 <0 0x0c562004 0 0x4>,
1790 <0 0x0c562018 0 0x4>,
1791 <0 0x0c562000 0 0x4>,
1792 <0 0x0c562010 0 0x4>,
1793
1794 <0 0x0c55ff60 0 0xa0>,
1795 <0 0x0c562004 0 0x4>,
1796 <0 0x0c562018 0 0x4>,
1797 <0 0x0c562000 0 0x4>,
1798 <0 0x0c562010 0 0x4>;
1799
1800 reg-names = "mcupm_base",
1801
1802 "mbox0_base",
1803 "mbox0_set",
1804 "mbox0_clr",
1805 "mbox0_send",
1806 "mbox0_recv",
1807
1808 "mbox1_base",
1809 "mbox1_set",
1810 "mbox1_clr",
1811 "mbox1_send",
1812 "mbox1_recv",
1813
1814 "mbox2_base",
1815 "mbox2_set",
1816 "mbox2_clr",
1817 "mbox2_send",
1818 "mbox2_recv",
1819
1820 "mbox3_base",
1821 "mbox3_set",
1822 "mbox3_clr",
1823 "mbox3_send",
1824 "mbox3_recv",
1825
1826 "mbox4_base",
1827 "mbox4_set",
1828 "mbox4_clr",
1829 "mbox4_send",
1830 "mbox4_recv",
1831
1832 "mbox5_base",
1833 "mbox5_set",
1834 "mbox5_clr",
1835 "mbox5_send",
1836 "mbox5_recv",
1837
1838 "mbox6_base",
1839 "mbox6_set",
1840 "mbox6_clr",
1841 "mbox6_send",
1842 "mbox6_recv",
1843
1844 "mbox7_base",
1845 "mbox7_set",
1846 "mbox7_clr",
1847 "mbox7_send",
1848 "mbox7_recv";
1849
1850 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1858
1859 interrupt-names = "mbox0",
1860 "mbox1",
1861 "mbox2",
1862 "mbox3",
1863 "mbox4",
1864 "mbox5",
1865 "mbox6",
1866 "mbox7";
1867 };
1868
1869 topckgen: topckgen@10000000 {
1870 compatible = "mediatek,topckgen", "syscon";
1871 reg = <0 0x10000000 0 0x1000>;
1872 };
1873
1874 dcm: dcm@10001000 {
1875 compatible = "mediatek,mt6880-dcm";
1876 reg = <0 0x10001000 0 0x1000>,
1877 <0 0x10002000 0 0x1000>,
1878 <0 0x10022000 0 0x1000>,
1879 <0 0x10219000 0 0x1000>,
1880 <0 0x10230000 0 0x2000>,
1881 <0 0x10235000 0 0x1000>,
1882 <0 0x10238000 0 0x1000>,
1883 <0 0x10240000 0 0x2000>,
1884 <0 0x10248000 0 0x1000>,
1885 <0 0xc538000 0 0x5000>,
1886 <0 0xc53a800 0 0x1000>;
1887 reg-names = "infracfg_ao",
1888 "infracfg_ao_mem",
1889 "infra_ao_bcrm",
1890 "emi",
1891 "dramc_ch0_top0",
1892 "chn0_emi",
1893 "dramc_ch0_top5",
1894 "dramc_ch1_top0",
1895 "dramc_ch1_top5",
1896 "mp_cpusys_top",
1897 "cpccfg_reg";
1898 };
1899
1900 infracfg_ao: infracfg_ao@10001000 {
1901 compatible = "mediatek,infracfg_ao", "syscon", "simple-mfd";
1902 reg = <0 0x10001000 0 0x1000>;
1903 infracfg_rst: reset-controller {
1904 compatible = "ti,syscon-reset";
1905 #reset-cells = <1>;
1906
1907 ti,reset-bits = <
1908 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
1909 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
1910 >;
1911 };
1912 };
1913
1914 infracfg_ao_mem@10002000 {
1915 compatible = "mediatek,infracfg_ao_mem";
1916 reg = <0 0x10002000 0 0x1000>;
1917 };
1918
1919 pericfg@10003000 {
1920 compatible = "mediatek,pericfg";
1921 reg = <0 0x10003000 0 0x1000>;
1922 };
1923
1924 gpio_usage_mapping: gpio_usage_mapping {
1925 compatible = "mediatek,gpio_usage_mapping";
1926 };
1927
1928 gpio: gpio@10005000 {
1929 compatible = "mediatek,gpio";
1930 reg = <0 0x10005000 0 0x1000>;
1931 };
1932
1933 pio: pinctrl@10005000 {
1934 compatible = "mediatek,mt2735-pinctrl";
1935 reg = <0 0x10005000 0 0x1000>,
1936 <0 0x11c10000 0 0x1000>,
1937 <0 0x11c20000 0 0x1000>,
1938 <0 0x11d00000 0 0x1000>,
1939 <0 0x11d10000 0 0x1000>,
1940 <0 0x11d20000 0 0x1000>,
1941 <0 0x11e00000 0 0x1000>,
1942 <0 0x11f00000 0 0x1000>,
1943 <0 0x1000b000 0 0x1000>;
1944 reg-names = "gpio", "iocfg_rm",
1945 "iocfg_rb", "iocfg_bl",
1946 "iocfg_bm", "iocfg_br",
1947 "iocfg_lt", "iocfg_tl",
1948 "eint";
1949 gpio-controller;
1950 #gpio-cells = <2>;
1951 gpio-ranges = <&pio 0 0 235>;
1952 interrupt-controller;
1953 #interrupt-cells = <2>;
1954 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1955 interrupt-parent = <&gic>;
1956 };
1957
1958 sleep: sleep@10006000 {
1959 compatible = "mediatek,sleep", "syscon";
1960 reg = <0 0x10006000 0 0x1000>;
1961 };
1962
1963 spmtwam: spmtwam@10006000 {
1964 compatible = "mediatek,spmtwam";
1965 reg = <0 0x10006000 0 0x1000>;
1966 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1967 spm_twam_con = <0xa0>;
1968 spm_twam_window_len = <0xa4>;
1969 spm_twam_idle_sel = <0xa8>;
1970 spm_irq_mask = <0xb4>;
1971 spm_irq_sta = <0x128>;
1972 spm_twam_last_sta0 = <0x1d0>;
1973 spm_twam_last_sta1 = <0x1d4>;
1974 spm_twam_last_sta2 = <0x1d8>;
1975 spm_twam_last_sta3 = <0x1dc>;
1976 };
1977
1978 srclken: srclken@10006500 {
1979 compatible = "mediatek,srclken";
1980 reg = <0 0x10006500 0 0x1000>,
1981 <0 0x105c4000 0 0x1000>,
1982 <0 0x10005000 0 0x1000>;
1983 reg-names = "srclken", "scpdvfs", "gpio";
1984 srclken-mode = "bringup";
1985
1986 srclken-rst-cfg = <0x0>;
1987 srclken-central-cfg = <0x4 0x8 0x1C>;
1988 srclken-cmd-cfg = <0xC>;
1989 srclken-pmic-cfg = <0x10 0x14>;
1990 srclken-dcxo-fpm-cfg = <0x18>;
1991 srclken-subsys-cfg = <0x20>;
1992 srclken-misc-cfg = <0xB4>;
1993 srclken-spm-cfg = <0xB8>;
1994 srclken-subsys-if-cfg = <0xBC>;
1995 srclken-fsm-sta = <0x60>;
1996 srclken-cmd-sta = <0x64 0x68>;
1997 srclken-spi-sta = <0x6C>;
1998 srclken-pipo-sta = <0x70>;
1999 srclken-subsys-sta = <0x80>;
2000 srclken-dbg-trace-sta = <0xC0 0xC4>;
2001
2002 srclken-scp-enable = "n";
2003 scp-vreq-cfg = <0x54>;
2004 scp-rc-vreq-bit = <27 28>;
2005
2006 srclken-gpio-enable = "n";
2007 gpio-dir-cfg = <0x0>;
2008 gpio-dout-cfg = <0x100>;
2009 gpio-pull-bit = <6>;
2010 };
2011
2012 watchdog: watchdog@10007000 {
2013 compatible = "mediatek,mt2735-wdt";
2014 reg = <0 0x10007000 0 0x1000>;
2015 };
2016
2017 apxgpt@10008000 {
2018 compatible = "mediatek,apxgpt";
2019 reg = <0 0x10008000 0 0x1000>;
2020 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
2021 };
2022
2023 sej@1000a000 {
2024 compatible = "mediatek,sej";
2025 reg = <0 0x1000a000 0 0x1000>;
2026 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
2027 };
2028
2029 apmixed: apmixed@1000c000 {
2030 compatible = "mediatek,apmixed";
2031 reg = <0 0x1000c000 0 0xe00>;
2032 };
2033
2034 fhctl@1000ce00 {
2035 compatible = "mediatek,mt6880-fhctl";
2036 reg = <0 0x1000ce00 0 0x200>;
2037 mediatek,apmixed = <&apmixed>;
2038
2039 armpll_ll {
2040 mediatek,fh-id = <0>;
2041 mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_LL>;
2042 mediatek,fh-cpu-pll;
2043 };
2044
2045 mainpll {
2046 mediatek,fh-id = <1>;
2047 mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
2048 };
2049
2050 mpll {
2051 mediatek,fh-id = <2>;
2052 mediatek,fh-pll-id = <CLK_APMIXED_MPLL>;
2053 };
2054
2055 msdcpll {
2056 mediatek,fh-id = <4>;
2057 mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
2058 };
2059
2060 mfgpll {
2061 mediatek,fh-id = <5>;
2062 mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
2063 };
2064
2065 mmpll {
2066 mediatek,fh-id = <6>;
2067 mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
2068 };
2069 };
2070
2071 pwrap@1000d000 {
2072 compatible = "mediatek,pwrap";
2073 reg = <0 0x1000d000 0 0x1000>;
2074 };
2075
2076 keypad:kp@10010000 {
2077 compatible = "mediatek,kp";
2078 reg = <0 0x10010000 0 0x1000>;
2079 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
2080 clocks = <&clk26m>;
2081 clock-names = "kpd";
2082 };
2083
2084 gpio-keys {
2085 compatible = "gpio-keys";
2086
2087 button0 {
2088 label = "Modem RF";
2089 gpios = <&pio 6 GPIO_ACTIVE_LOW>;
2090 linux,code = <KEY_PHONE>;
2091 };
2092
2093 button1 {
2094 label = "GPS";
2095 gpios = <&pio 7 GPIO_ACTIVE_LOW>;
2096 linux,code = <246>;
2097 };
2098/*
2099 button2 {
2100 label = "Factory Mode";
2101 gpios = <&pio 112 GPIO_ACTIVE_LOW>;
2102 linux,code = <112>;
2103 };
2104
2105 button3 {
2106 label = "WIFI";
2107 gpios = <&pio 114 GPIO_ACTIVE_LOW>;
2108 linux,code = <114>;
2109 };
2110
2111 button4 {
2112 label = "WPS";
2113 gpios = <&pio 115 GPIO_ACTIVE_LOW>;
2114 linux,code = <115>;
2115 };
2116*/
2117 };
2118
2119 topmisc@10011000 {
2120 compatible = "mediatek,topmisc";
2121 reg = <0 0x10011000 0 0x1000>;
2122 };
2123
2124 dvfsrc: dvfsrc@10012000 {
2125 compatible = "mediatek,mt6890-dvfsrc";
2126 reg = <0 0x10012000 0 0x1000>,
2127 <0 0x10006000 0 0x1000>;
2128 reg-names = "dvfsrc", "spm";
2129 #interconnect-cells = <1>;
2130 dvfsrc_vcore: dvfsrc-vcore {
2131 regulator-name = "dvfsrc-vcore";
2132 regulator-min-microvolt = <550000>;
2133 regulator-max-microvolt = <750000>;
2134 regulator-always-on;
2135 };
2136
2137 dvfsrc_freq_opp6: opp6 {
2138 opp-peak-KBps = <0>;
2139 };
2140 dvfsrc_freq_opp5: opp5 {
2141 opp-peak-KBps = <2500000>;
2142 };
2143 dvfsrc_freq_opp4: opp4 {
2144 opp-peak-KBps = <3800000>;
2145 };
2146 dvfsrc_freq_opp3: opp3 {
2147 opp-peak-KBps = <5100000>;
2148 };
2149 dvfsrc_freq_opp2: opp2 {
2150 opp-peak-KBps = <5900000>;
2151 };
2152 dvfsrc_freq_opp1: opp1 {
2153 opp-peak-KBps = <7600000>;
2154 };
2155 dvfsrc_freq_opp0: opp0 {
2156 opp-peak-KBps = <10200000>;
2157 };
2158
2159 dvfsrc-helper {
2160 compatible = "mediatek,dvfsrc-helper";
2161 vcore-supply = <&mt6330_vcore_buck_reg>;
2162 rc-vcore-supply = <&dvfsrc_vcore>;
2163 interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>;
2164 interconnect-names = "icc-perf-bw";
2165 required-opps = <&dvfsrc_freq_opp0>,
2166 <&dvfsrc_freq_opp1>,
2167 <&dvfsrc_freq_opp2>,
2168 <&dvfsrc_freq_opp3>,
2169 <&dvfsrc_freq_opp4>,
2170 <&dvfsrc_freq_opp5>,
2171 <&dvfsrc_freq_opp6>;
2172 };
2173
2174 dvfsrc-met {
2175 compatible = "mediatek,dvfsrc-met";
2176 };
2177 };
2178
2179 mbist_ao@10013000 {
2180 compatible = "mediatek,mbist_ao";
2181 reg = <0 0x10013000 0 0x1000>;
2182 };
2183
2184 dpmaif_ao@10014000 {
2185 compatible = "mediatek,dpmaif_ao";
2186 reg = <0 0x10014000 0 0x1000>;
2187 };
2188
2189 aes_top0@10016000 {
2190 compatible = "mediatek,aes_top0";
2191 reg = <0 0x10016000 0 0x1000>;
2192 };
2193
2194 timer: timer {
2195 compatible = "arm,armv8-timer";
2196 interrupt-parent = <&gic>;
2197 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
2198 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
2199 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
2200 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
2201 clock-frequency = <13000000>;
2202 };
2203
2204 sys_timer@10017000 {
2205 compatible = "mediatek,sys_timer",
2206 "mediatek,mt6765-timer";
2207 reg = <0 0x10017000 0 0x1000>;
2208 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
2209 clocks = <&clk13m>;
2210 };
2211
2212 modem_temp_share@10018000 {
2213 compatible = "mediatek,modem_temp_share";
2214 reg = <0 0x10018000 0 0x1000>;
2215 };
2216
2217 security_ao@1001a000 {
2218 compatible = "mediatek,security_ao";
2219 reg = <0 0x1001a000 0 0x1000>;
2220 };
2221
2222 topckgen_ao@1001b000 {
2223 compatible = "mediatek,topckgen_ao";
2224 reg = <0 0x1001b000 0 0x1000>;
2225 };
2226
2227 devapc_ao_mm@1001c000 {
2228 compatible = "mediatek,devapc_ao_mm";
2229 reg = <0 0x1001c000 0 0x1000>;
2230 };
2231
2232 sleep_sram@1001e000 {
2233 compatible = "mediatek,sleep_sram";
2234 reg = <0 0x1001e000 0 0x4000>;
2235 };
2236
2237 bcrm_ao_peri@10022000 {
2238 compatible = "mediatek,bcrm_ao_peri";
2239 reg = <0 0x10022000 0 0x1000>;
2240 };
2241
2242 debug_ao_peri@10023000 {
2243 compatible = "mediatek,debug_ao_peri";
2244 reg = <0 0x10023000 0 0x1000>;
2245 };
2246
2247 mhccif: mhccif@10024000 {
2248 compatible = "mediatek,mt6880-mhccif";
2249 #interrupt-cells = <3>;
2250 interrupt-controller;
2251 reg = <0 0x10024000 0 0x1000>,
2252 <0 0x10025000 0 0x1000>;
2253 reg-names = "mhccif_rc", "mhccif_ep";
2254 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
2255 status = "disabled";
2256 };
2257
2258 spmi_bus: spmi@10026000 {
2259 compatible = "mediatek,mt6880-pmif-m", "syscon";
2260 reg = <0 0x10026000 0 0x0008F0>,
2261 <0 0x10029000 0 0x000110>;
2262 reg-names = "pmif", "spmimst";
2263 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
2264 <&pio 216 IRQ_TYPE_LEVEL_HIGH>;
2265 interrupt-names = "pmif_irq", "rcs_irq";
2266 interrupt-controller;
2267 #interrupt-cells = <1>;
2268 irq_event_en = <0x0 0x00180000 0x0 0x0 0x0>;
2269 clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
2270 <&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
2271 <&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
2272 <&topckgen_clk CLK_TOP_OSC_D10>,
2273 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2274 <&topckgen_clk CLK_TOP_SPMI_M_MST_SEL>,
2275 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2276 <&topckgen_clk CLK_TOP_OSC_D10>;
2277 clock-names = "pmif_sys_ck",
2278 "pmif_tmr_ck",
2279 "pmif_clk_mux",
2280 "pmif_clk_osc_d10",
2281 "pmif_clk26m",
2282 "spmimst_clk_mux",
2283 "spmimst_clk26m",
2284 "spmimst_clk_osc_d10";
2285 swinf_ch_start = <6>;
2286 ap_swinf_no = <2>;
2287 grpid = <0xB>;
2288 #address-cells = <2>;
2289 #size-cells = <0>;
2290 };
2291
2292 spmi_p_bus: spmi_p@10027000 {
2293 compatible = "mediatek,mt6880-pmif-p";
2294 reg = <0 0x10027000 0 0x0008F0>,
2295 <0 0x10028000 0 0x000110>;
2296 reg-names = "pmif", "spmimst";
2297 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2298 interrupt-names = "pmif_irq";
2299 irq_event_en = <0x0 0x0 0x0 0x0 0x0>;
2300 clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
2301 <&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
2302 <&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
2303 <&topckgen_clk CLK_TOP_OSC_D10>,
2304 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2305 <&topckgen_clk CLK_TOP_SPMI_P_MST_SEL>,
2306 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2307 <&topckgen_clk CLK_TOP_MAINPLL_D7_D8>;
2308 clock-names = "pmif_sys_ck",
2309 "pmif_tmr_ck",
2310 "pmif_clk_mux",
2311 "pmif_clk_osc_d10",
2312 "pmif_clk26m",
2313 "spmimst_clk_mux",
2314 "spmimst_clk26m",
2315 "spmimst_clk_mainpll_d7_d8";
2316 swinf_ch_start = <6>;
2317 ap_swinf_no = <2>;
2318 grpid = <0xB>;
2319 #address-cells = <2>;
2320 #size-cells = <0>;
2321 };
2322
2323 /* ATF logger */
2324 atf_logger {
2325 compatible = "mediatek,atf_logger";
2326 };
2327
2328 bcrm_peri_ao@1002a000 {
2329 compatible = "mediatek,bcrm_peri_ao";
2330 reg = <0 0x1002a000 0 0x1000>;
2331 };
2332
2333 debug_ao_peri@1002b000 {
2334 compatible = "mediatek,debug_ao_peri";
2335 reg = <0 0x1002b000 0 0x1000>;
2336 };
2337
2338 bcrm_peri_ao2@1002d000 {
2339 compatible = "mediatek,bcrm_peri_ao2";
2340 reg = <0 0x1002d000 0 0x1000>;
2341 };
2342
2343 debug_ao_peri2@1002e000 {
2344 compatible = "mediatek,debug_ao_peri2";
2345 reg = <0 0x1002e000 0 0x1000>;
2346 };
2347
2348 devapc_ao_infra@10030000 {
2349 compatible = "mediatek,devapc_ao_infra";
2350 reg = <0 0x10030000 0 0x4000>;
2351 };
2352
2353 devapc_ao_peri@10034000 {
2354 compatible = "mediatek,devapc_ao_peri";
2355 reg = <0 0x10034000 0 0x4000>;
2356 };
2357
2358 devapc_ao_peri2@10038000 {
2359 compatible = "mediatek,devapc_ao_peri2";
2360 reg = <0 0x10038000 0 0x4000>;
2361 };
2362
2363 devapc_ao_peri_par@1003c000 {
2364 compatible = "mediatek,devapc_ao_peri_par";
2365 reg = <0 0x1003c000 0 0x4000>;
2366 };
2367
2368 debug_ao_peri_par@10040000 {
2369 compatible = "mediatek,debug_ao_peri_par";
2370 reg = <0 0x10040000 0 0x1000>;
2371 };
2372
2373 bcrm_peri_par_ao@10041000 {
2374 compatible = "mediatek,bcrm_peri_par_ao";
2375 reg = <0 0x10041000 0 0x1000>;
2376 };
2377
2378 debug_ao_fmem@10042000 {
2379 compatible = "mediatek,debug_ao_fmem";
2380 reg = <0 0x10042000 0 0x1000>;
2381 };
2382
2383 bcrm_fmem_ao@10043000 {
2384 compatible = "mediatek,bcrm_fmem_ao";
2385 reg = <0 0x10043000 0 0x1000>;
2386 };
2387
2388 devapc_ao_fmem@10044000 {
2389 compatible = "mediatek,devapc_ao_fmem";
2390 reg = <0 0x10044000 0 0x4000>;
2391 };
2392
2393 pwm@10048000 {
2394 compatible = "mediatek,mt6880-pwm";
2395 reg = <0 0x10048000 0 0x1000>;
2396 #pwm-cells = <2>;
2397 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
2398
2399 clocks = <&topckgen_clk CLK_TOP_PWM_SEL>,
2400 <&infracfg_ao_clk CLK_IFRAO_PWM>,
2401 <&infracfg_ao_clk CLK_IFRAO_PWM1>,
2402 <&infracfg_ao_clk CLK_IFRAO_PWM2>,
2403 <&infracfg_ao_clk CLK_IFRAO_PWM3>,
2404 <&infracfg_ao_clk CLK_IFRAO_PWM4>,
2405 <&infracfg_ao_clk CLK_IFRAO_PWM5>,
2406 <&infracfg_ao_clk CLK_IFRAO_PWM6>,
2407 <&infracfg_ao_clk CLK_IFRAO_PWM7>;
2408 clock-names = "top",
2409 "main",
2410 "pwm1",
2411 "pwm2",
2412 "pwm3",
2413 "pwm4",
2414 "pwm5",
2415 "pwm6",
2416 "pwm7";
2417 };
2418
2419 sgmii0@10060000 {
2420 compatible = "mediatek,sgmii0";
2421 reg = <0 0x10060000 0 0x8000>;
2422 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
2423 };
2424
2425 sgmii1@10070000 {
2426 compatible = "mediatek,sgmii1";
2427 reg = <0 0x10070000 0 0x8000>;
2428 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
2429 };
2430
2431 sys_cirq@10204000 {
2432 compatible = "mediatek,sys_cirq";
2433 reg = <0 0x10204000 0 0x1000>;
2434 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
2435 };
2436
2437 devapc@10207000 {
2438 compatible = "mediatek,mt6880-devapc";
2439 reg = <0 0x10207000 0 0x1000>,
2440 <0 0x10274000 0 0x1000>,
2441 <0 0x10275000 0 0x1000>,
2442 <0 0x11020000 0 0x1000>,
2443 <0 0x10030000 0 0x1000>,
2444 <0 0x1020e000 0 0x1000>,
2445 <0 0x10033000 0 0x1000>;
2446 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2447 clocks = <&infracfg_ao_clk CLK_IFRAO_DEVICE_APC>;
2448 clock-names = "devapc-infra-clock";
2449 };
2450
2451 hwrng: hwrng {
2452 compatible = "mediatek,mt67xx-rng";
2453 };
2454
2455 bus_dbg@10208000 {
2456 compatible = "mediatek,bus_dbg-v2";
2457 reg = <0 0x10208000 0 0x1000>,
2458 <0 0x10001000 0 0x1000>;
2459 mediatek,bus_dbg_con_offset = <0x2fc>;
2460 interrupt = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
2461 };
2462
2463 ap_ccif0@10209000 {
2464 compatible = "mediatek,ap_ccif0";
2465 reg = <0 0x10209000 0 0x1000>;
2466 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
2467 };
2468
2469 md_ccif0@1020a000 {
2470 compatible = "mediatek,md_ccif0";
2471 reg = <0 0x1020a000 0 0x1000>;
2472 };
2473
2474 ap_ccif1@1020b000 {
2475 compatible = "mediatek,ap_ccif1";
2476 reg = <0 0x1020b000 0 0x1000>;
2477 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
2478 };
2479
2480 md_ccif1@1020c000 {
2481 compatible = "mediatek,md_ccif1";
2482 reg = <0 0x1020c000 0 0x1000>;
2483 };
2484
2485 infra_mbist@1020d000 {
2486 compatible = "mediatek,infra_mbist";
2487 reg = <0 0x1020d000 0 0x1000>;
2488 };
2489
2490 infracfg@1020e000 {
2491 compatible = "mediatek,infracfg";
2492 reg = <0 0x1020e000 0 0x1000>;
2493 };
2494
2495 trng@1020f000 {
2496 compatible = "mediatek,trng";
2497 reg = <0 0x1020f000 0 0x1000>;
2498 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
2499 };
2500
2501 dxcc_sec@10210000 {
2502 compatible = "mediatek,dxcc_sec";
2503 reg = <0 0x10210000 0 0x1000>;
2504 };
2505
2506 cq_dma@10212000 {
2507 compatible = "mediatek,cq_dma";
2508 reg = <0 0x10212000 0 0x1000>;
2509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2510 };
2511
2512 md2md_md2_ccif0@10213000 {
2513 compatible = "mediatek,md2md_md2_ccif0";
2514 reg = <0 0x10213000 0 0x1000>;
2515 };
2516
2517 sramrom@10214000 {
2518 compatible = "mediatek,sramrom";
2519 reg = <0 0x10214000 0 0x1000>;
2520 };
2521
2522 bcrm_infra@10215000 {
2523 compatible = "mediatek,bcrm_infra";
2524 reg = <0 0x10215000 0 0x1000>;
2525 };
2526
2527 dbg_tracker2@10218000 {
2528 compatible = "mediatek,dbg_tracker2";
2529 reg = <0 0x10218000 0 0x1000>;
2530 };
2531
2532 emicen: emicen@10219000 {
2533 compatible = "mediatek,mt6880-emicen",
2534 "mediatek,common-emicen";
2535 reg = <0 0x10219000 0 0x1000>;
2536 mediatek,emi-reg = <&emichn>;
2537 };
2538
2539 infra_device_mpu@1021a000 {
2540 compatible = "mediatek,infra_device_mpu";
2541 reg = <0 0x1021a000 0 0x1000>;
2542 };
2543
2544 infra_device_mpu@1021b000 {
2545 compatible = "mediatek,infra_device_mpu";
2546 reg = <0 0x1021b000 0 0x1000>;
2547 };
2548
2549 infracfg_mem@1021c000 {
2550 compatible = "mediatek,infracfg_mem";
2551 reg = <0 0x1021c000 0 0x1000>;
2552 };
2553
2554 emimpu:emimpu@10226000 {
2555 compatible = "mediatek,mt6880-emimpu",
2556 "mediatek,common-emimpu";
2557 reg = <0 0x10226000 0 0x1000>;
2558 mediatek,emi-reg = <&emicen>;
2559 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2560 region_cnt = <32>;
2561 domain_cnt = <16>;
2562 addr_align = <16>;
2563 ap_region = <31>;
2564 ap_apc = <0 0 5 5 0 0 6 0>,
2565 <0 0 5 5 5 5 5 5>;
2566 dump = <0x1f0 0x1f8 0x1fc>;
2567 clear = <0x160 0xffffffff 16>,
2568 <0x200 0x00000003 16>,
2569 <0x1f0 0x80000000 1>;
2570 clear_md = <0x1fc 0x80000000 1>;
2571 ctrl_intf = <1>;
2572 slverr = <0>;
2573 };
2574
2575 cldma_sys_ap {
2576 compatible = "mediatek,cldma_sys_ap";
2577 reg = <0 0x1004A000 0 0x1000>, /*CLDMA0_AO_INDMA_AO_MD*/
2578 <0 0x1021E000 0 0x1000>; /*CLDMA0_AO_INDMA_PD_MD*/
2579 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; /*cldma0_md_int_ap*/
2580 clocks = <&infracfg_ao_clk CLK_IFRAO_RG_133M_CLDMA_TOP>;
2581 clock-names = "infra-cldma0-rh";
2582 mediatek,hif_ids = <1>; /* (1 << HIF_ID_CLDMA) */
2583 };
2584
2585 mrdump_ext_rst: mrdump_ext_rst {
2586 compatible = "mediatek, mrdump_ext_rst-disabled";
2587 mode = "IRQ";
2588 status = "okay";
2589 };
2590
2591 dpmaif:dpmaif@10014000 {
2592 compatible = "mediatek,dpmaif";
2593 reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
2594 <0 0x1022D000 0 0x1000>, /*PD_UL*/
2595 <0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
2596 <0 0x1022E000 0 0x1000>, /*SRAM*/
2597 <0 0x15B14000 0 0x1000>, /*MED_BMP_CFG*/
2598 <0 0x15B38000 0 0x1000>; /*MED_SSR1_CFG*/
2599 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; /*209+32=241*/
2600 mediatek,dpmaif_capability = <6>;
2601 clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
2602 <&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>;
2603 clock-names = "infra-dpmaif-clk",
2604 "infra-dpmaif-blk-clk";
2605 };
2606
2607 mddriver:mddriver {
2608 compatible = "mediatek,mddriver";
2609 mediatek,mdhif_type = <2>; /* bit0~3: CLDMA|CCIF|DPMAIF */
2610 mediatek,md_id = <0>;
2611 mediatek,cldma_capability = <2>;
2612 reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
2613 <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
2614 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 174/206*/
2615 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 175/207*/
2616 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; /*MDWDT*/
2617 clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
2618 <&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
2619 <&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
2620 <&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
2621 <&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
2622 <&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>,
2623 <&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>;
2624 clock-names = "infra-ccif-ap",
2625 "infra-ccif-md",
2626 "infra-ccif1-ap",
2627 "infra-ccif1-md",
2628 "infra-ccif2-ap",
2629 "infra-ccif2-md",
2630 "infra-ccif4-md";
2631 power-domains = <&scpsys MT6890_POWER_DOMAIN_MD1>;
2632 };
2633
2634/* md_auxadc:md_auxadc {
2635 compatible = "mediatek,md_auxadc";
2636 io-channels = <&auxadc 2>;
2637 io-channel-names = "md-channel",
2638 "md-battery";
2639 };
2640
2641 md_ccci_rtc:md_ccci_rtc {
2642 compatible = "mediatek,md_ccci_rtc";
2643 nvmem-cells = <&ext_32k>;
2644 nvmem-cell-names = "external-32k";
2645 }; */
2646
2647 gce_mbox: gce_mbox@10228000 {
2648 compatible = "mediatek,mailbox-gce";
2649 reg = <0 0x10228000 0 0x4000>;
2650 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
2651
2652 #mbox-cells = <3>;
2653 #gce-event-cells = <1>;
2654 #gce-subsys-cells = <2>;
2655 default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
2656 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
2657 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
2658 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
2659 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
2660 /bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
2661 /bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
2662 clocks = <&infracfg_ao_clk CLK_IFRAO_GCE>,
2663 <&infracfg_ao_clk CLK_IFRAO_GCE_26M_SET>;
2664 clock-names = "gce", "gce-timer";
2665 };
2666
2667 cmdq-test {
2668 compatible = "mediatek,cmdq-test";
2669 mediatek,gce = <&gce_mbox>;
2670 mmsys_config = <&mmsys_config>;
2671 mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
2672 mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>,
2673 <&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
2674 <&gce_mbox 11 0 CMDQ_THR_PRIO_1>;
2675 token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
2676 token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
2677 };
2678
2679 infra_dpmaif@1022c000 {
2680 compatible = "mediatek,infra_dpmaif";
2681 reg = <0 0x1022c000 0 0x10>;
2682 };
2683
2684 dramc: dramc@10230000 {
2685 compatible = "mediatek,mt6880-dramc",
2686 "mediatek,common-dramc";
2687 reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
2688 <0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
2689 <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
2690 <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
2691 <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
2692 <0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
2693 <0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
2694 <0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
2695 <0 0x10006000 0 0x1000>; /* SLEEP BASE */
2696 mr4_version = <1>;
2697 mr4_rg = <0x0090 0x0000ffff 0>;
2698 fmeter_version = <1>;
2699 crystal_freq = <52>;
2700 pll_id = <0x050c 0x00000100 8>;
2701 shu_lv = <0x050c 0x00030000 16>;
2702 shu_of = <0x700>;
2703 sdmpcw = <0x0704 0xffff0000 16>,
2704 <0x0724 0xffff0000 16>;
2705 prediv = <0x0708 0x000c0000 18>,
2706 <0x0728 0x000c0000 18>;
2707 posdiv = <0x0708 0x00000007 0>,
2708 <0x0728 0x00000007 0>;
2709 ckdiv4 = <0x0874 0x00000004 2>,
2710 <0x0874 0x00000004 2>;
2711 pll_md = <0x0744 0x00000100 8>,
2712 <0x0744 0x00000100 8>;
2713 cldiv2 = <0x08b4 0x00000002 1>,
2714 <0x08b4 0x00000002 1>;
2715 fbksel = <0x070c 0x00000040 6>,
2716 <0x070c 0x00000040 6>;
2717 dqopen = <0x0870 0x00100000 20>,
2718 <0x0870 0x00100000 20>;
2719 };
2720 emiisu: emiisu {
2721 compatible = "mediatek,mt6880-emiisu",
2722 "mediatek,common-emiisu";
2723 ctrl_intf = <1>;
2724 };
2725 emichn: emichn@10235000 {
2726 compatible = "mediatek,mt6880-emichn",
2727 "mediatek,common-emichn";
2728 reg = <0 0x10235000 0 0x1000>,
2729 <0 0x10245000 0 0x1000>;
2730 };
2731
2732 dramc_ch0_top0@10230000 {
2733 compatible = "mediatek,dramc_ch0_top0";
2734 reg = <0 0x10230000 0 0x2000>;
2735 };
2736
2737 dramc_ch0_top1@10232000 {
2738 compatible = "mediatek,dramc_ch0_top1";
2739 reg = <0 0x10232000 0 0x2000>;
2740 };
2741
2742 dramc_ch0_top2@10234000 {
2743 compatible = "mediatek,dramc_ch0_top2";
2744 reg = <0 0x10234000 0 0x1000>;
2745 };
2746
2747 dramc_ch0_top3@10235000 {
2748 compatible = "mediatek,dramc_ch0_top3";
2749 reg = <0 0x10235000 0 0x1000>;
2750 };
2751
2752 dramc_ch0_top4@10236000 {
2753 compatible = "mediatek,dramc_ch0_top4";
2754 reg = <0 0x10236000 0 0x2000>;
2755 };
2756
2757 dramc_ch0_top5@10238000 {
2758 compatible = "mediatek,dramc_ch0_top5";
2759 reg = <0 0x10238000 0 0x2000>;
2760 };
2761
2762 dramc_ch0_top6@1023a000 {
2763 compatible = "mediatek,dramc_ch0_top6";
2764 reg = <0 0x1023a000 0 0x2000>;
2765 };
2766
2767 ap_ccif2@1023c000 {
2768 compatible = "mediatek,ap_ccif2";
2769 reg = <0 0x1023c000 0 0x1000>;
2770 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2771 };
2772
2773 md_ccif2@1023d000 {
2774 compatible = "mediatek,md_ccif2";
2775 reg = <0 0x1023d000 0 0x1000>;
2776 };
2777
2778 ap_ccif3@1023e000 {
2779 compatible = "mediatek,ap_ccif3";
2780 reg = <0 0x1023e000 0 0x1000>;
2781 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2782 };
2783
2784 md_ccif3@1023f000 {
2785 compatible = "mediatek,md_ccif3";
2786 reg = <0 0x1023f000 0 0x1000>;
2787 };
2788
2789 i2c_common: i2c_common {
2790 compatible = "mediatek,i2c_common";
2791 dma_support = /bits/ 8 <3>;
2792 idvfs = /bits/ 8 <1>;
2793 set_dt_div = /bits/ 8 <1>;
2794 check_max_freq = /bits/ 8 <1>;
2795 ver = /bits/ 8 <2>;
2796 set_ltiming = /bits/ 8 <1>;
2797 ext_time_config = /bits/ 16 <0x1801>;
2798 cnt_constraint = /bits/ 8 <1>;
2799 dma_ver = /bits/ 8 <1>;
2800 };
2801
2802 i2c0: i2c0@11c40000 {
2803 compatible = "mediatek,i2c";
2804 id = <0>;
2805 reg = <0 0x11c40000 0 0x1000>,
2806 <0 0x10217080 0 0x80>;
2807 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2808 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C0_RO>,
2809 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2810 clock-names = "main", "dma";
2811 clock-div = <5>;
2812 aed = <0x1a>;
2813 };
2814
2815 i2c1: i2c1@11c41000 {
2816 compatible = "mediatek,i2c";
2817 id = <1>;
2818 reg = <0 0x11c41000 0 0x1000>,
2819 <0 0x10217100 0 0x80>;
2820 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2821 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C1_RO>,
2822 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2823 clock-names = "main", "dma";
2824 clock-div = <5>;
2825 aed = <0x1a>;
2826 };
2827
2828 i2c2: i2c2@11c42000 {
2829 compatible = "mediatek,i2c";
2830 id = <2>;
2831 reg = <0 0x11c42000 0 0x1000>,
2832 <0 0x10217180 0 0x80>;
2833 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2834 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C2_RO>,
2835 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2836 clock-names = "main", "dma";
2837 clock-div = <5>;
2838 aed = <0x1a>;
2839 };
2840
2841 i2c3: i2c3@11c43000 {
2842 compatible = "mediatek,i2c";
2843 id = <3>;
2844 reg = <0 0x11c43000 0 0x1000>,
2845 <0 0x10217200 0 0x80>;
2846 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2847 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C3_RO>,
2848 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2849 clock-names = "main", "dma";
2850 clock-div = <5>;
2851 aed = <0x1a>;
2852 };
2853
2854 i2c4: i2c4@11c44000 {
2855 compatible = "mediatek,i2c";
2856 id = <4>;
2857 reg = <0 0x11c44000 0 0x1000>,
2858 <0 0x10217280 0 0x80>;
2859 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2860 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C4_RO>,
2861 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2862 clock-names = "main", "dma";
2863 clock-div = <5>;
2864 aed = <0x1a>;
2865 };
2866
2867 i2c5: i2c5@11c45000 {
2868 compatible = "mediatek,i2c";
2869 id = <5>;
2870 reg = <0 0x11c45000 0 0x1000>,
2871 <0 0x10217300 0 0x80>;
2872 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
2873 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C5_RO>,
2874 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2875 clock-names = "main", "dma";
2876 clock-div = <5>;
2877 aed = <0x1a>;
2878 };
2879
2880 ssusb: usb@11201000 {
2881 compatible = "mediatek,mtu3";
2882 reg = <0 0x11201000 0 0x2e00>,
2883 <0 0x11203e00 0 0x0100>;
2884 reg-names = "mac", "ippc";
2885 vusb33-supply = <&mt6330_vusb_ldo_reg>;
2886 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2887
2888 phy-cells = <1>;
2889 phys = <&u2port0 PHY_TYPE_USB2>,
2890 <&u3port0 PHY_TYPE_USB3>;
2891 plat_type = <1>; /* 0: FPGA 1: ASIC */
2892 dr_mode = "peripheral";
2893 maximum-speed = "super-speed";
2894 clocks = <&infracfg_ao_clk CLK_IFRAO_SSUSB>,
2895 <&infracfg_ao_clk CLK_IFRAO_SSUSB_XHCI>;
2896 clock-names = "sys_ck","ref_ck";
2897 power-domains = <&scpsys MT6890_POWER_DOMAIN_SSUSB>;
2898 usb-role-switch;
2899 mediatek,force-vbus;
2900 mediatek,usb3-drd;
2901
2902 #address-cells = <2>;
2903 #size-cells = <2>;
2904 ranges;
2905
2906 usb_host: xhci0@11200000 {
2907 compatible = "mediatek,mtk-xhci";
2908 reg = <0 0x11200000 0 0x1000>;
2909 reg-names = "mac";
2910 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2911 clocks = <&clk26m>;
2912 clock-names = "sys_ck";
2913 };
2914 };
2915
2916 u3fpgaphy: usb-phy {
2917 compatible = "mediatek,fpga-u3phy";
2918 mediatek,ippc = <0x11203e00>;
2919 #address-cells = <2>;
2920 #size-cells = <2>;
2921 fpga_i2c_physical_base = <0x11c42000>;
2922 status = "disabled";
2923
2924 u3fpgaport0: usb-phy@0 {
2925 chip-id= <0xa60931a>;
2926 port = <0>;
2927 pclk_phase = <23>;
2928 #phy-cells = <1>;
2929 };
2930 };
2931
2932 u3phy: usb-phy@11e30000 {
2933 compatible = "mediatek,generic-tphy-v2";
2934 clocks = <&clk26m>;
2935 clock-names = "u3phya_ref";
2936 #address-cells = <2>;
2937 #size-cells = <2>;
2938 ranges;
2939
2940 u2port0: usb2-phy0@11e30000 {
2941 reg = <0 0x11e30000 0 0x700>;
2942 #phy-cells = <1>;
2943 mediatek,eye-rev6 = <1>;
2944 mediatek,eye-vrt = <5>;
2945 mediatek,eye-term = <5>;
2946 mediatek,rx-sqth = <5>;
2947 status = "okay";
2948 };
2949
2950 u3port0: usb3-phy0@11e30700 {
2951 reg = <0 0x11e30700 0 0x900>;
2952 #phy-cells = <1>;
2953 status = "okay";
2954 };
2955 };
2956
2957 apdma: dma-controller@0x10217000 {
2958 compatible = "mediatek, mt6873-uart-dma",
2959 "mediatek,mt6577-uart-dma";
2960 reg = <0 0x10217380 0 0x80>,
2961 <0 0x10217400 0 0x80>,
2962 <0 0x10217480 0 0x80>,
2963 <0 0x10217500 0 0x80>,
2964 <0 0x10217580 0 0x80>,
2965 <0 0x10217600 0 0x80>;
2966 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2967 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2968 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2969 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2970 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2971 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2972 dma-requests = <6>;
2973 dma-bits = <34>;
2974 clocks = <&clk26m>;
2975 #dma-cells = <1>;
2976 };
2977
2978 auxadc: auxadc@11001000 {
2979 compatible = "mediatek,mt6765-auxadc";
2980 reg = <0 0x11001000 0 0x1000>;
2981 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
2982 clocks = <&infracfg_ao_clk CLK_IFRAO_AUXADC>;
2983 clock-names = "main";
2984 #io-channel-cells = <1>;
2985 /* Auxadc efuse calibration */
2986 /* 1. Auxadc cali on/off bit shift */
2987 mediatek,cali-en-bit = <20>;
2988 /* 2. Auxadc cali ge bits shift */
2989 mediatek,cali-ge-bit = <10>;
2990 /* 3. Auxadc cali oe bits shift */
2991 mediatek,cali-oe-bit = <0>;
2992 /* 4. Auxadc cali efuse reg offset */
2993 mediatek,cali-efuse-reg-offset = <0xf8>;
2994 nvmem = <&efuse>;
2995 nvmem-names = "mtk_efuse";
2996 #interconnect-cells = <1>;
2997 };
2998
2999 uart0: serial@11002000 {
3000 compatible = "mediatek,mt6873-uart",
3001 "mediatek,mt6577-uart";
3002 reg = <0 0x11002000 0 0x1000>;
3003 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
3004 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART0>;
3005 clock-names = "baud", "bus";
3006 dmas = <&apdma 0
3007 &apdma 1>;
3008 dma-names = "tx", "rx";
3009 };
3010
3011 uart1: serial@11003000 {
3012 compatible = "mediatek,mt6873-uart",
3013 "mediatek,mt6577-uart";
3014 reg = <0 0x11003000 0 0x1000>;
3015 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
3016 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART1>;
3017 clock-names = "baud", "bus";
3018 dmas = <&apdma 2
3019 &apdma 3>;
3020 dma-names = "tx", "rx";
3021 };
3022
3023 uart2: serial@11004000 {
3024 compatible = "mediatek,mt6873-uart",
3025 "mediatek,mt6577-uart";
3026 reg = <0 0x11004000 0 0x1000>;
3027 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
3028 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART2>;
3029 clock-names = "baud", "bus";
3030 dmas = <&apdma 4
3031 &apdma 5>;
3032 dma-names = "tx", "rx";
3033 };
3034
3035 nandc: nfi@11005000 {
3036 compatible = "mediatek,mt6880-nfc";
3037 reg = <0 0x11005000 0 0x1000>,
3038 <0 0x11006000 0 0x1000>;
3039 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
3040 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
3041 status = "ok";
3042 };
3043
3044 nor: nor_flash@0x11250000 {
3045 compatible = "mediatek,mt8173-nor";
3046 reg = <0 0x11250000 0 0x1000>;
3047 clocks =<&topckgen_clk CLK_TOP_SFLASH_SEL>,
3048 <&infracfg_ao_clk CLK_IFRAO_RG_FLASHIF_SFLASH>;
3049 clock-names = "spi", "sf";
3050 #address-cells = <1>;
3051 #size-cells = <0>;
3052 status = "ok";
3053 };
3054
3055 pd-sgmii_0_phy {
3056 compatible = "mediatek,sgmii-bring-up";
3057 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
3058 };
3059
3060 pd-sgmii_0_top {
3061 compatible = "mediatek,sgmii-bring-up";
3062 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
3063 };
3064
3065 pd-sgmii_1_phy {
3066 compatible = "mediatek,sgmii-bring-up";
3067 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
3068 };
3069
3070 pd-sgmii_1_top {
3071 compatible = "mediatek,sgmii-bring-up";
3072 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
3073 };
3074
3075 sgmiisys_0: sgmiisys@10060000 {
3076 compatible = "mediatek,colgin-sgmiisys_0", "syscon";
3077 reg = <0 0x10060000 0 0x1000>;
3078 #clock-cells = <1>;
3079 mediatek,physpeed = "2500";
3080 /*modify by CLK SW Pei-hsuan Cheng */
3081 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
3082 };
3083
3084 sgmiisys_1: sgmiisys@10070000 {
3085 compatible = "mediatek,colgin-sgmiisys_1", "syscon";
3086 reg = <0 0x10070000 0 0x1000>;
3087 #clock-cells = <1>;
3088 mediatek,physpeed = "2500";
3089 /*modify by CLK SW Pei-hsuan Cheng */
3090 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
3091 };
3092
3093 sgmiisys_phy_0: sgmiiphy@11ED0000 {
3094 compatible = "mediatek,colgin-sgmiisys_phy_0", "syscon";
3095 reg = <0 0x11ED0000 0 0x1000>;
3096 #clock-cells = <1>;
3097 /*modify by CLK SW Pei-hsuan Cheng */
3098 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
3099 };
3100
3101 sgmiisys_phy_1: sgmiiphy@11EE0000 {
3102 compatible = "mediatek,colgin-sgmiisys_phy_1", "syscon";
3103 reg = <0 0x11EE0000 0 0x1000>;
3104 #clock-cells = <1>;
3105 /*modify by CLK SW Pei-hsuan Cheng */
3106 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
3107 };
3108
3109 ethsys: ethsys@15000000 {
3110 #address-cells = <1>;
3111 #size-cells = <1>;
3112 compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
3113 reg = <0 0x15000000 0 0x1000>;
3114 #clock-cells = <1>;
3115 #reset-cells = <1>;
3116
3117 ethsysrst: reset-controller {
3118 compatible = "ti,syscon-reset";
3119 #reset-cells = <1>;
3120 ti,reset-bits = <
3121 0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET) /* 4: wocpu_rst */
3122 >;
3123 };
3124 };
3125
3126 wo: wo@15195000 {
3127 compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
3128 reg = <0 0x15195000 0 0x1000>;
3129 };
3130
3131 eth: ethernet@15100000 {
3132 compatible = "mediatek,mt6890-eth",
3133 "syscon";
3134 reg = <0 0x15100000 0 0x20000>;
3135 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
3136 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
3137 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
3138 clocks = <&topckgen_clk CLK_TOP_NETSYS_SEL>,
3139 <&topckgen_clk CLK_TOP_MEDSYS_SEL>,
3140 <&topckgen_clk CLK_TOP_NETSYS_500M_SEL>,
3141 <&topckgen_clk CLK_TOP_NETSYS_MED_MCU_SEL>,
3142 <&topckgen_clk CLK_TOP_NETSYS_WED_MCU_SEL>,
3143 <&topckgen_clk CLK_TOP_NETSYS_2X_SEL>,
3144 <&topckgen_clk CLK_TOP_SGMII_SEL>,
3145 <&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
3146 clock-names = "net_sel", "med_sel", "net_500_sel",
3147 "med_mcu_sel", "wed_mcu_sel",
3148 "net_2x_sel", "sgmii_sel", "sgmii_sbus_sel";
3149 /*modify by CLK SW Pei-hsuan Cheng
3150 power-domains = <&scpsys MT6890_POWER_DOMAIN_NETSYS>;*/
3151 mediatek,ethsys = <&ethsys>;
3152 mediatek,wo = <&wo>;
3153 mediatek,sgmiisys = <&sgmiisys_0>,<&sgmiisys_1>;
3154 mediatek,sgmiisys_phy = <&sgmiisys_phy_0>,<&sgmiisys_phy_1>;
3155 #address-cells = <1>;
3156 #size-cells = <0>;
3157 status = "disabled";
3158 };
3159
3160 stmmac_axi_setup: stmmac-axi-config {
3161 snps,wr_osr_lmt = <0x7>;
3162 snps,rd_osr_lmt = <0x7>;
3163 snps,blen = <0 0 0 0 16 8 4>;
3164 };
3165
3166 mtl_rx_setup: rx-queues-config {
3167 snps,rx-queues-to-use = <1>;
3168 snps,rx-sched-sp;
3169 queue0 {
3170 snps,dcb-algorithm;
3171 snps,map-to-dma-channel = <0x0>;
3172 snps,priority = <0x0>;
3173 };
3174 queue1 {
3175 snps,dcb-algorithm;
3176 snps,map-to-dma-channel = <0x1>;
3177 snps,priority = <0x0>;
3178 snps,route-ptp;
3179 };
3180 queue2 {
3181 snps,dcb-algorithm;
3182 snps,map-to-dma-channel = <0x2>;
3183 snps,priority = <0x0>;
3184 snps,route-multi-broad;
3185 };
3186 };
3187
3188 mtl_tx_setup: tx-queues-config {
3189 snps,tx-queues-to-use = <3>;
3190 snps,tx-sched-wrr;
3191 queue0 {
3192 snps,weight = <0x10>;
3193 snps,dcb-algorithm;
3194 snps,priority = <0x0>;
3195 };
3196
3197 queue1 {
3198 snps,weight = <0x11>;
3199 snps,dcb-algorithm;
3200 snps,priority = <0x1>;
3201 };
3202
3203 queue2 {
3204 snps,weight = <0x12>;
3205 snps,dcb-algorithm;
3206 snps,priority = <0x2>;
3207 };
3208 };
3209
3210 snps_mac: ethernet@11021000 {
3211 compatible = "mediatek,mt2735-gmac";
3212 reg = <0 0x11021000 0 0x1300>;
3213 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3214 interrupt-names = "macirq";
3215 mac-address = [00 55 7b b5 7d f7];
3216 clock-names = "mac_main",
3217 "ptp_ref",
3218 "eth_cg",
3219 "eth_rmii",
3220 "sgmii_sel",
3221 "sgmii_sbus_sel";
3222 clocks = <&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
3223 <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
3224 <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
3225 <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
3226 <&topckgen_clk CLK_TOP_SGMII_SEL>,
3227 <&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
3228 mediatek,pericfg = <&infracfg_ao>;
3229 snps,axi-config = <&stmmac_axi_setup>;
3230 snps,mtl-rx-config = <&mtl_rx_setup>;
3231 snps,mtl-tx-config = <&mtl_tx_setup>;
3232 /*modify by CLK SW Pei-hsuan Cheng */
3233 power-domains = <&scpsys MT6890_POWER_DOMAIN_ETH>;
3234 mediatek,sgmiisys = <&sgmiisys_0>;
3235 mediatek,sgmiisys_phy = <&sgmiisys_phy_0>;
3236 snps,txpbl = <1>;
3237 snps,rxpbl = <1>;
3238 clk_csr = <0>;
3239 status = "disabled";
3240 };
3241
3242 crypto: crypto@10320000 {
3243 /* compatible = "mediatek,eip97-crypto"; */
3244 /* compatible = "safexcel-ip-97-mob"; */
3245 compatible = "inside-secure,safexcel-eip97";
3246 reg = <0 0x10320000 0 0x40000>;
3247 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
3250 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3251 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
3252 interrupt-names = "ring0", "ring1", "ring2", "ring3";
3253 clocks = <&topckgen_clk CLK_TOP_EIP97_SEL>,
3254 <&topckgen_clk CLK_TOP_NET2PLL>,
3255 <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>;
3256 clock-names = "clk-mux", "net2pll", "D5_D2";
3257 power-domains = <&scpsys MT6890_POWER_DOMAIN_EIP97>;
3258 };
3259
3260 dramc_ch1_top0@10240000 {
3261 compatible = "mediatek,dramc_ch1_top0";
3262 reg = <0 0x10240000 0 0x2000>;
3263 };
3264
3265 dramc_ch1_top1@10242000 {
3266 compatible = "mediatek,dramc_ch1_top1";
3267 reg = <0 0x10242000 0 0x2000>;
3268 };
3269
3270 dramc_ch1_top2@10244000 {
3271 compatible = "mediatek,dramc_ch1_top2";
3272 reg = <0 0x10244000 0 0x1000>;
3273 };
3274
3275 dramc_ch1_top3@10245000 {
3276 compatible = "mediatek,dramc_ch1_top3";
3277 reg = <0 0x10245000 0 0x1000>;
3278 };
3279
3280 dramc_ch1_top4@10246000 {
3281 compatible = "mediatek,dramc_ch1_top4";
3282 reg = <0 0x10246000 0 0x2000>;
3283 };
3284
3285 dramc_ch1_top5@10248000 {
3286 compatible = "mediatek,dramc_ch1_top5";
3287 reg = <0 0x10248000 0 0x2000>;
3288 };
3289
3290 dramc_ch1_top6@1024a000 {
3291 compatible = "mediatek,dramc_ch1_top6";
3292 reg = <0 0x1024a000 0 0x2000>;
3293 };
3294
3295 ap_ccif4@1024c000 {
3296 compatible = "mediatek,ap_ccif4";
3297 reg = <0 0x1024c000 0 0x1000>;
3298 };
3299
3300 md_ccif4@1024d000 {
3301 compatible = "mediatek,md_ccif4";
3302 reg = <0 0x1024d000 0 0x1000>;
3303 };
3304
3305 md_ccif4@1024e000 {
3306 compatible = "mediatek,md_ccif4";
3307 reg = <0 0x1024e000 0 0x1000>;
3308 };
3309
3310 dramc_ch2_top0@10250000 {
3311 compatible = "mediatek,dramc_ch2_top0";
3312 reg = <0 0x10250000 0 0x2000>;
3313 };
3314
3315 dramc_ch2_top1@10252000 {
3316 compatible = "mediatek,dramc_ch2_top1";
3317 reg = <0 0x10252000 0 0x2000>;
3318 };
3319
3320 dramc_ch2_top2@10254000 {
3321 compatible = "mediatek,dramc_ch2_top2";
3322 reg = <0 0x10254000 0 0x1000>;
3323 };
3324
3325 dramc_ch2_top3@10255000 {
3326 compatible = "mediatek,dramc_ch2_top3";
3327 reg = <0 0x10255000 0 0x1000>;
3328 };
3329
3330 dramc_ch2_top4@10256000 {
3331 compatible = "mediatek,dramc_ch2_top4";
3332 reg = <0 0x10256000 0 0x2000>;
3333 };
3334
3335 dramc_ch2_top5@10258000 {
3336 compatible = "mediatek,dramc_ch2_top5";
3337 reg = <0 0x10258000 0 0x2000>;
3338 };
3339
3340 dramc_ch2_top6@1025a000 {
3341 compatible = "mediatek,dramc_ch2_top6";
3342 reg = <0 0x1025a000 0 0x2000>;
3343 };
3344
3345 ap_ccif5@1025c000 {
3346 compatible = "mediatek,ap_ccif5";
3347 reg = <0 0x1025c000 0 0x1000>;
3348 };
3349
3350 md_ccif5@1025d000 {
3351 compatible = "mediatek,md_ccif5";
3352 reg = <0 0x1025d000 0 0x1000>;
3353 };
3354
3355 mm_vpu_m0_sub_common@1025e000 {
3356 compatible = "mediatek,mm_vpu_m0_sub_common";
3357 reg = <0 0x1025e000 0 0x1000>;
3358 };
3359
3360 mm_vpu_m1_sub_common@1025f000 {
3361 compatible = "mediatek,mm_vpu_m1_sub_common";
3362 reg = <0 0x1025f000 0 0x1000>;
3363 };
3364
3365 dramc_ch3_top0@10260000 {
3366 compatible = "mediatek,dramc_ch3_top0";
3367 reg = <0 0x10260000 0 0x2000>;
3368 };
3369
3370 dramc_ch3_top1@10262000 {
3371 compatible = "mediatek,dramc_ch3_top1";
3372 reg = <0 0x10262000 0 0x2000>;
3373 };
3374
3375 dramc_ch3_top2@10264000 {
3376 compatible = "mediatek,dramc_ch3_top2";
3377 reg = <0 0x10264000 0 0x1000>;
3378 };
3379
3380 dramc_ch3_top3@10265000 {
3381 compatible = "mediatek,dramc_ch3_top3";
3382 reg = <0 0x10265000 0 0x1000>;
3383 };
3384
3385 dramc_ch3_top4@10266000 {
3386 compatible = "mediatek,dramc_ch3_top4";
3387 reg = <0 0x10266000 0 0x2000>;
3388 };
3389
3390 dramc_ch3_top5@10268000 {
3391 compatible = "mediatek,dramc_ch3_top5";
3392 reg = <0 0x10268000 0 0x2000>;
3393 };
3394
3395 dramc_ch3_top6@1026a000 {
3396 compatible = "mediatek,dramc_ch3_top6";
3397 reg = <0 0x1026a000 0 0x2000>;
3398 };
3399
3400 bcrm_peri@10272000 {
3401 compatible = "mediatek,bcrm_peri";
3402 reg = <0 0x10272000 0 0x1000>;
3403 };
3404
3405 bcrm_peri2@10273000 {
3406 compatible = "mediatek,bcrm_peri2";
3407 reg = <0 0x10273000 0 0x1000>;
3408 };
3409
3410 devapc_peri@10274000 {
3411 compatible = "mediatek,devapc_peri";
3412 reg = <0 0x10274000 0 0x1000>;
3413 };
3414
3415 devapc_peri2@10275000 {
3416 compatible = "mediatek,devapc_peri2";
3417 reg = <0 0x10275000 0 0x1000>;
3418 };
3419
3420 bcrm_fmem@10276000 {
3421 compatible = "mediatek,bcrm_fmem";
3422 reg = <0 0x10276000 0 0x1000>;
3423 };
3424
3425 mm_vpu_m0_sub_common@10309000 {
3426 compatible = "mediatek,mm_vpu_m0_sub_common";
3427 reg = <0 0x10309000 0 0x1000>;
3428 };
3429
3430 mm_vpu_m1_sub_common@1030a000 {
3431 compatible = "mediatek,mm_vpu_m1_sub_common";
3432 reg = <0 0x1030a000 0 0x1000>;
3433 };
3434
3435 mm_vpu_m1_sub_common@1030b000 {
3436 compatible = "mediatek,mm_vpu_m1_sub_common";
3437 reg = <0 0x1030b000 0 0x1000>;
3438 };
3439
3440 mm_vpu_m1_sub_common@1030c000 {
3441 compatible = "mediatek,mm_vpu_m1_sub_common";
3442 reg = <0 0x1030c000 0 0x1000>;
3443 };
3444
3445 mm_vpu_m1_sub_common@1030d000 {
3446 compatible = "mediatek,mm_vpu_m1_sub_common";
3447 reg = <0 0x1030d000 0 0x1000>;
3448 };
3449
3450 sys_cirq1@10312000 {
3451 compatible = "mediatek,sys_cirq1";
3452 reg = <0 0x10312000 0 0x1000>;
3453 };
3454
3455 sys_cirq2@10313000 {
3456 compatible = "mediatek,sys_cirq2";
3457 reg = <0 0x10313000 0 0x1000>;
3458 };
3459
3460 dbg_tracker@10314000 {
3461 compatible = "mediatek,dbg_tracker";
3462 reg = <0 0x10314000 0 0x1000>;
3463 };
3464
3465 pwrmcu@10400000 {
3466 compatible = "mediatek,pwrmcu";
3467 reg = <0 0x10400000 0 0x100000>;
3468 };
3469
3470 sspm@10400000 {
3471 compatible = "mediatek,sspm";
3472 reg = <0 0x10400000 0 0x28000>,
3473 <0 0x10440000 0 0x10000>,
3474 <0 0x10450000 0 0x100>,
3475 <0 0x10451000 0 0x4>,
3476 <0 0x10451004 0 0x4>,
3477 <0 0x10460000 0 0x100>,
3478 <0 0x10461000 0 0x4>,
3479 <0 0x10461004 0 0x4>,
3480 <0 0x10470000 0 0x100>,
3481 <0 0x10471000 0 0x4>,
3482 <0 0x10471004 0 0x4>,
3483 <0 0x10480000 0 0x100>,
3484 <0 0x10481000 0 0x4>,
3485 <0 0x10481004 0 0x4>,
3486 <0 0x10490000 0 0x100>,
3487 <0 0x10491000 0 0x4>,
3488 <0 0x10491004 0 0x4>;
3489
3490 reg-names = "sspm_base",
3491 "cfgreg",
3492 "mbox0_base",
3493 "mbox0_set",
3494 "mbox0_clr",
3495 "mbox1_base",
3496 "mbox1_set",
3497 "mbox1_clr",
3498 "mbox2_base",
3499 "mbox2_set",
3500 "mbox2_clr",
3501 "mbox3_base",
3502 "mbox3_set",
3503 "mbox3_clr",
3504 "mbox4_base",
3505 "mbox4_set",
3506 "mbox4_clr";
3507
3508 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3512 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3513 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3514
3515 interrupt-names = "ipc",
3516 "mbox0",
3517 "mbox1",
3518 "mbox2",
3519 "mbox3",
3520 "mbox4";
3521 };
3522
3523 tinsys@10500000 {
3524 compatible = "mediatek,tinsys";
3525 reg = <0 0x10500000 0 0x0>;
3526 };
3527
3528 dramc_ch1_rsv0@10900000 {
3529 compatible = "mediatek,dramc_ch1_rsv0";
3530 reg = <0 0x10900000 0 0x40000>;
3531 };
3532
3533 dramc_ch1_rsv1@10940000 {
3534 compatible = "mediatek,dramc_ch1_rsv1";
3535 reg = <0 0x10940000 0 0xc0000>;
3536 };
3537
3538 mali: mali@13000000 {
3539 compatible = "mediatek,mali", "arm,mali-midgard", "arm,mali-bifrost";
3540 reg = <0 0x13000000 0 0x4000>;
3541 interrupts =
3542 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
3544 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
3545 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
3546 interrupt-names =
3547 "GPU",
3548 "MMU",
3549 "JOB",
3550 "EVENT";
3551 operating-points-v2 = <&gpu_mali_opp>;
3552 #cooling-cells = <2>;
3553 gpufreq-supply = <&gpufreq>;
3554 };
3555
3556 gpu_mali_opp: opp-table0 {
3557 compatible = "operating-points-v2";
3558 opp00 {
3559 opp-hz = /bits/ 64 <780000000>;
3560 opp-microvolt = <750000>;
3561 };
3562 opp01 {
3563 opp-hz = /bits/ 64 <570000000>;
3564 opp-microvolt = <650000>;
3565 };
3566 opp02 {
3567 opp-hz = /bits/ 64 <360000000>;
3568 opp-microvolt = <600000>;
3569 };
3570 opp03 {
3571 opp-hz = /bits/ 64 <300000000>;
3572 opp-microvolt = <550000>;
3573 };
3574 };
3575
3576 gpufreq: gpufreq {
3577 compatible = "mediatek,gpufreq";
3578 clocks =
3579 <&topckgen_clk CLK_TOP_MFG_SEL>,
3580 <&topckgen_clk CLK_TOP_MFGPLL>,
3581 <&topckgen_clk CLK_TOP_MFG_REF_SEL>,
3582 <&mfgsys_clk CLK_MFGCFG_BG3D>;
3583 clock-names =
3584 "clk_mux", /* switch main/sub */
3585 "clk_main_parent", /* main pll freq */
3586 "clk_sub_parent", /* default 218.4 MHz */
3587 "cg_bg3d";
3588 /* power-domains = <&scpsys MT6890_POWER_DOMAIN_MFG0>; */
3589 status = "disabled";
3590 };
3591
3592 mmc0: mmc@11230000 {
3593 compatible = "mediatek,mt6880-mmc";
3594 reg = <0 0x11230000 0 0x1000>,
3595 <0 0x11f10000 0 0x1000>;
3596 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
3597 clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
3598 <&infracfg_ao_clk CLK_IFRAO_MSDC0>,
3599 <&infracfg_ao_clk CLK_IFRAO_MSDC0_SRC_CLK>;
3600 clock-names = "source", "hclk", "source_cg";
3601 power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
3602 status = "disabled";
3603 };
3604
3605 mmc1: mmc@11240000 {
3606 compatible = "mediatek,mt6880-mmc";
3607 reg = <0 0x11240000 0 0x1000>,
3608 <0 0x11f20000 0 0x1000>;
3609 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3610 clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
3611 <&infracfg_ao_clk CLK_IFRAO_MSDC1>,
3612 <&infracfg_ao_clk CLK_IFRAO_MSDC1_SRC_CLK>;
3613 clock-names = "source", "hclk", "source_cg";
3614 power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
3615 status = "disabled";
3616 };
3617
3618 lvts: lvts@1100b000 {
3619 compatible = "mediatek,mt6880-lvts";
3620 reg = <0 0x1100b000 0 0x1000>,
3621 <0 0x11278000 0 0x1000>,
3622 <0 0x10001000 0 0x1000>;
3623 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3625 clocks = <&infracfg_ao_clk CLK_IFRAO_THERM>;
3626 clock-names = "lvts_clk";
3627
3628 resets = <&infracfg_rst 0>,
3629 <&infracfg_rst 1>;
3630
3631 nvmem-cells = <&lvts_e_data1>;
3632 nvmem-cell-names = "e_data1";
3633 #thermal-sensor-cells = <1>;
3634 };
3635
3636 disp_pwm: disp_pwm0@1100e000 {
3637 compatible = "mediatek,disp_pwm0",
3638 "mediatek,mt6890-disp-pwm";
3639 reg = <0 0x1100e000 0 0x1000>;
3640 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3641 #pwm-cells = <2>;
3642 clocks = <&infracfg_ao CLK_IFRAO_DISP_PWM>,
3643 <&topckgen CLK_TOP_DISP_PWM_SEL>;
3644 clock-names = "main", "mm";
3645 };
3646
3647 pcie0: pcie@11280000 {
3648 compatible = "mediatek,mt2735-pcie";
3649 reg = <0 0x11280000 0 0x2000>;
3650 reg-names = "pcie-mac";
3651 linux,pci-domain = <0>;
3652 #address-cells = <3>;
3653 #size-cells = <2>;
3654 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
3655 bus-range = <0x00 0xff>;
3656 ranges = <0x82000000 0 0x00000000
3657 0x0 0x30000000 0 0x10000000>;
3658 status = "disabled";
3659
3660 clocks = <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_26M>,
3661 <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_96M>,
3662 <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_32K>,
3663 <&infracfg_ao_clk CLK_IFRAO_PCIE_PERI_26M>,
3664 <&infracfg_ao_clk CLK_IFRAO_RG_133M_PCIE_P0>;
3665
3666 phys = <&pciephy0>;
3667 phy-names = "pcie-phy";
3668 power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1>;
3669
3670 #interrupt-cells = <1>;
3671 interrupt-map-mask = <0 0 0 7>;
3672 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
3673 <0 0 0 2 &pcie_intc0 1>,
3674 <0 0 0 3 &pcie_intc0 2>,
3675 <0 0 0 4 &pcie_intc0 3>;
3676 pcie_intc0: legacy-interrupt-controller {
3677 interrupt-controller;
3678 #address-cells = <0>;
3679 #interrupt-cells = <1>;
3680 };
3681 };
3682
3683 pciephy0: phy0@11e40000 {
3684 compatible = "mediatek,mt2735-pcie-phy";
3685 #address-cells = <2>;
3686 #size-cells = <2>;
3687 #phy-cells = <0>;
3688 reg = <0 0x11e40000 0 0x10000>,
3689 <0 0x11e50000 0 0x10000>;
3690 reg-names = "phy-sif", "phy-ckm";
3691 nvmem = <&efuse>;
3692 nvmem-names = "mtk_efuse";
3693 nvmem-cells = <&efuse_segment>;
3694 nvmem-cell-names = "efuse_segment_cell";
3695
3696 power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1_PHY>;
3697 };
3698
3699 efuse: efuse@11ec0000 {
3700 compatible = "mediatek,devinfo";
3701 reg = <0 0x11ec0000 0 0x10000>;
3702 #address-cells = <1>;
3703 #size-cells = <1>;
3704 efuse_segment: segment@78 {
3705 reg = <0x78 0x4>;
3706 };
3707
3708 lvts_e_data1: data1 {
3709 reg = <0x1E0 0x24>;
3710 };
3711 };
3712
3713 dfd@13e00000 {
3714 compatible = "mediatek,dfd";
3715 reg = <0 0x13e00000 0 0x40000>;
3716 };
3717
3718 g3d_dvfs@13fbc000 {
3719 compatible = "mediatek,g3d_dvfs";
3720 reg = <0 0x13fbc000 0 0x1000>;
3721 };
3722
3723 g3d_testbench@13fbd000 {
3724 compatible = "mediatek,g3d_testbench";
3725 reg = <0 0x13fbd000 0 0x1000>;
3726 };
3727
3728 g3d_config@13fbf000 {
3729 compatible = "mediatek,g3d_config";
3730 reg = <0 0x13fbf000 0 0x1000>;
3731 };
3732
3733 mmsys_config: mmsys_config@14000000 {
3734 compatible = "mediatek,mmsys_config";
3735 reg = <0 0x14000000 0 0x1000>;
3736 };
3737
3738 disp_mutex0@14001000 {
3739 compatible = "mediatek,disp_mutex0";
3740 reg = <0 0x14001000 0 0x1000>;
3741 };
3742
3743 mdp_rdma0@14002000 {
3744 compatible = "mediatek,mdp_rdma0";
3745 reg = <0 0x14002000 0 0x1000>;
3746 };
3747
3748 mdp_rsz0@14003000 {
3749 compatible = "mediatek,mdp_rsz0";
3750 reg = <0 0x14003000 0 0x1000>;
3751 };
3752
3753 mdp_wrot0@14004000 {
3754 compatible = "mediatek,mdp_wrot0";
3755 reg = <0 0x14004000 0 0x1000>;
3756 };
3757
3758 mdp_tdshp0@14005000 {
3759 compatible = "mediatek,mdp_tdshp0";
3760 reg = <0 0x14005000 0 0x1000>;
3761 };
3762
3763 disp_ovl0@14006000 {
3764 compatible = "mediatek,disp_ovl0";
3765 reg = <0 0x14006000 0 0x1000>;
3766 };
3767
3768 disp_rdma0@14007000 {
3769 compatible = "mediatek,disp_rdma0";
3770 reg = <0 0x14007000 0 0x1000>;
3771 };
3772
3773 disp_color0@14008000 {
3774 compatible = "mediatek,disp_color0";
3775 reg = <0 0x14008000 0 0x1000>;
3776 };
3777
3778 disp_ccorr0@14009000 {
3779 compatible = "mediatek,disp_ccorr0";
3780 reg = <0 0x14009000 0 0x1000>;
3781 };
3782
3783 disp_aal0@1400a000 {
3784 compatible = "mediatek,disp_aal0";
3785 reg = <0 0x1400a000 0 0x1000>;
3786 };
3787
3788 disp_gamma0@1400b000 {
3789 compatible = "mediatek,disp_gamma0";
3790 reg = <0 0x1400b000 0 0x1000>;
3791 };
3792
3793 disp_dither0@1400c000 {
3794 compatible = "mediatek,disp_dither0";
3795 reg = <0 0x1400c000 0 0x1000>;
3796 };
3797
3798 disp_wdma0@1400d000 {
3799 compatible = "mediatek,disp_wdma0";
3800 reg = <0 0x1400d000 0 0x1000>;
3801 };
3802
3803 dsi0@1400e000 {
3804 compatible = "mediatek,dsi0";
3805 reg = <0 0x1400e000 0 0x1000>;
3806 };
3807
3808 dbpi0@1400f000 {
3809 compatible = "mediatek,dbpi0";
3810 reg = <0 0x1400f000 0 0x1000>;
3811 };
3812
3813 smi_sub_common0@14010000 {
3814 compatible = "mediatek,smi_sub_common0";
3815 reg = <0 0x14010000 0 0x1000>;
3816 };
3817
3818 smi_common0@14016000 {
3819 compatible = "mediatek,smi_common0";
3820 reg = <0 0x14016000 0 0x1000>;
3821 };
3822
3823 smi_larb0: larb@14017000 {
3824 compatible = "mediatek,smi_larb0";
3825 reg = <0 0x14017000 0 0x1000>;
3826 mediatek,larb-id = <0>;
3827 };
3828
3829 spi0: spi0@1100a000 {
3830 compatible = "mediatek,mt6765-spi";
3831 mediatek,pad-select = <0>;
3832 reg = <0 0x1100a000 0 0x100>;
3833 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
3834 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3835 <&topckgen_clk CLK_TOP_SPI_SEL>,
3836 <&infracfg_ao_clk CLK_IFRAO_SPI0>;
3837 clock-names = "parent-clk", "sel-clk", "spi-clk";
3838 };
3839
3840 spi1: spi1@11010000 {
3841 compatible = "mediatek,mt6765-spi";
3842 mediatek,pad-select = <0>;
3843 reg = <0 0x11010000 0 0x100>;
3844 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3845 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3846 <&topckgen_clk CLK_TOP_SPI_SEL>,
3847 <&infracfg_ao_clk CLK_IFRAO_SPI1>;
3848 clock-names = "parent-clk", "sel-clk", "spi-clk";
3849 };
3850
3851 spi2: spi2@11012000 {
3852 compatible = "mediatek,mt6765-spi";
3853 mediatek,pad-select = <0>;
3854 reg = <0 0x11012000 0 0x100>;
3855 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
3856 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3857 <&topckgen_clk CLK_TOP_SPI_SEL>,
3858 <&infracfg_ao_clk CLK_IFRAO_SPI2>;
3859 clock-names = "parent-clk", "sel-clk", "spi-clk";
3860 };
3861
3862 spi3: spi3@11013000 {
3863 compatible = "mediatek,mt6765-spi";
3864 mediatek,pad-select = <0>;
3865 reg = <0 0x11013000 0 0x100>;
3866 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
3867 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3868 <&topckgen_clk CLK_TOP_SPI_SEL>,
3869 <&infracfg_ao_clk CLK_IFRAO_SPI3>;
3870 clock-names = "parent-clk", "sel-clk", "spi-clk";
3871 };
3872
3873 iommu0: iommu@14011000 {
3874 compatible = "mediatek,mt6880-m4u";
3875 reg = <0 14011000 0 0x1000>;
3876 mediatek,larbs = <&smi_larb0>;
3877 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3878#if 0
3879 clocks = <&dispsys_config MM_SMI_INFRA>,
3880 <&dispsys_config MM_SMI_IOMMU>,
3881 <&scpsys SCP_SYS_DIS>;
3882 clock-names = "disp-infra-ck", "disp-iommu-ck", "power";
3883#endif
3884 #iommu-cells = <1>;
3885 };
3886
3887 amms_control {
3888 compatible = "mediatek,amms";
3889 interrupts = <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>;
3890 };
3891
3892 mtk_m4u_debug {
3893 compatible = "mediatek,mt6880-m4u-debug";
3894#if 0
3895 iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
3896 <&iommu0 M4U_PORT_OVL_RDMA0_HDR>,
3897 <&iommu0 M4U_PORT_OVL_RDMA0>,
3898 <&iommu0 M4U_PORT_DISP_FAKE0>;
3899#endif
3900 };
3901
3902 reserved@14018000 {
3903 compatible = "mediatek,reserved";
3904 reg = <0 0x14018000 0 0x1000>;
3905 };
3906
3907 reserved@14019000 {
3908 compatible = "mediatek,reserved";
3909 reg = <0 0x14019000 0 0x1000>;
3910 };
3911
3912 reserved@1401a000 {
3913 compatible = "mediatek,reserved";
3914 reg = <0 0x1401a000 0 0x1000>;
3915 };
3916
3917 reserved@1401b000 {
3918 compatible = "mediatek,reserved";
3919 reg = <0 0x1401b000 0 0x1000>;
3920 };
3921
3922 reserved@1401c000 {
3923 compatible = "mediatek,reserved";
3924 reg = <0 0x1401c000 0 0x1000>;
3925 };
3926
3927 reserved@1401d000 {
3928 compatible = "mediatek,reserved";
3929 reg = <0 0x1401d000 0 0x1000>;
3930 };
3931
3932 reserved@1401e000 {
3933 compatible = "mediatek,reserved";
3934 reg = <0 0x1401e000 0 0x1000>;
3935 };
3936
3937 reserved@1401f000 {
3938 compatible = "mediatek,reserved";
3939 reg = <0 0x1401f000 0 0x1000>;
3940 };
3941
3942 reserved@14020000 {
3943 compatible = "mediatek,reserved";
3944 reg = <0 0x14020000 0 0x1000>;
3945 };
3946
3947 reserved@14021000 {
3948 compatible = "mediatek,reserved";
3949 reg = <0 0x14021000 0 0x1000>;
3950 };
3951
3952 reserved@14022000 {
3953 compatible = "mediatek,reserved";
3954 reg = <0 0x14022000 0 0x1000>;
3955 };
3956
3957 reserved@14023000 {
3958 compatible = "mediatek,reserved";
3959 reg = <0 0x14023000 0 0x1000>;
3960 };
3961
3962 reserved@14024000 {
3963 compatible = "mediatek,reserved";
3964 reg = <0 0x14024000 0 0x1000>;
3965 };
3966
3967 reserved@14025000 {
3968 compatible = "mediatek,reserved";
3969 reg = <0 0x14025000 0 0x1000>;
3970 };
3971
3972 reserved@14026000 {
3973 compatible = "mediatek,reserved";
3974 reg = <0 0x14026000 0 0xda000>;
3975 };
3976
3977 medmcu: medmcu@15f00000 {
3978 compatible = "mediatek,medmcu";
3979 status = "okay";
3980 reg = <0 0x15d00000 0 0x20000>, /* tcm */
3981 <0 0x15f24000 0 0x1000>, /* cfg */
3982 <0 0x15f21000 0 0x1000>, /* clk*/
3983 <0 0x15f30000 0 0x1000>, /* cfg core0 */
3984 <0 0x15f40000 0 0x1000>, /* cfg core1 */
3985 <0 0x15f52000 0 0x1000>, /* bus tracker */
3986 <0 0x15f60000 0 0x40000>, /* llc */
3987 <0 0x15fa5000 0 0x4>, /* cfg_sec */
3988 <0 0x15ffb000 0 0x100>, /* mbox0 base */
3989 <0 0x15ffb100 0 0x4>, /* mbox0 set */
3990 <0 0x15ffb10c 0 0x4>, /* mbox0 clr */
3991 <0 0x15fa5020 0 0x4>, /* mbox0 init */
3992 <0 0x15ffc000 0 0x100>, /* mbox1 base */
3993 <0 0x15ffc100 0 0x4>, /* mbox1 set */
3994 <0 0x15ffc10c 0 0x4>, /* mbox1 clr */
3995 <0 0x15fa5024 0 0x4>, /* mbox1 init */
3996 <0 0x15ffd000 0 0x100>, /* mbox2 base */
3997 <0 0x15ffd100 0 0x4>, /* mbox2 set */
3998 <0 0x15ffd10c 0 0x4>, /* mbox2 clr */
3999 <0 0x15fa5028 0 0x4>, /* mbox2 init */
4000 <0 0x15ffe000 0 0x100>, /* mbox3 base */
4001 <0 0x15ffe100 0 0x4>, /* mbox3 set */
4002 <0 0x15ffe10c 0 0x4>, /* mbox3 clr */
4003 <0 0x15fa502c 0 0x4>, /* mbox3 init */
4004 <0 0x15fff000 0 0x100>, /* mbox4 base */
4005 <0 0x15fff100 0 0x4>, /* mbox4 set */
4006 <0 0x15fff10c 0 0x4>, /* mbox4 clr */
4007 <0 0x15fa5030 0 0x4>; /* mbox4 init */
4008
4009 reg-names = "scp_sram_base",
4010 "scp_cfgreg",
4011 "scp_clkreg",
4012 "scp_cfgreg_core0",
4013 "scp_cfgreg_core1",
4014 "scp_bus_tracker",
4015 "scp_l1creg",
4016 "scp_cfgreg_sec",
4017 "mbox0_base",
4018 "mbox0_set",
4019 "mbox0_clr",
4020 "mbox0_init",
4021 "mbox1_base",
4022 "mbox1_set",
4023 "mbox1_clr",
4024 "mbox1_init",
4025 "mbox2_base",
4026 "mbox2_set",
4027 "mbox2_clr",
4028 "mbox2_init",
4029 "mbox3_base",
4030 "mbox3_set",
4031 "mbox3_clr",
4032 "mbox3_init",
4033 "mbox4_base",
4034 "mbox4_set",
4035 "mbox4_clr",
4036 "mbox4_init";
4037
4038 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4039 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4040 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4041 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4042 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
4043
4044 interrupt-names = "mbox0",
4045 "mbox1",
4046 "mbox2",
4047 "mbox3",
4048 "mbox4";
4049
4050 core_0 = "enable";
4051 scp_sramSize = <0x00020000>;
4052 };
4053
4054 consys: consys@18000000 {
4055 compatible = "mediatek,mt6880-consys";
4056 #thermal-sensor-cells = <0>;
4057 /* conn_infra_rgu */
4058 reg = <0 0x18000000 0 0x1000>,
4059 /* conn_infra_cfg */
4060 <0 0x18001000 0 0x1000>,
4061 /* conn_host_csr_top */
4062 <0 0x18060000 0 0x10000>,
4063 /* infracfg_ao */
4064 <0 0x10001000 0 0x1000>,
4065 /* TOP RGU */
4066 <0 0x10007000 0 0x1000>,
4067 /* SPM */
4068 <0 0x10006000 0 0x1000>,
4069 /* INFRACFG */
4070 <0 0x1020e000 0 0x1000>,
4071 /* conn_wt_slp_ctl_reg */
4072 <0 0x18005000 0 0x1000>,
4073 /* conn_afe_ctl */
4074 <0 0x18003000 0 0x1000>,
4075 /* GPIO */
4076 <0 0x10005000 0 0x1000>,
4077 /* conn_rf_spi_mst_reg */
4078 <0 0x18004000 0 0x1000>,
4079 /* conn_semaphore */
4080 <0 0x18070000 0 0x10000>,
4081 /* conn_top_therm_ctl */
4082 <0 0x18002000 0 0x1000>,
4083 /* IOCFG_BM */
4084 <0 0x11d10000 0 0x1000>,
4085 /* debug_ctrl */
4086 <0 0x1800f000 0 0x1000>,
4087 /* conn_infra_clkgen_on_top */
4088 <0 0x18009000 0 0x1000>,
4089 /* conn_infra_bus_cr */
4090 <0 0x1800e000 0 0x400>,
4091 /* conn_infra_debug_ctrl_ao */
4092 <0 0x1802f000 0 0x430>;
4093 power-domains = <&scpsys MT6890_POWER_DOMAIN_CONN>;
4094 };
4095
4096 gps: gps@18C00000 {
4097 compatible = "mediatek,connac2-gps";
4098 reg = <0 0x18000000 0 0x100000>,
4099 <0 0x18C00000 0 0x100000>,
4100 <0 0x10003304 0 0x4>,
4101 <0 0x1001C000 0 0x4>,
4102 <0 0x1001C030 0 0x4>;
4103 reg-names = "conn_infra_base", "conn_gps_base",
4104 "status_dummy_cr", "tia2_gps_on", "tia2_gps_rc_sel";
4105 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
4106 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
4107 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
4111 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
4112 memory-region = <&gps_mem>;
4113 pmic = <&pmic_efuse>;
4114 mtk-vcore-supply = <&dvfsrc_vcore>;
4115 };
4116
4117 odm: odm {
4118 compatible = "simple-bus";
4119 /* reserved for overlay by odm */
4120 };
4121
4122 pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
4123 compatible = "mediatek,pmic_clock_buffer";
4124 mediatek,clkbuf-quantity = <7>;
4125 mediatek,clkbuf-config = <2 1 1 2 0 0 2>;
4126 mediatek,clkbuf-output-impedance = <3 4 3 4 0 0 3>;
4127 mediatek,clkbuf-controls-for-desense = <0 4 0 3 0 0 0>;
4128 mediatek,bblpm-support = "enable";
4129
4130 pwrap-dcxo-en = <0x24 4 0x28 1 0x28 0>;
4131 pwrap-dcxo-conn = <0x5c 0 0x5c 16 0x60 0 0x60 16>;
4132 pwrap-dcxo-nfc = <0x64 0 0x64 16 0x68 0 0x68 16>;
4133
4134 spm-pwr-status = <0x16c 0 0x16c 1>;
4135 spm-io-en = <0x2c 7>;
4136 spm-power-on-val = <0x8 21 0x8 14>;
4137 spm-sck-con = <0xc 24>;
4138 pcm-reg7-rf = <0x10c 21>;
4139
4140 pwrap = <&spmi_bus>;
4141 sleep = <&sleep>;
4142 };
4143 typec_switch: typec_switch {
4144 compatible = "mediatek,typec_switch";
4145 };
4146
4147 afe: mt6880-afe-pcm@11210000 {
4148 compatible = "mediatek,mt6880-sound";
4149 reg = <0 0x11210000 0 0x1000>;
4150 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
4151 i2s3-share = "I2S0";
4152 topckgen = <&topckgen_clk>;
4153 power-domains = <&scpsys MT6890_POWER_DOMAIN_AUDIO>;
4154 clocks = <&audsys_clk CLK_AUDSYS_AFE>,
4155 <&audsys_clk CLK_AUDSYS_DAC>,
4156 <&audsys_clk CLK_AUDSYS_DAC_PREDIS>,
4157 <&audsys_clk CLK_AUDSYS_ADC>,
4158 <&audsys_clk CLK_AUDSYS_22M>,
4159 <&audsys_clk CLK_AUDSYS_24M>,
4160 <&audsys_clk CLK_AUDSYS_APLL_TUNER>,
4161 <&audsys_clk CLK_AUDSYS_APLL2_TUNER>,
4162 <&audsys_clk CLK_AUDSYS_TDM>,
4163 <&audsys_clk CLK_AUDSYS_TML>,
4164 <&infracfg_ao_clk CLK_IFRAO_AUDIO>,
4165 <&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>,
4166 <&topckgen_clk CLK_TOP_AUDIO_SEL>,
4167 <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
4168 <&topckgen_clk CLK_TOP_MMPLL_D4_D4>,
4169 <&topckgen_clk CLK_TOP_AUD_1_SEL>,
4170 <&topckgen_clk CLK_TOP_APLL1>,
4171 <&topckgen_clk CLK_TOP_AUD_2_SEL>,
4172 <&topckgen_clk CLK_TOP_APLL2>,
4173 <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
4174 <&topckgen_clk CLK_TOP_APLL1_D8>,
4175 <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
4176 <&topckgen_clk CLK_TOP_APLL2_D8>,
4177 <&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
4178 <&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
4179 <&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
4180 <&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
4181 <&topckgen_clk CLK_TOP_APLL_TDMOUT_MCK_SEL>,
4182 <&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
4183 <&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
4184 <&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
4185 <&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
4186 <&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
4187 <&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
4188 <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
4189 <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_B>,
4190 <&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
4191 <&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
4192 <&topckgen_clk CLK_TOP_TCK_26M_MX9>;
4193 clock-names = "aud_afe_clk",
4194 "aud_dac_clk",
4195 "aud_dac_predis_clk",
4196 "aud_adc_clk",
4197 "aud_apll22m_clk",
4198 "aud_apll24m_clk",
4199 "aud_apll1_tuner_clk",
4200 "aud_apll2_tuner_clk",
4201 "aud_tdm_clk",
4202 "aud_tml_clk",
4203 "aud_infra_clk",
4204 "mtkaif_26m_clk",
4205 "top_mux_audio",
4206 "top_mux_audio_int",
4207 "top_mainpll_d2_d4",
4208 "top_mux_aud_1",
4209 "top_apll1_ck",
4210 "top_mux_aud_2",
4211 "top_apll2_ck",
4212 "top_mux_aud_eng1",
4213 "top_apll1_d8",
4214 "top_mux_aud_eng2",
4215 "top_apll2_d8",
4216 "top_i2s0_m_sel",
4217 "top_i2s1_m_sel",
4218 "top_i2s2_m_sel",
4219 "top_i2s4_m_sel",
4220 "top_tdm_m_sel",
4221 "top_i2s5_m_sel",
4222 "top_i2s6_m_sel",
4223 "top_apll12_div0",
4224 "top_apll12_div1",
4225 "top_apll12_div2",
4226 "top_apll12_div4",
4227 "top_apll12_divm",
4228 "top_apll12_divb",
4229 "top_apll12_div5",
4230 "top_apll12_div6",
4231 "top_clk26m_clk";
4232 pinctrl-names = "aud_gpio_i2s0_off",
4233 "aud_gpio_i2s0_on",
4234 "aud_gpio_i2s1_off",
4235 "aud_gpio_i2s1_on",
4236 "aud_gpio_i2s2_off",
4237 "aud_gpio_i2s2_on",
4238 "aud_gpio_i2s3_off",
4239 "aud_gpio_i2s3_on",
4240 "aud_gpio_i2s4_off",
4241 "aud_gpio_i2s4_on",
4242 "aud_gpio_i2s5_off",
4243 "aud_gpio_i2s5_on",
4244 "aud_gpio_i2s6_off",
4245 "aud_gpio_i2s6_on",
4246 "aud_gpio_proslic_off",
4247 "aud_gpio_proslic_on",
4248 "aud_gpio_tdm_off",
4249 "aud_gpio_tdm_on",
4250 "extamp-pullhigh",
4251 "extamp-pulllow";
4252 pinctrl-0 = <&aud_gpio_i2s0_off>;
4253 pinctrl-1 = <&aud_gpio_i2s0_on>;
4254 pinctrl-2 = <&aud_gpio_i2s1_off>;
4255 pinctrl-3 = <&aud_gpio_i2s1_on>;
4256 pinctrl-4 = <&aud_gpio_i2s2_off>;
4257 pinctrl-5 = <&aud_gpio_i2s2_on>;
4258 pinctrl-6 = <&aud_gpio_i2s3_off>;
4259 pinctrl-7 = <&aud_gpio_i2s3_on>;
4260 pinctrl-8 = <&aud_gpio_i2s4_off>;
4261 pinctrl-9 = <&aud_gpio_i2s4_on>;
4262 pinctrl-10 = <&aud_gpio_i2s5_off>;
4263 pinctrl-11 = <&aud_gpio_i2s5_on>;
4264 pinctrl-12 = <&aud_gpio_i2s6_off>;
4265 pinctrl-13 = <&aud_gpio_i2s6_on>;
4266 pinctrl-14 = <&aud_gpio_proslic_off>;
4267 pinctrl-15 = <&aud_gpio_proslic_on>;
4268 pinctrl-16 = <&aud_gpio_tdm_off>;
4269 pinctrl-17 = <&aud_gpio_tdm_on>;
4270 pinctrl-18 = <&aud_pins_extamp_high>;
4271 pinctrl-19 = <&aud_pins_extamp_low>;
4272 };
4273 sound: sound {
4274 compatible = "mediatek,mt6880-mt6359-sound";
4275 mediatek,platform = <&afe>;
4276 };
4277
4278 audio_sram@11211000 {
4279 compatible = "mediatek,audio_sram";
4280 reg = <0 0x11211000 0 0x10000>;
4281 prefer_mode = <1>;
4282 mode_size = <0xC000 0x10000>;
4283 block_size = <0x1000>;
4284 };
4285
4286 smart_pa: smart_pa {
4287 };
4288
4289 extcon_usb: extcon_usb {
4290 compatible = "mediatek,extcon-usb";
4291 dev-conn = <&ssusb>;
4292 };
4293};
4294
4295&spmi_bus {
4296 mt6315_5: mt6315@5 {
4297 compatible = "mediatek,mt6315", "mtk,spmi-pmic";
4298 reg = <0x5 SPMI_USID 0xb SPMI_GSID>;
4299 #address-cells = <1>;
4300 #size-cells = <0>;
4301 mt6315_5_regulator: mt6315_5_regulator {
4302 compatible = "mediatek,mt6315_5-regulator";
4303 #interrupt-cells = <2>;
4304 interrupt-controller;
4305 interrupt-parent = <&pio>;
4306 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
4307 };
4308 };
4309
4310 md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
4311 };
4312
4313 md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
4314 };
4315};
4316#include "mt6890-clkao.dtsi"
4317#include "mt6330.dtsi"
4318#include "cust_mt6890_msdc.dtsi"
4319
4320&pmic {
4321 mt63xx_ot_debug: mt63xx-ot-debug {
4322 compatible = "mediatek,mt63xx-ot-debug";
4323 interrupt-parent = <&mt6315_5_regulator>;
4324 /* INT_TEMP_H */
4325 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
4326 };
4327};