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192.168.1.100 / T800 / df7242cdc1476484ea05f45c0d5c441fb87e54f8 / . / meta-sdk / meta / meta-lynqSDK-T800 / recipes-kernel / linux / files / mt2735.dtsi
blob: c233f90b824c6b742ec51bef805b40b35e87cb67 [file] [log] [blame]
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 */
5
6/dts-v1/;
7#include <generated/autoconf.h>
8
9#include <dt-bindings/clock/mt6890-clk.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/mt2735-pinfunc.h>
13#include <dt-bindings/memory/mt6880-larb-port.h>
14#include <dt-bindings/power/mt6890-power.h>
15#include <dt-bindings/reset/ti-syscon.h>
16#include <dt-bindings/soc/mediatek,boot-mode.h>
17#include <dt-bindings/spmi/spmi.h>
18#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/input/input.h>
20#include <dt-bindings/phy/phy.h>
21#include <dt-bindings/interconnect/mtk,mt6873-emi.h>
22#include <dt-bindings/iio/mt635x-auxadc.h>
23#include <dt-bindings/gce/mt6890-gce.h>
24#include <dt-bindings/thermal/thermal.h>
25/ {
26 model = "MT6890";
27 compatible = "mediatek,MT6890";
28 interrupt-parent = <&gic>;
29 #address-cells = <2>;
30 #size-cells = <2>;
31
32 /* chosen */
33 chosen: chosen {
34 bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
35 vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
36 firmware_class.path=/vendor/firmware \
37 page_owner=on";
38 };
39
40 psci {
41 compatible = "arm,psci-0.2";
42 method = "smc";
43 };
44
45 gpio_leds {
46 compatible = "gpio-leds";
47 led0 {
48 label = "led9501:red:sim";
49 gpios = <&pio 209 GPIO_ACTIVE_HIGH>;
50 linux,default-trigger = "none";
51 default-state = "off";
52 };
53 led1 {
54 label = "led9502:red:cellular-stat";
55 gpios = <&pio 210 GPIO_ACTIVE_HIGH>;
56 linux,default-trigger = "none";
57 default-state = "off";
58 };
59 led2 {
60 label = "led9504:red:cellular-data";
61 gpios = <&pio 211 GPIO_ACTIVE_HIGH>;
62 linux,default-trigger = "none";
63 default-state = "off";
64 };
65 led3 {
66 label = "led9505:red:cellular-rat";
67 gpios = <&pio 212 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "none";
69 default-state = "off";
70 };
71 led4 {
72 label = "led9506:red:cellular-ims";
73 gpios = <&pio 213 GPIO_ACTIVE_HIGH>;
74 linux,default-trigger = "none";
75 default-state = "off";
76 };
77 };
78
79 cluster0_opp: opp_table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
82 opp0 {
83 opp-hz = /bits/ 64 <500000000>;
84 opp-microvolt = <650000>;
85 };
86 opp1 {
87 opp-hz = /bits/ 64 <600000000>;
88 opp-microvolt = <650000>;
89 };
90 opp2 {
91 opp-hz = /bits/ 64 <684000000>;
92 opp-microvolt = <668750>;
93 };
94 opp3 {
95 opp-hz = /bits/ 64 <768000000>;
96 opp-microvolt = <687500>;
97 };
98 opp4 {
99 opp-hz = /bits/ 64 <820000000>;
100 opp-microvolt = <700000>;
101 };
102 opp5 {
103 opp-hz = /bits/ 64 <937000000>;
104 opp-microvolt = <725000>;
105 };
106 opp6 {
107 opp-hz = /bits/ 64 <1060000000>;
108 opp-microvolt = <750000>;
109 };
110 opp7 {
111 opp-hz = /bits/ 64 <1134000000>;
112 opp-microvolt = <768750>;
113 };
114 opp8 {
115 opp-hz = /bits/ 64 <1275000000>;
116 opp-microvolt = <800000>;
117 };
118 opp9 {
119 opp-hz = /bits/ 64 <1387000000>;
120 opp-microvolt = <825000>;
121 };
122 opp10 {
123 opp-hz = /bits/ 64 <1500000000>;
124 opp-microvolt = <850000>;
125 };
126 opp11 {
127 opp-hz = /bits/ 64 <1666000000>;
128 opp-microvolt = <900000>;
129 };
130 opp12 {
131 opp-hz = /bits/ 64 <1750000000>;
132 opp-microvolt = <925000>;
133 };
134 opp13 {
135 opp-hz = /bits/ 64 <1833000000>;
136 opp-microvolt = <950000>;
137 };
138 opp14 {
139 opp-hz = /bits/ 64 <1916000000>;
140 opp-microvolt = <975000>;
141 };
142 opp15 {
143 opp-hz = /bits/ 64 <2000000000>;
144 opp-microvolt = <1000000>;
145 };
146 };
147
148 cpus {
149 #address-cells = <1>;
150 #size-cells = <0>;
151
152 cpu0: cpu@0 {
153 device_type = "cpu";
154 compatible = "arm,cortex-a55";
155 reg = <0x0000>;
156 enable-method = "psci";
157 clock-frequency = <1701000000>;
158 operating-points-v2 = <&cluster0_opp>;
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]159 dynamic-power-coefficient = <85>;
160 #cooling-cells = <2>;
161 };
162
163 cpu1: cpu@001 {
164 device_type = "cpu";
165 compatible = "arm,cortex-a55";
166 reg = <0x0100>;
167 enable-method = "psci";
168 clock-frequency = <1701000000>;
169 operating-points-v2 = <&cluster0_opp>;
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]170 dynamic-power-coefficient = <85>;
171 #cooling-cells = <2>;
172 };
173
174 cpu2: cpu@002 {
175 device_type = "cpu";
176 compatible = "arm,cortex-a55";
177 reg = <0x0200>;
178 enable-method = "psci";
179 clock-frequency = <1701000000>;
180 operating-points-v2 = <&cluster0_opp>;
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]181 dynamic-power-coefficient = <85>;
182 #cooling-cells = <2>;
183 };
184
185 cpu3: cpu@003 {
186 device_type = "cpu";
187 compatible = "arm,cortex-a55";
188 reg = <0x0300>;
189 enable-method = "psci";
190 clock-frequency = <1701000000>;
191 operating-points-v2 = <&cluster0_opp>;
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]192 dynamic-power-coefficient = <85>;
193 #cooling-cells = <2>;
194 };
195
196 cpu-map {
197 cluster0 {
198 core0 {
199 cpu = <&cpu0>;
200 };
201 core1 {
202 cpu = <&cpu1>;
203 };
204 core2 {
205 cpu = <&cpu2>;
206 };
207 core3 {
208 cpu = <&cpu3>;
209 };
210 };
211 };
212
you.chendf7242c2023-12-13 18:42:48 +0800[diff] [blame^]213#if 0
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]214 idle-states {
215 entry-method = "arm,psci";
216 cpuoff_l: cpuoff_l {
217 compatible = "mediatek,idle-state";
218 arm,psci-suspend-param = <0x00010001>;
219 local-timer-stop;
220 entry-latency-us = <50>;
221 exit-latency-us = <100>;
222 min-residency-us = <1600>;
223 };
224 clusteroff_l: clusteroff_l {
225 compatible = "mediatek,idle-state";
226 arm,psci-suspend-param = <0x01010001>;
227 local-timer-stop;
228 entry-latency-us = <100>;
229 exit-latency-us = <250>;
230 min-residency-us = <2100>;
231 };
232 mcusysoff: mcusysoff {
233 compatible = "mediatek,idle-state";
234 arm,psci-suspend-param = <0x01010002>;
235 local-timer-stop;
236 entry-latency-us = <300>;
237 exit-latency-us = <1200>;
238 min-residency-us = <2600>;
239 };
240 };
you.chendf7242c2023-12-13 18:42:48 +0800[diff] [blame^]241#endif
rjwdbb8a262022-11-01 14:17:32 +0800[diff] [blame]242
243 };
244
245 pmu {
246 compatible = "arm,armv8-pmuv3";
247 interrupt-parent = <&gic>;
248 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
249 };
250
251 dsu-pmu-0 {
252 compatible = "arm,dsu-pmu";
253 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
254 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
255 };
256
257 dvfsp: dvfsp@0011bc00 {
258 compatible = "mediatek,mcupm-dvfsp";
259 reg = <0 0x0011bc00 0 0x1400>;
260 nvmem = <&efuse>;
261 nvmem-names = "mtk_efuse";
262 nvmem-cells = <&efuse_segment>;
263 nvmem-cell-names = "efuse_segment_cell";
264 };
265
266 leakage@1100b000 {
267 compatible = "mediatek,leakage";
268 reg = <0 0x1100b000 0 0x1000>;
269 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
270 nvmem = <&efuse>;
271 nvmem-names = "mtk_efuse";
272 nvmem-cells = <&efuse_segment>;
273 nvmem-cell-names = "efuse_segment_cell";
274 n-domain = <7>;
275 domain = "LL", "CCI", "VCORE", "MODEM_NR", "VSRAM_CPULL", "VSRAM_MODEM", "VCORE_OFF";
276 LL = <750 30 0x224 0 0 1>;
277 CCI = <750 30 0x220 24 0 1>;
278 VCORE = <750 30 0x21C 16 0 1>;
279 MODEM_NR = <825 30 0x21C 8 0 1>;
280 VSRAM_CPULL = <750 30 0X228 16 0 1>;
281 VSRAM_MODEM = <825 30 0X22C 0 0 1>;
282 VCORE_OFF = <550 30 0x224 16 0 1>;
283 };
284
285 memory {
286 device_type = "memory";
287#if defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 1024)
288 reg = <0 0x40000000 0 0x40000000>;
289#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 896)
290 reg = <0 0x40000000 0 0x38000000>;
291#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 768)
292 reg = <0 0x40000000 0 0x30000000>;
293#elif defined(CONFIG_MTK_MEMORY_SIZE) && (CONFIG_MTK_MEMORY_SIZE == 640)
294 reg = <0 0x40000000 0 0x28000000>;
295#else
296 reg = <0 0x40000000 0 0x20000000>;
297#endif
298 };
299
300 wed: wed@15010000 {
301 compatible = "mediatek,wed";
302 wed_num = <2>;
303 /* add this property for wed get the pci slot number. */
304 pci_slot_map = <0>, <1>;
305 reg = <0 0x15010000 0 0x1000>,
306 <0 0x15011000 0 0x1000>;
307 interrupt-parent = <&gic>;
308 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
310 };
311
312 wed2: wed2@15011000 {
313 compatible = "mediatek,wed2";
314 wed_num = <2>;
315 reg = <0 0x15010000 0 0x1000>,
316 <0 0x15011000 0 0x1000>;
317 interrupt-parent = <&gic>;
318 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>;
320 };
321
322 wdma: wdma@15102800 {
323 compatible = "mediatek,wed-wdma";
324 reg = <0 0x15102800 0 0x400>,
325 <0 0x15102c00 0 0x400>;
326 interrupt-parent = <&gic>;
327 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
333 };
334
335 ap2woccif: ap2woccif@151A9000 {
336 compatible = "mediatek,ap2woccif";
337 reg = <0 0x151a9000 0 0x1000>,
338 <0 0x151ab000 0 0x1000>;
339 interrupt-parent = <&gic>;
340 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
342 };
343
344 wocpu_sysram: wocpu@15180000 {
345 compatible = "mediatek,wocpu_sysram";
346 reg = <0 0x15180000 0 0x8000>;
347 shared = <1>;
348 };
349
350 wocpu_dlm: wocpu_dlm@1518E000 {
351 compatible = "mediatek,wocpu_dlm";
352 reg = <0 0x1518E000 0 0x2000>,
353 <0 0x15192000 0 0x2000>;
354
355 resets = <&ethsysrst 0>;
356 reset-names = "wocpu_rst";
357 };
358
359 cpu_boot: wocpu_boot@15194000 {
360 compatible = "mediatek,wocpu_boot";
361 reg = <0 0x15194000 0 0x1000>;
362 };
363
364 pcie_mirror: pcie_mirror@10201000 {
365 compatible = "mediatek,pcie-mirror";
366 reg = <0 0x10201000 0 0x1000>;
367 };
368
369 reserved_memory: reserved-memory {
370 #address-cells = <2>;
371 #size-cells = <2>;
372 ranges;
373
374 reserve-memory-atf {
375 compatible = "mediatek,reserve-memory-atf";
376 no-map;
377 reg = <0 0x42FC0000 0 0x1FA000>;
378 };
379
380 reserve-memory-mcupm_share {
381 compatible = "mediatek,reserve-memory-mcupm_share";
382 no-map;
383 status = "okay";
384#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
385 reg = <0 0x42290000 0 0x210000>; /* 2M + 64K */
386#else
387 reg = <0 0x42290000 0 0x610000>; /* 6M + 64K */
388#endif
389 };
390
391 reserve-memory-sspm_share {
392 compatible = "mediatek,reserve-memory-sspm_share";
393 no-map;
394 status = "okay";
395#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
396 reg = <0 0x429A0000 0 0x210000>; /* 2M + 64K */
397#else
398 reg = <0 0x429A0000 0 0x610000>; /* 6M + 64K */
399#endif
400 };
401
402 gps_mem: gps-reserve-memory {
403 compatible = "mediatek,gps-reserve-memory";
404 no-map;
405 reg = <0 0x432ca000 0 0x60000>; /* 384KB */
406 };
407
408 reserved-memory-pstore {
409 compatible = "ramoops";
410 reg = <0x0 0x4332a000 0x0 0xe0000>;
411 record-size = <0x1000>;
412 console-size = <0x40000>;
413 ftrace-size = <0x1000>;
414 pmsg-size = <0x10000>;
415 };
416
417 reserved-memory-aee {
418 reg = <0x0 0x4340a000 0x0 0x100000>;
419 compatible = "mediatek,aee-lk";
420 };
421
422 reserved-memory-minirdump {
423 reg = <0x0 0x4350a000 0x0 0x10000>;
424 no-map;
425 compatible = "mediatek,minirdump";
426 };
427
428 reserved-memory-ram_console {
429 reg = <0x0 0x4351a000 0x0 0x10000>;
430 no-map;
431 compatible = "mediatek,ram_console";
432 };
433
434 reserved-memory-log_store {
435 reg = <0x0 0x4352a000 0x0 0x40000>;
436 compatible = "mediatek,log_store";
437 };
438
439 wocpu0_emi: wocpu0_emi@50000000 {
440 compatible = "mediatek,wocpu0_emi";
441 no-map;
442 reg = <0 0x50000000 0 0x80000>;
443 shared = <0>;
444 };
445
446 wocpu1_emi: wocpu1_emi@50040000 {
447 compatible = "mediatek,wocpu1_emi";
448 no-map;
449 reg = <0 0x50080000 0 0x80000>;
450 shared = <0>;
451 };
452
453 wocpu_data: wocpu_data@50100000 {
454 compatible = "mediatek,wocpu_data";
455 no-map;
456 reg = <0 0x50100000 0 0x180000>;
457 shared = <1>;
458 };
459 };
460
461 gic: interrupt-controller {
462 compatible = "arm,gic-v3";
463 #interrupt-cells = <3>;
464 #address-cells = <2>;
465 #size-cells = <2>;
466 #redistributor-regions = <1>;
467 interrupt-parent = <&gic>;
468 interrupt-controller;
469 reg = <0 0x0c000000 0 0x40000>, // distributor
470 <0 0x0c040000 0 0x200000>; // redistributor
471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
472 };
473
474 clkao: clkao {
475 compatible = "simple-bus";
476 };
477
478 clocks {
479 clk_null: clk_null {
480 compatible = "fixed-clock";
481 #clock-cells = <0>;
482 clock-frequency = <0>;
483 };
484
485 clk10m: clk10m {
486 compatible = "fixed-clock";
487 #clock-cells = <0>;
488 clock-frequency = <10000000>;
489 };
490
491 clk26m: clk26m {
492 compatible = "fixed-clock";
493 #clock-cells = <0>;
494 clock-frequency = <26000000>;
495 };
496
497 clk12m: clk12m {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-frequency = <12000000>;
501 };
502
503 clk32k: clk32k {
504 compatible = "fixed-clock";
505 #clock-cells = <0>;
506 clock-frequency = <32000>;
507 };
508
509 clk13m: clk13m {
510 compatible = "fixed-clock";
511 #clock-cells = <0>;
512 clock-frequency = <13000000>;
513 };
514
515 ulposc: ulposc {
516 compatible = "fixed-clock";
517 #clock-cells = <0>;
518 clock-frequency = <260000000>;
519 };
520 };
521
522 topckgen_clk: syscon@10000000 {
523 compatible = "mediatek,mt6890-topckgen", "syscon";
524 reg = <0 0x10000000 0 0x1000>;
525 #clock-cells = <1>;
526 };
527
528 apmixedsys_clk: syscon@1000c000 {
529 compatible = "mediatek,mt6890-apmixedsys", "syscon";
530 reg = <0 0x1000c000 0 0xe00>;
531 #clock-cells=<1>;
532 };
533
534 dbgsys_dem_clk: syscon@0d0a0000 {
535 compatible = "mediatek,mt6890-dbgsys_dem", "syscon";
536 reg = <0 0x0d0a0000 0 0x1000>;
537 #clock-cells = <1>;
538 };
539
540 infracfg_ao_clk: syscon@10001000 {
541 compatible = "mediatek,mt6890-infracfg_ao", "syscon";
542 reg = <0 0x10001000 0 0x1000>;
543 #clock-cells = <1>;
544 };
545
546 pericfg_clk: syscon@10003000 {
547 compatible = "mediatek,mt6890-pericfg", "syscon";
548 reg = <0 0x10003000 0 0x1000>;
549 #clock-cells = <1>;
550 };
551
552 scpsys: power-controller@10006000 {
553 compatible = "mediatek,mt6890-scpsys", "syscon";
554 reg = <0 0x10006000 0 0x1000>;
555 #power-domain-cells = <1>;
556 infracfg = <&infracfg_ao_clk>;
557 clocks = <&topckgen_clk CLK_TOP_MM_SEL>,
558 <&topckgen_clk CLK_TOP_MFG_SEL>,
559 <&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
560 <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
561 <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
562 <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
563 <&topckgen_clk CLK_TOP_EIP97_SEL>,
564 <&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>;
565 clock-names = "mm",
566 "mfg",
567 "snps_eth_312p5m_sel",
568 "snps_eth_250m_sel",
569 "snps_ptp_sel",
570 "snps_rmii_sel",
571 "eip97_sel",
572 "audio";
573 /*status="disabled";*/
574 };
575
576 gce_clk: syscon@10228000 {
577 compatible = "mediatek,mt6890-gce", "syscon";
578 reg = <0 0x10228000 0 0x1000>;
579 #clock-cells = <1>;
580 };
581
582 audsys_clk: syscon@11210000 {
583 compatible = "mediatek,mt6890-audsys", "syscon";
584 reg = <0 0x11210000 0 0x1000>;
585 #clock-cells = <1>;
586 };
587
588 imp_iic_wrap_e_clk: syscon@11c46000 {
589 compatible = "mediatek,mt6890-imp_iic_wrap_e", "syscon";
590 reg = <0 0x11c46000 0 0x1000>;
591 #clock-cells = <1>;
592 };
593
594 mfgsys_clk: syscon@13fbf000 {
595 compatible = "mediatek,mt6890-mfgsys", "syscon";
596 reg = <0 0x13fbf000 0 0x1000>;
597 #clock-cells = <1>;
598 };
599
600 mmsys_config_clk: syson@14000000 {
601 compatible = "mediatek,mt6890-mmsys_config", "syscon";
602 reg = <0 0x14000000 0 0x1000>;
603 #clock-cells = <1>;
604 };
605
606 mtk_lpm: mtk_lpm {
607 compatible = "mediatek,mtk-lpm";
608 #address-cells = <2>;
609 #size-cells = <2>;
610 ranges;
611 suspend-method = "system";
612 irq-remain = <&edge_keypad &edge_mdwdt>;
613 resource-ctrl = <&bus26m &infra &syspll>,
614 <&dram_s0 &dram_s1>;
615 constraints = <&rc_bus26m &rc_syspll &rc_dram>;
616
617 lpm_sysram: lpm_sysram@0011b500 {
618 compatible = "mediatek,lpm-sysram";
619 reg = <0 0x0011b500 0 0x300>;
620 };
621
622 irq-remain-list {
623 edge_keypad: edge_keypad {
624 target = <&keypad>;
625 value = <1 0 0 0x4>;
626 };
627 edge_mdwdt: edge_mdwdt {
628 target = <&mddriver>;
629 value = <1 0 0 0x02000000>;
630 };
631 };
632 resource-ctrl-list {
633 bus26m: bus26m {
634 id = <0x00000000>;
635 value = <0>;
636 };
637 infra: infra {
638 id = <0x00000001>;
639 value = <0>;
640 };
641 syspll: syspll {
642 id = <0x00000002>;
643 value = <0>;
644 };
645 dram_s0: dram_s0 {
646 id = <0x00000003>;
647 value = <0>;
648 };
649 dram_s1: dram_s1 {
650 id = <0x00000004>;
651 value = <0>;
652 };
653 };
654 constraint-list {
655 rc_bus26m: rc_bus26m {
656 id = <0x00000000>;
657 value = <1>;
658 };
659 rc_syspll: rc_syspll {
660 id = <0x00000001>;
661 value = <1>;
662 };
663 rc_dram: rc_dram {
664 id = <0x00000002>;
665 value = <1>;
666 };
667 };
668 };
669
670 cpupm_sysram: cpupm-sysram@0011b000 {
671 compatible = "mediatek,cpupm-sysram";
672 reg = <0 0x0011b000 0 0x500>;
673 };
674
675 mcusys_ctrl: mcusys-ctrl@0c53a000 {
676 compatible = "mediatek,mcusys-ctrl";
677 reg = <0 0x0c53a000 0 0x1000>;
678 };
679
680 tboard_thermistor1: thermal-ntc1 {
681 compatible = "mediatek,mt6880-board-ntc";
682 #thermal-sensor-cells = <0>;
683 reg = <0 0x1001C0D4 0 0x4>; /* TIA DATA T0 */
684 pmic_auxadc = <&pmic_auxadc>;
685 temperature-lookup-table = <
686 (-40000) 4397119
687 (-39000) 4092874
688 (-38000) 3811717
689 (-37000) 3551749
690 (-36000) 3311236
691 (-35000) 3088599
692 (-34000) 2882396
693 (-33000) 2691310
694 (-32000) 2514137
695 (-31000) 2349778
696 (-30000) 2197225
697 (-29000) 2055558
698 (-28000) 1923932
699 (-27000) 1801573
700 (-26000) 1687773
701 (-25000) 1581881
702 (-24000) 1483100
703 (-23000) 1391113
704 (-22000) 1305413
705 (-21000) 1225531
706 (-20000) 1151037
707 (-19000) 1081535
708 (-18000) 1016661
709 (-17000) 956080
710 (-16000) 899481
711 (-15000) 846579
712 (-14000) 797111
713 (-13000) 750834
714 (-12000) 707524
715 (-11000) 666972
716 (-10000) 628988
717 (-9000) 593342
718 (-8000) 559931
719 (-7000) 528602
720 (-6000) 499212
721 (-5000) 471632
722 (-4000) 445772
723 (-3000) 421480
724 (-2000) 398652
725 (-1000) 377193
726 0 357012
727 1000 338006
728 2000 320122
729 3000 303287
730 4000 287434
731 5000 272500
732 6000 258426
733 7000 245160
734 8000 232649
735 9000 220847
736 10000 209710
737 11000 199196
738 12000 189268
739 13000 179890
740 14000 171027
741 15000 162651
742 16000 154726
743 17000 147232
744 18000 140142
745 19000 133432
746 20000 127080
747 21000 121066
748 22000 115368
749 23000 109970
750 24000 104852
751 25000 100000
752 26000 95398
753 27000 91032
754 28000 86889
755 29000 82956
756 30000 79222
757 31000 75675
758 32000 72306
759 33000 69104
760 34000 66061
761 35000 63167
762 36000 60415
763 37000 57797
764 38000 55306
765 39000 52934
766 40000 50677
767 41000 48528
768 42000 46482
769 43000 44533
770 44000 42675
771 45000 40904
772 46000 39213
773 47000 37601
774 48000 36063
775 49000 34595
776 50000 33195
777 51000 31859
778 52000 30584
779 53000 29366
780 54000 28203
781 55000 27091
782 56000 26028
783 57000 25013
784 58000 24042
785 59000 23113
786 60000 22224
787 61000 21374
788 62000 20560
789 63000 19782
790 64000 19036
791 65000 18322
792 66000 17640
793 67000 16986
794 68000 16360
795 69000 15759
796 70000 15184
797 71000 14631
798 72000 14100
799 73000 13591
800 74000 13103
801 75000 12635
802 76000 12187
803 77000 11756
804 78000 11343
805 79000 10946
806 80000 10565
807 81000 10199
808 82000 9847
809 83000 9509
810 84000 9184
811 85000 8872
812 86000 8572
813 87000 8283
814 88000 8005
815 89000 7738
816 90000 7481
817 91000 7234
818 92000 6997
819 93000 6769
820 94000 6548
821 95000 6337
822 96000 6132
823 97000 5934
824 98000 5744
825 99000 5561
826 100000 5384
827 101000 5214
828 102000 5051
829 103000 4893
830 104000 4741
831 105000 4594
832 106000 4453
833 107000 4316
834 108000 4184
835 109000 4057
836 110000 3934
837 111000 3816
838 112000 3701
839 113000 3591
840 114000 3484
841 115000 3380
842 116000 3281
843 117000 3185
844 118000 3093
845 119000 3003
846 120000 2916
847 121000 2832
848 122000 2751
849 123000 2672
850 124000 2596
851 125000 2522>;
852 };
853
854 tboard_thermistor2: thermal-ntc2 {
855 compatible = "mediatek,mt6880-board-ntc";
856 #thermal-sensor-cells = <0>;
857 reg = <0 0x1001C0D8 0 0x4>; /* TIA DATA T1 */
858 pmic_auxadc = <&pmic_auxadc>;
859 temperature-lookup-table = <
860 (-40000) 4397119
861 (-39000) 4092874
862 (-38000) 3811717
863 (-37000) 3551749
864 (-36000) 3311236
865 (-35000) 3088599
866 (-34000) 2882396
867 (-33000) 2691310
868 (-32000) 2514137
869 (-31000) 2349778
870 (-30000) 2197225
871 (-29000) 2055558
872 (-28000) 1923932
873 (-27000) 1801573
874 (-26000) 1687773
875 (-25000) 1581881
876 (-24000) 1483100
877 (-23000) 1391113
878 (-22000) 1305413
879 (-21000) 1225531
880 (-20000) 1151037
881 (-19000) 1081535
882 (-18000) 1016661
883 (-17000) 956080
884 (-16000) 899481
885 (-15000) 846579
886 (-14000) 797111
887 (-13000) 750834
888 (-12000) 707524
889 (-11000) 666972
890 (-10000) 628988
891 (-9000) 593342
892 (-8000) 559931
893 (-7000) 528602
894 (-6000) 499212
895 (-5000) 471632
896 (-4000) 445772
897 (-3000) 421480
898 (-2000) 398652
899 (-1000) 377193
900 0 357012
901 1000 338006
902 2000 320122
903 3000 303287
904 4000 287434
905 5000 272500
906 6000 258426
907 7000 245160
908 8000 232649
909 9000 220847
910 10000 209710
911 11000 199196
912 12000 189268
913 13000 179890
914 14000 171027
915 15000 162651
916 16000 154726
917 17000 147232
918 18000 140142
919 19000 133432
920 20000 127080
921 21000 121066
922 22000 115368
923 23000 109970
924 24000 104852
925 25000 100000
926 26000 95398
927 27000 91032
928 28000 86889
929 29000 82956
930 30000 79222
931 31000 75675
932 32000 72306
933 33000 69104
934 34000 66061
935 35000 63167
936 36000 60415
937 37000 57797
938 38000 55306
939 39000 52934
940 40000 50677
941 41000 48528
942 42000 46482
943 43000 44533
944 44000 42675
945 45000 40904
946 46000 39213
947 47000 37601
948 48000 36063
949 49000 34595
950 50000 33195
951 51000 31859
952 52000 30584
953 53000 29366
954 54000 28203
955 55000 27091
956 56000 26028
957 57000 25013
958 58000 24042
959 59000 23113
960 60000 22224
961 61000 21374
962 62000 20560
963 63000 19782
964 64000 19036
965 65000 18322
966 66000 17640
967 67000 16986
968 68000 16360
969 69000 15759
970 70000 15184
971 71000 14631
972 72000 14100
973 73000 13591
974 74000 13103
975 75000 12635
976 76000 12187
977 77000 11756
978 78000 11343
979 79000 10946
980 80000 10565
981 81000 10199
982 82000 9847
983 83000 9509
984 84000 9184
985 85000 8872
986 86000 8572
987 87000 8283
988 88000 8005
989 89000 7738
990 90000 7481
991 91000 7234
992 92000 6997
993 93000 6769
994 94000 6548
995 95000 6337
996 96000 6132
997 97000 5934
998 98000 5744
999 99000 5561
1000 100000 5384
1001 101000 5214
1002 102000 5051
1003 103000 4893
1004 104000 4741
1005 105000 4594
1006 106000 4453
1007 107000 4316
1008 108000 4184
1009 109000 4057
1010 110000 3934
1011 111000 3816
1012 112000 3701
1013 113000 3591
1014 114000 3484
1015 115000 3380
1016 116000 3281
1017 117000 3185
1018 118000 3093
1019 119000 3003
1020 120000 2916
1021 121000 2832
1022 122000 2751
1023 123000 2672
1024 124000 2596
1025 125000 2522>;
1026 };
1027
1028 tboard_thermistor3: thermal-ntc3 {
1029 compatible = "mediatek,mt6880-board-ntc";
1030 #thermal-sensor-cells = <0>;
1031 reg = <0 0x1001C0DC 0 0x4>; /* TIA DATA T2 */
1032 pmic_auxadc = <&pmic_auxadc>;
1033 temperature-lookup-table = <
1034 (-40000) 4397119
1035 (-39000) 4092874
1036 (-38000) 3811717
1037 (-37000) 3551749
1038 (-36000) 3311236
1039 (-35000) 3088599
1040 (-34000) 2882396
1041 (-33000) 2691310
1042 (-32000) 2514137
1043 (-31000) 2349778
1044 (-30000) 2197225
1045 (-29000) 2055558
1046 (-28000) 1923932
1047 (-27000) 1801573
1048 (-26000) 1687773
1049 (-25000) 1581881
1050 (-24000) 1483100
1051 (-23000) 1391113
1052 (-22000) 1305413
1053 (-21000) 1225531
1054 (-20000) 1151037
1055 (-19000) 1081535
1056 (-18000) 1016661
1057 (-17000) 956080
1058 (-16000) 899481
1059 (-15000) 846579
1060 (-14000) 797111
1061 (-13000) 750834
1062 (-12000) 707524
1063 (-11000) 666972
1064 (-10000) 628988
1065 (-9000) 593342
1066 (-8000) 559931
1067 (-7000) 528602
1068 (-6000) 499212
1069 (-5000) 471632
1070 (-4000) 445772
1071 (-3000) 421480
1072 (-2000) 398652
1073 (-1000) 377193
1074 0 357012
1075 1000 338006
1076 2000 320122
1077 3000 303287
1078 4000 287434
1079 5000 272500
1080 6000 258426
1081 7000 245160
1082 8000 232649
1083 9000 220847
1084 10000 209710
1085 11000 199196
1086 12000 189268
1087 13000 179890
1088 14000 171027
1089 15000 162651
1090 16000 154726
1091 17000 147232
1092 18000 140142
1093 19000 133432
1094 20000 127080
1095 21000 121066
1096 22000 115368
1097 23000 109970
1098 24000 104852
1099 25000 100000
1100 26000 95398
1101 27000 91032
1102 28000 86889
1103 29000 82956
1104 30000 79222
1105 31000 75675
1106 32000 72306
1107 33000 69104
1108 34000 66061
1109 35000 63167
1110 36000 60415
1111 37000 57797
1112 38000 55306
1113 39000 52934
1114 40000 50677
1115 41000 48528
1116 42000 46482
1117 43000 44533
1118 44000 42675
1119 45000 40904
1120 46000 39213
1121 47000 37601
1122 48000 36063
1123 49000 34595
1124 50000 33195
1125 51000 31859
1126 52000 30584
1127 53000 29366
1128 54000 28203
1129 55000 27091
1130 56000 26028
1131 57000 25013
1132 58000 24042
1133 59000 23113
1134 60000 22224
1135 61000 21374
1136 62000 20560
1137 63000 19782
1138 64000 19036
1139 65000 18322
1140 66000 17640
1141 67000 16986
1142 68000 16360
1143 69000 15759
1144 70000 15184
1145 71000 14631
1146 72000 14100
1147 73000 13591
1148 74000 13103
1149 75000 12635
1150 76000 12187
1151 77000 11756
1152 78000 11343
1153 79000 10946
1154 80000 10565
1155 81000 10199
1156 82000 9847
1157 83000 9509
1158 84000 9184
1159 85000 8872
1160 86000 8572
1161 87000 8283
1162 88000 8005
1163 89000 7738
1164 90000 7481
1165 91000 7234
1166 92000 6997
1167 93000 6769
1168 94000 6548
1169 95000 6337
1170 96000 6132
1171 97000 5934
1172 98000 5744
1173 99000 5561
1174 100000 5384
1175 101000 5214
1176 102000 5051
1177 103000 4893
1178 104000 4741
1179 105000 4594
1180 106000 4453
1181 107000 4316
1182 108000 4184
1183 109000 4057
1184 110000 3934
1185 111000 3816
1186 112000 3701
1187 113000 3591
1188 114000 3484
1189 115000 3380
1190 116000 3281
1191 117000 3185
1192 118000 3093
1193 119000 3003
1194 120000 2916
1195 121000 2832
1196 122000 2751
1197 123000 2672
1198 124000 2596
1199 125000 2522>;
1200 };
1201
1202 tboard_thermistor4: thermal-ntc4 {
1203 compatible = "mediatek,mt6880-board-ntc";
1204 #thermal-sensor-cells = <0>;
1205 reg = <0 0x1001C0E0 0 0x4>; /* TIA DATA T3 */
1206 pmic_auxadc = <&pmic_auxadc>;
1207 temperature-lookup-table = <
1208 (-40000) 4397119
1209 (-39000) 4092874
1210 (-38000) 3811717
1211 (-37000) 3551749
1212 (-36000) 3311236
1213 (-35000) 3088599
1214 (-34000) 2882396
1215 (-33000) 2691310
1216 (-32000) 2514137
1217 (-31000) 2349778
1218 (-30000) 2197225
1219 (-29000) 2055558
1220 (-28000) 1923932
1221 (-27000) 1801573
1222 (-26000) 1687773
1223 (-25000) 1581881
1224 (-24000) 1483100
1225 (-23000) 1391113
1226 (-22000) 1305413
1227 (-21000) 1225531
1228 (-20000) 1151037
1229 (-19000) 1081535
1230 (-18000) 1016661
1231 (-17000) 956080
1232 (-16000) 899481
1233 (-15000) 846579
1234 (-14000) 797111
1235 (-13000) 750834
1236 (-12000) 707524
1237 (-11000) 666972
1238 (-10000) 628988
1239 (-9000) 593342
1240 (-8000) 559931
1241 (-7000) 528602
1242 (-6000) 499212
1243 (-5000) 471632
1244 (-4000) 445772
1245 (-3000) 421480
1246 (-2000) 398652
1247 (-1000) 377193
1248 0 357012
1249 1000 338006
1250 2000 320122
1251 3000 303287
1252 4000 287434
1253 5000 272500
1254 6000 258426
1255 7000 245160
1256 8000 232649
1257 9000 220847
1258 10000 209710
1259 11000 199196
1260 12000 189268
1261 13000 179890
1262 14000 171027
1263 15000 162651
1264 16000 154726
1265 17000 147232
1266 18000 140142
1267 19000 133432
1268 20000 127080
1269 21000 121066
1270 22000 115368
1271 23000 109970
1272 24000 104852
1273 25000 100000
1274 26000 95398
1275 27000 91032
1276 28000 86889
1277 29000 82956
1278 30000 79222
1279 31000 75675
1280 32000 72306
1281 33000 69104
1282 34000 66061
1283 35000 63167
1284 36000 60415
1285 37000 57797
1286 38000 55306
1287 39000 52934
1288 40000 50677
1289 41000 48528
1290 42000 46482
1291 43000 44533
1292 44000 42675
1293 45000 40904
1294 46000 39213
1295 47000 37601
1296 48000 36063
1297 49000 34595
1298 50000 33195
1299 51000 31859
1300 52000 30584
1301 53000 29366
1302 54000 28203
1303 55000 27091
1304 56000 26028
1305 57000 25013
1306 58000 24042
1307 59000 23113
1308 60000 22224
1309 61000 21374
1310 62000 20560
1311 63000 19782
1312 64000 19036
1313 65000 18322
1314 66000 17640
1315 67000 16986
1316 68000 16360
1317 69000 15759
1318 70000 15184
1319 71000 14631
1320 72000 14100
1321 73000 13591
1322 74000 13103
1323 75000 12635
1324 76000 12187
1325 77000 11756
1326 78000 11343
1327 79000 10946
1328 80000 10565
1329 81000 10199
1330 82000 9847
1331 83000 9509
1332 84000 9184
1333 85000 8872
1334 86000 8572
1335 87000 8283
1336 88000 8005
1337 89000 7738
1338 90000 7481
1339 91000 7234
1340 92000 6997
1341 93000 6769
1342 94000 6548
1343 95000 6337
1344 96000 6132
1345 97000 5934
1346 98000 5744
1347 99000 5561
1348 100000 5384
1349 101000 5214
1350 102000 5051
1351 103000 4893
1352 104000 4741
1353 105000 4594
1354 106000 4453
1355 107000 4316
1356 108000 4184
1357 109000 4057
1358 110000 3934
1359 111000 3816
1360 112000 3701
1361 113000 3591
1362 114000 3484
1363 115000 3380
1364 116000 3281
1365 117000 3185
1366 118000 3093
1367 119000 3003
1368 120000 2916
1369 121000 2832
1370 122000 2751
1371 123000 2672
1372 124000 2596
1373 125000 2522>;
1374 };
1375
1376 trm: thermal_risk_monitor {
1377 compatible = "mediatek,mt6880-trm";
1378 };
1379
1380 pmic_temp: pmic_temp {
1381 compatible = "mediatek,mt6330-pmic-temp";
1382 io-channels =
1383 <&pmic_auxadc AUXADC_CHIP_TEMP>;
1384 io-channel-names =
1385 "pmic_chip_temp";
1386
1387 #thermal-sensor-cells = <0>;
1388 nvmem-cells = <&thermal_efuse_data1>;
1389 nvmem-cell-names = "t_e_data1@6c";
1390 pmic_temp,cali_factor = <1681>;
1391 pmic_temp,iio_chan = <0>;
1392 };
1393
1394 pmic_vcore: pmic_vcore {
1395 compatible = "mediatek,mt6330-pmic-temp";
1396 io-channels =
1397 <&pmic_auxadc AUXADC_VCORE_TEMP>;
1398 io-channel-names =
1399 "pmic_buck1_temp";
1400
1401 #thermal-sensor-cells = <0>;
1402 nvmem-cells = <&thermal_efuse_data1>;
1403 nvmem-cell-names = "t_e_data1@6c";
1404 pmic_temp,cali_factor = <1863>;
1405 pmic_temp,iio_chan = <1>;
1406 };
1407
1408 pmic_vproc: pmic_vproc {
1409 compatible = "mediatek,mt6330-pmic-temp";
1410 io-channels =
1411 <&pmic_auxadc AUXADC_VPROC_TEMP>;
1412 io-channel-names =
1413 "pmic_buck2_temp";
1414 #thermal-sensor-cells = <0>;
1415 nvmem-cells = <&thermal_efuse_data1>;
1416 nvmem-cell-names = "t_e_data1@6c";
1417 pmic_temp,cali_factor = <1863>;
1418 pmic_temp,iio_chan = <2>;
1419 };
1420
1421 pmic_vgpu: pmic_vgpu {
1422 compatible = "mediatek,mt6330-pmic-temp";
1423 io-channels =
1424 <&pmic_auxadc AUXADC_VGPU_TEMP>;
1425 io-channel-names =
1426 "pmic_buck3_temp";
1427 #thermal-sensor-cells = <0>;
1428 nvmem-cells = <&thermal_efuse_data1>;
1429 nvmem-cell-names = "t_e_data1@6c";
1430 pmic_temp,cali_factor = <1863>;
1431 pmic_temp,iio_chan = <3>;
1432 };
1433
1434 md_rf_ic: md-rf-ic {
1435 compatible = "mediatek,md-rf";
1436 #thermal-sensor-cells = <0>;
1437 };
1438
1439 md_cooler_mutt: mutt {
1440 compatible = "mediatek,mt6297-md-cooler-mutt";
1441 mutt_pa1: mutt-pa1 {
1442 id = <0>;
1443 #cooling-cells = <2>;
1444 };
1445 mutt_pa1_no_ims: mutt-pa1-no-ims {
1446 id = <0>;
1447 #cooling-cells = <2>;
1448 };
1449 mutt_pa2: mutt-pa2 {
1450 id = <1>;
1451 #cooling-cells = <2>;
1452 };
1453 mutt_pa2_no_ims: mutt-pa2-no-ims {
1454 id = <1>;
1455 #cooling-cells = <2>;
1456 };
1457 };
1458 md_cooler_tx_pwr: tx-pwr {
1459 compatible = "mediatek,md-cooler-tx-pwr";
1460 tx_pwr_pa1: tx-pwr-pa1 {
1461 id = <0>;
1462 #cooling-cells = <2>;
1463 };
1464 tx_pwr_pa2: tx-pwr-pa2 {
1465 id = <1>;
1466 #cooling-cells = <2>;
1467 };
1468 };
1469 md_cooler_scg_off: scg-off {
1470 compatible = "mediatek,md-cooler-scg-off";
1471 scg_off_pa2: scg-off-pa2 {
1472 id = <1>;
1473 #cooling-cells = <2>;
1474 };
1475 };
1476
1477 thermal-zones {
1478 soc_max {
1479 polling-delay = <100>; /* milliseconds */
1480 polling-delay-passive = <50>; /* milliseconds */
1481 thermal-sensors = <&lvts 0>;
1482 sustainable-power = <1700>;
1483
1484 trips {
1485 threshold: trip-point@0 {
1486 temperature = <85000>;
1487 hysteresis = <2000>;
1488 type = "passive";
1489 };
1490
1491 ipa_target: trip-point@1 {
1492 temperature = <95000>;
1493 hysteresis = <2000>;
1494 type = "passive";
1495 };
1496
1497 soc_max_crit: soc_max_crit@0 {
1498 temperature = <115000>;
1499 hysteresis = <2000>;
1500 type = "critical";
1501 };
1502 };
1503
1504 cooling-maps {
1505 map0 {
1506 trip = <&ipa_target>;
1507 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1508 contribution = <1024>;
1509 };
1510
1511 map1 {
1512 trip = <&ipa_target>;
1513 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1514 contribution = <1024>;
1515 };
1516 };
1517 };
1518
1519 cpu_little0 {
1520 polling-delay = <0>; /* milliseconds */
1521 polling-delay-passive = <0>; /* milliseconds */
1522 thermal-sensors = <&lvts 1>;
1523 };
1524
1525 cpu_little1 {
1526 polling-delay = <0>; /* milliseconds */
1527 polling-delay-passive = <0>; /* milliseconds */
1528 thermal-sensors = <&lvts 2>;
1529 };
1530
1531 cpu_little2 {
1532 polling-delay = <0>; /* milliseconds */
1533 polling-delay-passive = <0>; /* milliseconds */
1534 thermal-sensors = <&lvts 3>;
1535 };
1536
1537 cpu_little3 {
1538 polling-delay = <0>; /* milliseconds */
1539 polling-delay-passive = <0>; /* milliseconds */
1540 thermal-sensors = <&lvts 4>;
1541 };
1542
1543 gpu0 {
1544 polling-delay = <0>; /* milliseconds */
1545 polling-delay-passive = <0>; /* milliseconds */
1546 thermal-sensors = <&lvts 5>;
1547 };
1548
1549 gpu1 {
1550 polling-delay = <0>; /* milliseconds */
1551 polling-delay-passive = <0>; /* milliseconds */
1552 thermal-sensors = <&lvts 6>;
1553 };
1554
1555 dramc {
1556 polling-delay = <0>; /* milliseconds */
1557 polling-delay-passive = <0>; /* milliseconds */
1558 thermal-sensors = <&lvts 7>;
1559 };
1560
1561 mmsys {
1562 polling-delay = <0>; /* milliseconds */
1563 polling-delay-passive = <0>; /* milliseconds */
1564 thermal-sensors = <&lvts 8>;
1565 };
1566
1567 md_5g {
1568 polling-delay = <0>; /* milliseconds */
1569 polling-delay-passive = <0>; /* milliseconds */
1570 thermal-sensors = <&lvts 9>;
1571 };
1572
1573 md_4g {
1574 polling-delay = <0>; /* milliseconds */
1575 polling-delay-passive = <0>; /* milliseconds */
1576 thermal-sensors = <&lvts 10>;
1577 };
1578
1579 md_3g {
1580 polling-delay = <0>; /* milliseconds */
1581 polling-delay-passive = <0>; /* milliseconds */
1582 thermal-sensors = <&lvts 11>;
1583 };
1584
1585 soc_dram_ntc {
1586 polling-delay = <1000>; /* milliseconds */
1587 polling-delay-passive = <1000>; /* milliseconds */
1588 thermal-sensors = <&tboard_thermistor1>;
1589
1590 trips {
1591 soc_dram_ntc_crit: soc_dram_ntc_crit@0 {
1592 temperature = <100000>;
1593 hysteresis = <2000>;
1594 type = "critical";
1595 };
1596 };
1597 };
1598
1599 nrpa_ntc {
1600 polling-delay = <1000>; /* milliseconds */
1601 polling-delay-passive = <1000>; /* milliseconds */
1602 thermal-sensors = <&tboard_thermistor2>;
1603
1604 trips {
1605 nrpa_ntc_target: nrpa_ntc_trip@0 {
1606 temperature = <82000>;
1607 hysteresis = <2000>;
1608 type = "passive";
1609 };
1610 nrpa_ntc_no_ims: nrpa_ntc_trip@1 {
1611 temperature = <90000>;
1612 hysteresis = <2000>;
1613 type = "passive";
1614 };
1615 };
1616 cooling-maps {
1617 map0 {
1618 trip = <&nrpa_ntc_target>;
1619 cooling-device = <&mutt_pa2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1620 };
1621 map1 {
1622 trip = <&nrpa_ntc_no_ims>;
1623 cooling-device = <&mutt_pa2_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1624 };
1625 };
1626 };
1627
1628 ltepa_ntc {
1629 polling-delay = <1000>; /* milliseconds */
1630 polling-delay-passive = <1000>; /* milliseconds */
1631 thermal-sensors = <&tboard_thermistor3>;
1632
1633 trips {
1634 ltepa_ntc_target: ltepa_ntc_trip@0 {
1635 temperature = <82000>;
1636 hysteresis = <2000>;
1637 type = "passive";
1638 };
1639 ltepa_ntc_no_ims: ltepa_ntc_trip@1 {
1640 temperature = <90000>;
1641 hysteresis = <2000>;
1642 type = "passive";
1643 };
1644 ltepa_ntc_crit: ltepa_ntc_trip@2 {
1645 temperature = <100000>;
1646 hysteresis = <2000>;
1647 type = "critical";
1648 };
1649 };
1650 cooling-maps {
1651 map0 {
1652 trip = <&ltepa_ntc_target>;
1653 cooling-device = <&mutt_pa1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1654 };
1655 map1 {
1656 trip = <&ltepa_ntc_no_ims>;
1657 cooling-device = <&mutt_pa1_no_ims THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1658 };
1659 };
1660 };
1661
1662 rf_ntc {
1663 polling-delay = <1000>; /* milliseconds */
1664 polling-delay-passive = <1000>; /* milliseconds */
1665 thermal-sensors = <&tboard_thermistor4>;
1666
1667 trips {
1668 rf_ntc_crit: rf_ntc_crit@0 {
1669 temperature = <100000>;
1670 hysteresis = <2000>;
1671 type = "critical";
1672 };
1673 };
1674 };
1675
1676 pmic {
1677 polling-delay = <1000>; /* milliseconds */
1678 polling-delay-passive = <1000>; /* milliseconds */
1679 thermal-sensors = <&pmic_temp>;
1680
1681 trips {
1682 pmic_temp_crit: pmic_temp_crit@0 {
1683 temperature = <125000>;
1684 hysteresis = <2000>;
1685 type = "critical";
1686 };
1687 };
1688 };
1689 pmic_vcore {
1690 polling-delay = <0>; /* milliseconds */
1691 polling-delay-passive = <0>; /* milliseconds */
1692 thermal-sensors = <&pmic_vcore>;
1693 };
1694 pmic_vproc {
1695 polling-delay = <0>; /* milliseconds */
1696 polling-delay-passive = <0>; /* milliseconds */
1697 thermal-sensors = <&pmic_vproc>;
1698 };
1699 pmic_vgpu {
1700 polling-delay = <0>; /* milliseconds */
1701 polling-delay-passive = <0>; /* milliseconds */
1702 thermal-sensors = <&pmic_vgpu>;
1703 };
1704
1705 md_rf {
1706 polling-delay = <1000>; /* milliseconds */
1707 polling-delay-passive = <1000>; /* milliseconds */
1708 thermal-sensors = <&md_rf_ic>;
1709
1710 trips {
1711 md_rf_crit: md_rf_crit@0 {
1712 temperature = <117000>;
1713 hysteresis = <2000>;
1714 type = "critical";
1715 };
1716 };
1717 };
1718 conn_gps {
1719 polling-delay = <1000>; /* milliseconds */
1720 polling-delay-passive = <1000>; /* milliseconds */
1721 thermal-sensors = <&consys>;
1722
1723 trips {
1724 consys_max_crit: consys_max_crit@0 {
1725 temperature = <117000>;
1726 hysteresis = <2000>;
1727 type = "critical";
1728 };
1729 };
1730 };
1731 };
1732
1733 chipid@08000000 {
1734 compatible = "mediatek,chipid";
1735 reg = <0 0x08000000 0 0x0004>,
1736 <0 0x08000004 0 0x0004>,
1737 <0 0x08000008 0 0x0004>,
1738 <0 0x0800000c 0 0x0004>;
1739 };
1740
1741 dbgtop@1000d000 {
1742 compatible = "mediatek,dbgtop";
1743 reg = <0 0x1000d000 0 0x1000>;
1744 };
1745
1746 mcupm@0C540000 {
1747 compatible = "mediatek,mcupm";
1748 reg =<0 0x0C540000 0 0x22000>,
1749
1750 <0 0x0c55fb00 0 0xa0>,
1751 <0 0x0c562004 0 0x4>,
1752 <0 0x0c562018 0 0x4>,
1753 <0 0x0c562000 0 0x4>,
1754 <0 0x0c562010 0 0x4>,
1755
1756 <0 0x0c55fba0 0 0xa0>,
1757 <0 0x0c562004 0 0x4>,
1758 <0 0x0c562018 0 0x4>,
1759 <0 0x0c562000 0 0x4>,
1760 <0 0x0c562010 0 0x4>,
1761
1762 <0 0x0c55fc40 0 0xa0>,
1763 <0 0x0c562004 0 0x4>,
1764 <0 0x0c562018 0 0x4>,
1765 <0 0x0c562000 0 0x4>,
1766 <0 0x0c562010 0 0x4>,
1767
1768 <0 0x0c55fce0 0 0xa0>,
1769 <0 0x0c562004 0 0x4>,
1770 <0 0x0c562018 0 0x4>,
1771 <0 0x0c562000 0 0x4>,
1772 <0 0x0c562010 0 0x4>,
1773
1774 <0 0x0c55fd80 0 0xa0>,
1775 <0 0x0c562004 0 0x4>,
1776 <0 0x0c562018 0 0x4>,
1777 <0 0x0c562000 0 0x4>,
1778 <0 0x0c562010 0 0x4>,
1779
1780 <0 0x0c55fe20 0 0xa0>,
1781 <0 0x0c562004 0 0x4>,
1782 <0 0x0c562018 0 0x4>,
1783 <0 0x0c562000 0 0x4>,
1784 <0 0x0c562010 0 0x4>,
1785
1786 <0 0x0c55fec0 0 0xa0>,
1787 <0 0x0c562004 0 0x4>,
1788 <0 0x0c562018 0 0x4>,
1789 <0 0x0c562000 0 0x4>,
1790 <0 0x0c562010 0 0x4>,
1791
1792 <0 0x0c55ff60 0 0xa0>,
1793 <0 0x0c562004 0 0x4>,
1794 <0 0x0c562018 0 0x4>,
1795 <0 0x0c562000 0 0x4>,
1796 <0 0x0c562010 0 0x4>;
1797
1798 reg-names = "mcupm_base",
1799
1800 "mbox0_base",
1801 "mbox0_set",
1802 "mbox0_clr",
1803 "mbox0_send",
1804 "mbox0_recv",
1805
1806 "mbox1_base",
1807 "mbox1_set",
1808 "mbox1_clr",
1809 "mbox1_send",
1810 "mbox1_recv",
1811
1812 "mbox2_base",
1813 "mbox2_set",
1814 "mbox2_clr",
1815 "mbox2_send",
1816 "mbox2_recv",
1817
1818 "mbox3_base",
1819 "mbox3_set",
1820 "mbox3_clr",
1821 "mbox3_send",
1822 "mbox3_recv",
1823
1824 "mbox4_base",
1825 "mbox4_set",
1826 "mbox4_clr",
1827 "mbox4_send",
1828 "mbox4_recv",
1829
1830 "mbox5_base",
1831 "mbox5_set",
1832 "mbox5_clr",
1833 "mbox5_send",
1834 "mbox5_recv",
1835
1836 "mbox6_base",
1837 "mbox6_set",
1838 "mbox6_clr",
1839 "mbox6_send",
1840 "mbox6_recv",
1841
1842 "mbox7_base",
1843 "mbox7_set",
1844 "mbox7_clr",
1845 "mbox7_send",
1846 "mbox7_recv";
1847
1848 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1856
1857 interrupt-names = "mbox0",
1858 "mbox1",
1859 "mbox2",
1860 "mbox3",
1861 "mbox4",
1862 "mbox5",
1863 "mbox6",
1864 "mbox7";
1865 };
1866
1867 topckgen: topckgen@10000000 {
1868 compatible = "mediatek,topckgen", "syscon";
1869 reg = <0 0x10000000 0 0x1000>;
1870 };
1871
1872 dcm: dcm@10001000 {
1873 compatible = "mediatek,mt6880-dcm";
1874 reg = <0 0x10001000 0 0x1000>,
1875 <0 0x10002000 0 0x1000>,
1876 <0 0x10022000 0 0x1000>,
1877 <0 0x10219000 0 0x1000>,
1878 <0 0x10230000 0 0x2000>,
1879 <0 0x10235000 0 0x1000>,
1880 <0 0x10238000 0 0x1000>,
1881 <0 0x10240000 0 0x2000>,
1882 <0 0x10248000 0 0x1000>,
1883 <0 0xc538000 0 0x5000>,
1884 <0 0xc53a800 0 0x1000>;
1885 reg-names = "infracfg_ao",
1886 "infracfg_ao_mem",
1887 "infra_ao_bcrm",
1888 "emi",
1889 "dramc_ch0_top0",
1890 "chn0_emi",
1891 "dramc_ch0_top5",
1892 "dramc_ch1_top0",
1893 "dramc_ch1_top5",
1894 "mp_cpusys_top",
1895 "cpccfg_reg";
1896 };
1897
1898 infracfg_ao: infracfg_ao@10001000 {
1899 compatible = "mediatek,infracfg_ao", "syscon", "simple-mfd";
1900 reg = <0 0x10001000 0 0x1000>;
1901 infracfg_rst: reset-controller {
1902 compatible = "ti,syscon-reset";
1903 #reset-cells = <1>;
1904
1905 ti,reset-bits = <
1906 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: lvts_ap */
1907 0x730 12 0x734 12 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: lvts_mcu */
1908 >;
1909 };
1910 };
1911
1912 infracfg_ao_mem@10002000 {
1913 compatible = "mediatek,infracfg_ao_mem";
1914 reg = <0 0x10002000 0 0x1000>;
1915 };
1916
1917 pericfg@10003000 {
1918 compatible = "mediatek,pericfg";
1919 reg = <0 0x10003000 0 0x1000>;
1920 };
1921
1922 gpio_usage_mapping: gpio_usage_mapping {
1923 compatible = "mediatek,gpio_usage_mapping";
1924 };
1925
1926 gpio: gpio@10005000 {
1927 compatible = "mediatek,gpio";
1928 reg = <0 0x10005000 0 0x1000>;
1929 };
1930
1931 pio: pinctrl@10005000 {
1932 compatible = "mediatek,mt2735-pinctrl";
1933 reg = <0 0x10005000 0 0x1000>,
1934 <0 0x11c10000 0 0x1000>,
1935 <0 0x11c20000 0 0x1000>,
1936 <0 0x11d00000 0 0x1000>,
1937 <0 0x11d10000 0 0x1000>,
1938 <0 0x11d20000 0 0x1000>,
1939 <0 0x11e00000 0 0x1000>,
1940 <0 0x11f00000 0 0x1000>,
1941 <0 0x1000b000 0 0x1000>;
1942 reg-names = "gpio", "iocfg_rm",
1943 "iocfg_rb", "iocfg_bl",
1944 "iocfg_bm", "iocfg_br",
1945 "iocfg_lt", "iocfg_tl",
1946 "eint";
1947 gpio-controller;
1948 #gpio-cells = <2>;
1949 gpio-ranges = <&pio 0 0 235>;
1950 interrupt-controller;
1951 #interrupt-cells = <2>;
1952 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1953 interrupt-parent = <&gic>;
1954 };
1955
1956 sleep: sleep@10006000 {
1957 compatible = "mediatek,sleep", "syscon";
1958 reg = <0 0x10006000 0 0x1000>;
1959 };
1960
1961 spmtwam: spmtwam@10006000 {
1962 compatible = "mediatek,spmtwam";
1963 reg = <0 0x10006000 0 0x1000>;
1964 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1965 spm_twam_con = <0xa0>;
1966 spm_twam_window_len = <0xa4>;
1967 spm_twam_idle_sel = <0xa8>;
1968 spm_irq_mask = <0xb4>;
1969 spm_irq_sta = <0x128>;
1970 spm_twam_last_sta0 = <0x1d0>;
1971 spm_twam_last_sta1 = <0x1d4>;
1972 spm_twam_last_sta2 = <0x1d8>;
1973 spm_twam_last_sta3 = <0x1dc>;
1974 };
1975
1976 srclken: srclken@10006500 {
1977 compatible = "mediatek,srclken";
1978 reg = <0 0x10006500 0 0x1000>,
1979 <0 0x105c4000 0 0x1000>,
1980 <0 0x10005000 0 0x1000>;
1981 reg-names = "srclken", "scpdvfs", "gpio";
1982 srclken-mode = "bringup";
1983
1984 srclken-rst-cfg = <0x0>;
1985 srclken-central-cfg = <0x4 0x8 0x1C>;
1986 srclken-cmd-cfg = <0xC>;
1987 srclken-pmic-cfg = <0x10 0x14>;
1988 srclken-dcxo-fpm-cfg = <0x18>;
1989 srclken-subsys-cfg = <0x20>;
1990 srclken-misc-cfg = <0xB4>;
1991 srclken-spm-cfg = <0xB8>;
1992 srclken-subsys-if-cfg = <0xBC>;
1993 srclken-fsm-sta = <0x60>;
1994 srclken-cmd-sta = <0x64 0x68>;
1995 srclken-spi-sta = <0x6C>;
1996 srclken-pipo-sta = <0x70>;
1997 srclken-subsys-sta = <0x80>;
1998 srclken-dbg-trace-sta = <0xC0 0xC4>;
1999
2000 srclken-scp-enable = "n";
2001 scp-vreq-cfg = <0x54>;
2002 scp-rc-vreq-bit = <27 28>;
2003
2004 srclken-gpio-enable = "n";
2005 gpio-dir-cfg = <0x0>;
2006 gpio-dout-cfg = <0x100>;
2007 gpio-pull-bit = <6>;
2008 };
2009
2010 watchdog: watchdog@10007000 {
2011 compatible = "mediatek,mt2735-wdt";
2012 reg = <0 0x10007000 0 0x1000>;
2013 };
2014
2015 apxgpt@10008000 {
2016 compatible = "mediatek,apxgpt";
2017 reg = <0 0x10008000 0 0x1000>;
2018 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
2019 };
2020
2021 sej@1000a000 {
2022 compatible = "mediatek,sej";
2023 reg = <0 0x1000a000 0 0x1000>;
2024 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
2025 };
2026
2027 apmixed: apmixed@1000c000 {
2028 compatible = "mediatek,apmixed";
2029 reg = <0 0x1000c000 0 0xe00>;
2030 };
2031
2032 fhctl@1000ce00 {
2033 compatible = "mediatek,mt6880-fhctl";
2034 reg = <0 0x1000ce00 0 0x200>;
2035 mediatek,apmixed = <&apmixed>;
2036
2037 armpll_ll {
2038 mediatek,fh-id = <0>;
2039 mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_LL>;
2040 mediatek,fh-cpu-pll;
2041 };
2042
2043 mainpll {
2044 mediatek,fh-id = <1>;
2045 mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
2046 };
2047
2048 mpll {
2049 mediatek,fh-id = <2>;
2050 mediatek,fh-pll-id = <CLK_APMIXED_MPLL>;
2051 };
2052
2053 msdcpll {
2054 mediatek,fh-id = <4>;
2055 mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
2056 };
2057
2058 mfgpll {
2059 mediatek,fh-id = <5>;
2060 mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
2061 };
2062
2063 mmpll {
2064 mediatek,fh-id = <6>;
2065 mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
2066 };
2067 };
2068
2069 pwrap@1000d000 {
2070 compatible = "mediatek,pwrap";
2071 reg = <0 0x1000d000 0 0x1000>;
2072 };
2073
2074 keypad:kp@10010000 {
2075 compatible = "mediatek,kp";
2076 reg = <0 0x10010000 0 0x1000>;
2077 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
2078 clocks = <&clk26m>;
2079 clock-names = "kpd";
2080 };
2081
2082 gpio-keys {
2083 compatible = "gpio-keys";
2084
2085 button0 {
2086 label = "Modem RF";
2087 gpios = <&pio 6 GPIO_ACTIVE_LOW>;
2088 linux,code = <KEY_PHONE>;
2089 };
2090
2091 button1 {
2092 label = "GPS";
2093 gpios = <&pio 7 GPIO_ACTIVE_LOW>;
2094 linux,code = <246>;
2095 };
2096/*
2097 button2 {
2098 label = "Factory Mode";
2099 gpios = <&pio 112 GPIO_ACTIVE_LOW>;
2100 linux,code = <112>;
2101 };
2102
2103 button3 {
2104 label = "WIFI";
2105 gpios = <&pio 114 GPIO_ACTIVE_LOW>;
2106 linux,code = <114>;
2107 };
2108
2109 button4 {
2110 label = "WPS";
2111 gpios = <&pio 115 GPIO_ACTIVE_LOW>;
2112 linux,code = <115>;
2113 };
2114*/
2115 };
2116
2117 topmisc@10011000 {
2118 compatible = "mediatek,topmisc";
2119 reg = <0 0x10011000 0 0x1000>;
2120 };
2121
2122 dvfsrc: dvfsrc@10012000 {
2123 compatible = "mediatek,mt6890-dvfsrc";
2124 reg = <0 0x10012000 0 0x1000>,
2125 <0 0x10006000 0 0x1000>;
2126 reg-names = "dvfsrc", "spm";
2127 #interconnect-cells = <1>;
2128 dvfsrc_vcore: dvfsrc-vcore {
2129 regulator-name = "dvfsrc-vcore";
2130 regulator-min-microvolt = <550000>;
2131 regulator-max-microvolt = <750000>;
2132 regulator-always-on;
2133 };
2134
2135 dvfsrc_freq_opp6: opp6 {
2136 opp-peak-KBps = <0>;
2137 };
2138 dvfsrc_freq_opp5: opp5 {
2139 opp-peak-KBps = <2500000>;
2140 };
2141 dvfsrc_freq_opp4: opp4 {
2142 opp-peak-KBps = <3800000>;
2143 };
2144 dvfsrc_freq_opp3: opp3 {
2145 opp-peak-KBps = <5100000>;
2146 };
2147 dvfsrc_freq_opp2: opp2 {
2148 opp-peak-KBps = <5900000>;
2149 };
2150 dvfsrc_freq_opp1: opp1 {
2151 opp-peak-KBps = <7600000>;
2152 };
2153 dvfsrc_freq_opp0: opp0 {
2154 opp-peak-KBps = <10200000>;
2155 };
2156
2157 dvfsrc-helper {
2158 compatible = "mediatek,dvfsrc-helper";
2159 vcore-supply = <&mt6330_vcore_buck_reg>;
2160 rc-vcore-supply = <&dvfsrc_vcore>;
2161 interconnects = <&dvfsrc MT6873_MASTER_DBGIF &dvfsrc MT6873_SLAVE_DDR_EMI>;
2162 interconnect-names = "icc-perf-bw";
2163 required-opps = <&dvfsrc_freq_opp0>,
2164 <&dvfsrc_freq_opp1>,
2165 <&dvfsrc_freq_opp2>,
2166 <&dvfsrc_freq_opp3>,
2167 <&dvfsrc_freq_opp4>,
2168 <&dvfsrc_freq_opp5>,
2169 <&dvfsrc_freq_opp6>;
2170 };
2171
2172 dvfsrc-met {
2173 compatible = "mediatek,dvfsrc-met";
2174 };
2175 };
2176
2177 mbist_ao@10013000 {
2178 compatible = "mediatek,mbist_ao";
2179 reg = <0 0x10013000 0 0x1000>;
2180 };
2181
2182 dpmaif_ao@10014000 {
2183 compatible = "mediatek,dpmaif_ao";
2184 reg = <0 0x10014000 0 0x1000>;
2185 };
2186
2187 aes_top0@10016000 {
2188 compatible = "mediatek,aes_top0";
2189 reg = <0 0x10016000 0 0x1000>;
2190 };
2191
2192 timer: timer {
2193 compatible = "arm,armv8-timer";
2194 interrupt-parent = <&gic>;
2195 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
2196 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
2197 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
2198 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
2199 clock-frequency = <13000000>;
2200 };
2201
2202 sys_timer@10017000 {
2203 compatible = "mediatek,sys_timer",
2204 "mediatek,mt6765-timer";
2205 reg = <0 0x10017000 0 0x1000>;
2206 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&clk13m>;
2208 };
2209
2210 modem_temp_share@10018000 {
2211 compatible = "mediatek,modem_temp_share";
2212 reg = <0 0x10018000 0 0x1000>;
2213 };
2214
2215 security_ao@1001a000 {
2216 compatible = "mediatek,security_ao";
2217 reg = <0 0x1001a000 0 0x1000>;
2218 };
2219
2220 topckgen_ao@1001b000 {
2221 compatible = "mediatek,topckgen_ao";
2222 reg = <0 0x1001b000 0 0x1000>;
2223 };
2224
2225 devapc_ao_mm@1001c000 {
2226 compatible = "mediatek,devapc_ao_mm";
2227 reg = <0 0x1001c000 0 0x1000>;
2228 };
2229
2230 sleep_sram@1001e000 {
2231 compatible = "mediatek,sleep_sram";
2232 reg = <0 0x1001e000 0 0x4000>;
2233 };
2234
2235 bcrm_ao_peri@10022000 {
2236 compatible = "mediatek,bcrm_ao_peri";
2237 reg = <0 0x10022000 0 0x1000>;
2238 };
2239
2240 debug_ao_peri@10023000 {
2241 compatible = "mediatek,debug_ao_peri";
2242 reg = <0 0x10023000 0 0x1000>;
2243 };
2244
2245 mhccif: mhccif@10024000 {
2246 compatible = "mediatek,mt6880-mhccif";
2247 #interrupt-cells = <3>;
2248 interrupt-controller;
2249 reg = <0 0x10024000 0 0x1000>,
2250 <0 0x10025000 0 0x1000>;
2251 reg-names = "mhccif_rc", "mhccif_ep";
2252 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
2253 status = "disabled";
2254 };
2255
2256 spmi_bus: spmi@10026000 {
2257 compatible = "mediatek,mt6880-pmif-m", "syscon";
2258 reg = <0 0x10026000 0 0x0008F0>,
2259 <0 0x10029000 0 0x000110>;
2260 reg-names = "pmif", "spmimst";
2261 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
2262 <&pio 216 IRQ_TYPE_LEVEL_HIGH>;
2263 interrupt-names = "pmif_irq", "rcs_irq";
2264 interrupt-controller;
2265 #interrupt-cells = <1>;
2266 irq_event_en = <0x0 0x00180000 0x0 0x0 0x0>;
2267 clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
2268 <&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
2269 <&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
2270 <&topckgen_clk CLK_TOP_OSC_D10>,
2271 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2272 <&topckgen_clk CLK_TOP_SPMI_M_MST_SEL>,
2273 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2274 <&topckgen_clk CLK_TOP_OSC_D10>;
2275 clock-names = "pmif_sys_ck",
2276 "pmif_tmr_ck",
2277 "pmif_clk_mux",
2278 "pmif_clk_osc_d10",
2279 "pmif_clk26m",
2280 "spmimst_clk_mux",
2281 "spmimst_clk26m",
2282 "spmimst_clk_osc_d10";
2283 swinf_ch_start = <6>;
2284 ap_swinf_no = <2>;
2285 grpid = <0xB>;
2286 #address-cells = <2>;
2287 #size-cells = <0>;
2288 };
2289
2290 spmi_p_bus: spmi_p@10027000 {
2291 compatible = "mediatek,mt6880-pmif-p";
2292 reg = <0 0x10027000 0 0x0008F0>,
2293 <0 0x10028000 0 0x000110>;
2294 reg-names = "pmif", "spmimst";
2295 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2296 interrupt-names = "pmif_irq";
2297 irq_event_en = <0x0 0x0 0x0 0x0 0x0>;
2298 clocks = <&infracfg_ao_clk CLK_IFRAO_PMIC_AP_SET>,
2299 <&infracfg_ao_clk CLK_IFRAO_PMIC_TMR_SET>,
2300 <&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
2301 <&topckgen_clk CLK_TOP_OSC_D10>,
2302 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2303 <&topckgen_clk CLK_TOP_SPMI_P_MST_SEL>,
2304 <&topckgen_clk CLK_TOP_TCK_26M_MX9>,
2305 <&topckgen_clk CLK_TOP_MAINPLL_D7_D8>;
2306 clock-names = "pmif_sys_ck",
2307 "pmif_tmr_ck",
2308 "pmif_clk_mux",
2309 "pmif_clk_osc_d10",
2310 "pmif_clk26m",
2311 "spmimst_clk_mux",
2312 "spmimst_clk26m",
2313 "spmimst_clk_mainpll_d7_d8";
2314 swinf_ch_start = <6>;
2315 ap_swinf_no = <2>;
2316 grpid = <0xB>;
2317 #address-cells = <2>;
2318 #size-cells = <0>;
2319 };
2320
2321 /* ATF logger */
2322 atf_logger {
2323 compatible = "mediatek,atf_logger";
2324 };
2325
2326 bcrm_peri_ao@1002a000 {
2327 compatible = "mediatek,bcrm_peri_ao";
2328 reg = <0 0x1002a000 0 0x1000>;
2329 };
2330
2331 debug_ao_peri@1002b000 {
2332 compatible = "mediatek,debug_ao_peri";
2333 reg = <0 0x1002b000 0 0x1000>;
2334 };
2335
2336 bcrm_peri_ao2@1002d000 {
2337 compatible = "mediatek,bcrm_peri_ao2";
2338 reg = <0 0x1002d000 0 0x1000>;
2339 };
2340
2341 debug_ao_peri2@1002e000 {
2342 compatible = "mediatek,debug_ao_peri2";
2343 reg = <0 0x1002e000 0 0x1000>;
2344 };
2345
2346 devapc_ao_infra@10030000 {
2347 compatible = "mediatek,devapc_ao_infra";
2348 reg = <0 0x10030000 0 0x4000>;
2349 };
2350
2351 devapc_ao_peri@10034000 {
2352 compatible = "mediatek,devapc_ao_peri";
2353 reg = <0 0x10034000 0 0x4000>;
2354 };
2355
2356 devapc_ao_peri2@10038000 {
2357 compatible = "mediatek,devapc_ao_peri2";
2358 reg = <0 0x10038000 0 0x4000>;
2359 };
2360
2361 devapc_ao_peri_par@1003c000 {
2362 compatible = "mediatek,devapc_ao_peri_par";
2363 reg = <0 0x1003c000 0 0x4000>;
2364 };
2365
2366 debug_ao_peri_par@10040000 {
2367 compatible = "mediatek,debug_ao_peri_par";
2368 reg = <0 0x10040000 0 0x1000>;
2369 };
2370
2371 bcrm_peri_par_ao@10041000 {
2372 compatible = "mediatek,bcrm_peri_par_ao";
2373 reg = <0 0x10041000 0 0x1000>;
2374 };
2375
2376 debug_ao_fmem@10042000 {
2377 compatible = "mediatek,debug_ao_fmem";
2378 reg = <0 0x10042000 0 0x1000>;
2379 };
2380
2381 bcrm_fmem_ao@10043000 {
2382 compatible = "mediatek,bcrm_fmem_ao";
2383 reg = <0 0x10043000 0 0x1000>;
2384 };
2385
2386 devapc_ao_fmem@10044000 {
2387 compatible = "mediatek,devapc_ao_fmem";
2388 reg = <0 0x10044000 0 0x4000>;
2389 };
2390
2391 pwm@10048000 {
2392 compatible = "mediatek,mt6880-pwm";
2393 reg = <0 0x10048000 0 0x1000>;
2394 #pwm-cells = <2>;
2395 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
2396
2397 clocks = <&topckgen_clk CLK_TOP_PWM_SEL>,
2398 <&infracfg_ao_clk CLK_IFRAO_PWM>,
2399 <&infracfg_ao_clk CLK_IFRAO_PWM1>,
2400 <&infracfg_ao_clk CLK_IFRAO_PWM2>,
2401 <&infracfg_ao_clk CLK_IFRAO_PWM3>,
2402 <&infracfg_ao_clk CLK_IFRAO_PWM4>,
2403 <&infracfg_ao_clk CLK_IFRAO_PWM5>,
2404 <&infracfg_ao_clk CLK_IFRAO_PWM6>,
2405 <&infracfg_ao_clk CLK_IFRAO_PWM7>;
2406 clock-names = "top",
2407 "main",
2408 "pwm1",
2409 "pwm2",
2410 "pwm3",
2411 "pwm4",
2412 "pwm5",
2413 "pwm6",
2414 "pwm7";
2415 };
2416
2417 sgmii0@10060000 {
2418 compatible = "mediatek,sgmii0";
2419 reg = <0 0x10060000 0 0x8000>;
2420 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
2421 };
2422
2423 sgmii1@10070000 {
2424 compatible = "mediatek,sgmii1";
2425 reg = <0 0x10070000 0 0x8000>;
2426 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
2427 };
2428
2429 sys_cirq@10204000 {
2430 compatible = "mediatek,sys_cirq";
2431 reg = <0 0x10204000 0 0x1000>;
2432 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
2433 };
2434
2435 devapc@10207000 {
2436 compatible = "mediatek,mt6880-devapc";
2437 reg = <0 0x10207000 0 0x1000>,
2438 <0 0x10274000 0 0x1000>,
2439 <0 0x10275000 0 0x1000>,
2440 <0 0x11020000 0 0x1000>,
2441 <0 0x10030000 0 0x1000>,
2442 <0 0x1020e000 0 0x1000>,
2443 <0 0x10033000 0 0x1000>;
2444 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2445 clocks = <&infracfg_ao_clk CLK_IFRAO_DEVICE_APC>;
2446 clock-names = "devapc-infra-clock";
2447 };
2448
2449 hwrng: hwrng {
2450 compatible = "mediatek,mt67xx-rng";
2451 };
2452
2453 bus_dbg@10208000 {
2454 compatible = "mediatek,bus_dbg-v2";
2455 reg = <0 0x10208000 0 0x1000>,
2456 <0 0x10001000 0 0x1000>;
2457 mediatek,bus_dbg_con_offset = <0x2fc>;
2458 interrupt = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
2459 };
2460
2461 ap_ccif0@10209000 {
2462 compatible = "mediatek,ap_ccif0";
2463 reg = <0 0x10209000 0 0x1000>;
2464 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
2465 };
2466
2467 md_ccif0@1020a000 {
2468 compatible = "mediatek,md_ccif0";
2469 reg = <0 0x1020a000 0 0x1000>;
2470 };
2471
2472 ap_ccif1@1020b000 {
2473 compatible = "mediatek,ap_ccif1";
2474 reg = <0 0x1020b000 0 0x1000>;
2475 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
2476 };
2477
2478 md_ccif1@1020c000 {
2479 compatible = "mediatek,md_ccif1";
2480 reg = <0 0x1020c000 0 0x1000>;
2481 };
2482
2483 infra_mbist@1020d000 {
2484 compatible = "mediatek,infra_mbist";
2485 reg = <0 0x1020d000 0 0x1000>;
2486 };
2487
2488 infracfg@1020e000 {
2489 compatible = "mediatek,infracfg";
2490 reg = <0 0x1020e000 0 0x1000>;
2491 };
2492
2493 trng@1020f000 {
2494 compatible = "mediatek,trng";
2495 reg = <0 0x1020f000 0 0x1000>;
2496 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
2497 };
2498
2499 dxcc_sec@10210000 {
2500 compatible = "mediatek,dxcc_sec";
2501 reg = <0 0x10210000 0 0x1000>;
2502 };
2503
2504 cq_dma@10212000 {
2505 compatible = "mediatek,cq_dma";
2506 reg = <0 0x10212000 0 0x1000>;
2507 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2508 };
2509
2510 md2md_md2_ccif0@10213000 {
2511 compatible = "mediatek,md2md_md2_ccif0";
2512 reg = <0 0x10213000 0 0x1000>;
2513 };
2514
2515 sramrom@10214000 {
2516 compatible = "mediatek,sramrom";
2517 reg = <0 0x10214000 0 0x1000>;
2518 };
2519
2520 bcrm_infra@10215000 {
2521 compatible = "mediatek,bcrm_infra";
2522 reg = <0 0x10215000 0 0x1000>;
2523 };
2524
2525 dbg_tracker2@10218000 {
2526 compatible = "mediatek,dbg_tracker2";
2527 reg = <0 0x10218000 0 0x1000>;
2528 };
2529
2530 emicen: emicen@10219000 {
2531 compatible = "mediatek,mt6880-emicen",
2532 "mediatek,common-emicen";
2533 reg = <0 0x10219000 0 0x1000>;
2534 mediatek,emi-reg = <&emichn>;
2535 };
2536
2537 infra_device_mpu@1021a000 {
2538 compatible = "mediatek,infra_device_mpu";
2539 reg = <0 0x1021a000 0 0x1000>;
2540 };
2541
2542 infra_device_mpu@1021b000 {
2543 compatible = "mediatek,infra_device_mpu";
2544 reg = <0 0x1021b000 0 0x1000>;
2545 };
2546
2547 infracfg_mem@1021c000 {
2548 compatible = "mediatek,infracfg_mem";
2549 reg = <0 0x1021c000 0 0x1000>;
2550 };
2551
2552 emimpu:emimpu@10226000 {
2553 compatible = "mediatek,mt6880-emimpu",
2554 "mediatek,common-emimpu";
2555 reg = <0 0x10226000 0 0x1000>;
2556 mediatek,emi-reg = <&emicen>;
2557 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2558 region_cnt = <32>;
2559 domain_cnt = <16>;
2560 addr_align = <16>;
2561 ap_region = <31>;
2562 ap_apc = <0 0 5 5 0 0 6 0>,
2563 <0 0 5 5 5 5 5 5>;
2564 dump = <0x1f0 0x1f8 0x1fc>;
2565 clear = <0x160 0xffffffff 16>,
2566 <0x200 0x00000003 16>,
2567 <0x1f0 0x80000000 1>;
2568 clear_md = <0x1fc 0x80000000 1>;
2569 ctrl_intf = <1>;
2570 slverr = <0>;
2571 };
2572
2573 cldma_sys_ap {
2574 compatible = "mediatek,cldma_sys_ap";
2575 reg = <0 0x1004A000 0 0x1000>, /*CLDMA0_AO_INDMA_AO_MD*/
2576 <0 0x1021E000 0 0x1000>; /*CLDMA0_AO_INDMA_PD_MD*/
2577 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; /*cldma0_md_int_ap*/
2578 clocks = <&infracfg_ao_clk CLK_IFRAO_RG_133M_CLDMA_TOP>;
2579 clock-names = "infra-cldma0-rh";
2580 mediatek,hif_ids = <1>; /* (1 << HIF_ID_CLDMA) */
2581 };
2582
2583 mrdump_ext_rst: mrdump_ext_rst {
2584 compatible = "mediatek, mrdump_ext_rst-disabled";
2585 mode = "IRQ";
2586 status = "okay";
2587 };
2588
2589 dpmaif:dpmaif@10014000 {
2590 compatible = "mediatek,dpmaif";
2591 reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
2592 <0 0x1022D000 0 0x1000>, /*PD_UL*/
2593 <0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
2594 <0 0x1022E000 0 0x1000>, /*SRAM*/
2595 <0 0x15B14000 0 0x1000>, /*MED_BMP_CFG*/
2596 <0 0x15B38000 0 0x1000>; /*MED_SSR1_CFG*/
2597 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; /*209+32=241*/
2598 mediatek,dpmaif_capability = <6>;
2599 clocks = <&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
2600 <&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>;
2601 clock-names = "infra-dpmaif-clk",
2602 "infra-dpmaif-blk-clk";
2603 };
2604
2605 mddriver:mddriver {
2606 compatible = "mediatek,mddriver";
2607 mediatek,mdhif_type = <2>; /* bit0~3: CLDMA|CCIF|DPMAIF */
2608 mediatek,md_id = <0>;
2609 mediatek,cldma_capability = <2>;
2610 reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
2611 <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
2612 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 174/206*/
2613 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 175/207*/
2614 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; /*MDWDT*/
2615 clocks = <&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
2616 <&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
2617 <&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
2618 <&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
2619 <&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
2620 <&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>,
2621 <&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>;
2622 clock-names = "infra-ccif-ap",
2623 "infra-ccif-md",
2624 "infra-ccif1-ap",
2625 "infra-ccif1-md",
2626 "infra-ccif2-ap",
2627 "infra-ccif2-md",
2628 "infra-ccif4-md";
2629 power-domains = <&scpsys MT6890_POWER_DOMAIN_MD1>;
2630 };
2631
2632/* md_auxadc:md_auxadc {
2633 compatible = "mediatek,md_auxadc";
2634 io-channels = <&auxadc 2>;
2635 io-channel-names = "md-channel",
2636 "md-battery";
2637 };
2638
2639 md_ccci_rtc:md_ccci_rtc {
2640 compatible = "mediatek,md_ccci_rtc";
2641 nvmem-cells = <&ext_32k>;
2642 nvmem-cell-names = "external-32k";
2643 }; */
2644
2645 gce_mbox: gce_mbox@10228000 {
2646 compatible = "mediatek,mailbox-gce";
2647 reg = <0 0x10228000 0 0x4000>;
2648 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
2649
2650 #mbox-cells = <3>;
2651 #gce-event-cells = <1>;
2652 #gce-subsys-cells = <2>;
2653 default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
2654 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
2655 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
2656 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
2657 /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
2658 /bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
2659 /bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
2660 clocks = <&infracfg_ao_clk CLK_IFRAO_GCE>,
2661 <&infracfg_ao_clk CLK_IFRAO_GCE_26M_SET>;
2662 clock-names = "gce", "gce-timer";
2663 };
2664
2665 cmdq-test {
2666 compatible = "mediatek,cmdq-test";
2667 mediatek,gce = <&gce_mbox>;
2668 mmsys_config = <&mmsys_config>;
2669 mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
2670 mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>,
2671 <&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
2672 <&gce_mbox 11 0 CMDQ_THR_PRIO_1>;
2673 token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
2674 token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
2675 };
2676
2677 infra_dpmaif@1022c000 {
2678 compatible = "mediatek,infra_dpmaif";
2679 reg = <0 0x1022c000 0 0x10>;
2680 };
2681
2682 dramc: dramc@10230000 {
2683 compatible = "mediatek,mt6880-dramc",
2684 "mediatek,common-dramc";
2685 reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
2686 <0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
2687 <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
2688 <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
2689 <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
2690 <0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
2691 <0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
2692 <0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
2693 <0 0x10006000 0 0x1000>; /* SLEEP BASE */
2694 mr4_version = <1>;
2695 mr4_rg = <0x0090 0x0000ffff 0>;
2696 fmeter_version = <1>;
2697 crystal_freq = <52>;
2698 pll_id = <0x050c 0x00000100 8>;
2699 shu_lv = <0x050c 0x00030000 16>;
2700 shu_of = <0x700>;
2701 sdmpcw = <0x0704 0xffff0000 16>,
2702 <0x0724 0xffff0000 16>;
2703 prediv = <0x0708 0x000c0000 18>,
2704 <0x0728 0x000c0000 18>;
2705 posdiv = <0x0708 0x00000007 0>,
2706 <0x0728 0x00000007 0>;
2707 ckdiv4 = <0x0874 0x00000004 2>,
2708 <0x0874 0x00000004 2>;
2709 pll_md = <0x0744 0x00000100 8>,
2710 <0x0744 0x00000100 8>;
2711 cldiv2 = <0x08b4 0x00000002 1>,
2712 <0x08b4 0x00000002 1>;
2713 fbksel = <0x070c 0x00000040 6>,
2714 <0x070c 0x00000040 6>;
2715 dqopen = <0x0870 0x00100000 20>,
2716 <0x0870 0x00100000 20>;
2717 };
2718 emiisu: emiisu {
2719 compatible = "mediatek,mt6880-emiisu",
2720 "mediatek,common-emiisu";
2721 ctrl_intf = <1>;
2722 };
2723 emichn: emichn@10235000 {
2724 compatible = "mediatek,mt6880-emichn",
2725 "mediatek,common-emichn";
2726 reg = <0 0x10235000 0 0x1000>,
2727 <0 0x10245000 0 0x1000>;
2728 };
2729
2730 dramc_ch0_top0@10230000 {
2731 compatible = "mediatek,dramc_ch0_top0";
2732 reg = <0 0x10230000 0 0x2000>;
2733 };
2734
2735 dramc_ch0_top1@10232000 {
2736 compatible = "mediatek,dramc_ch0_top1";
2737 reg = <0 0x10232000 0 0x2000>;
2738 };
2739
2740 dramc_ch0_top2@10234000 {
2741 compatible = "mediatek,dramc_ch0_top2";
2742 reg = <0 0x10234000 0 0x1000>;
2743 };
2744
2745 dramc_ch0_top3@10235000 {
2746 compatible = "mediatek,dramc_ch0_top3";
2747 reg = <0 0x10235000 0 0x1000>;
2748 };
2749
2750 dramc_ch0_top4@10236000 {
2751 compatible = "mediatek,dramc_ch0_top4";
2752 reg = <0 0x10236000 0 0x2000>;
2753 };
2754
2755 dramc_ch0_top5@10238000 {
2756 compatible = "mediatek,dramc_ch0_top5";
2757 reg = <0 0x10238000 0 0x2000>;
2758 };
2759
2760 dramc_ch0_top6@1023a000 {
2761 compatible = "mediatek,dramc_ch0_top6";
2762 reg = <0 0x1023a000 0 0x2000>;
2763 };
2764
2765 ap_ccif2@1023c000 {
2766 compatible = "mediatek,ap_ccif2";
2767 reg = <0 0x1023c000 0 0x1000>;
2768 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2769 };
2770
2771 md_ccif2@1023d000 {
2772 compatible = "mediatek,md_ccif2";
2773 reg = <0 0x1023d000 0 0x1000>;
2774 };
2775
2776 ap_ccif3@1023e000 {
2777 compatible = "mediatek,ap_ccif3";
2778 reg = <0 0x1023e000 0 0x1000>;
2779 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2780 };
2781
2782 md_ccif3@1023f000 {
2783 compatible = "mediatek,md_ccif3";
2784 reg = <0 0x1023f000 0 0x1000>;
2785 };
2786
2787 i2c_common: i2c_common {
2788 compatible = "mediatek,i2c_common";
2789 dma_support = /bits/ 8 <3>;
2790 idvfs = /bits/ 8 <1>;
2791 set_dt_div = /bits/ 8 <1>;
2792 check_max_freq = /bits/ 8 <1>;
2793 ver = /bits/ 8 <2>;
2794 set_ltiming = /bits/ 8 <1>;
2795 ext_time_config = /bits/ 16 <0x1801>;
2796 cnt_constraint = /bits/ 8 <1>;
2797 dma_ver = /bits/ 8 <1>;
2798 };
2799
2800 i2c0: i2c0@11c40000 {
2801 compatible = "mediatek,i2c";
2802 id = <0>;
2803 reg = <0 0x11c40000 0 0x1000>,
2804 <0 0x10217080 0 0x80>;
2805 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2806 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C0_RO>,
2807 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2808 clock-names = "main", "dma";
2809 clock-div = <5>;
2810 aed = <0x1a>;
2811 };
2812
2813 i2c1: i2c1@11c41000 {
2814 compatible = "mediatek,i2c";
2815 id = <1>;
2816 reg = <0 0x11c41000 0 0x1000>,
2817 <0 0x10217100 0 0x80>;
2818 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
2819 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C1_RO>,
2820 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2821 clock-names = "main", "dma";
2822 clock-div = <5>;
2823 aed = <0x1a>;
2824 };
2825
2826 i2c2: i2c2@11c42000 {
2827 compatible = "mediatek,i2c";
2828 id = <2>;
2829 reg = <0 0x11c42000 0 0x1000>,
2830 <0 0x10217180 0 0x80>;
2831 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2832 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C2_RO>,
2833 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2834 clock-names = "main", "dma";
2835 clock-div = <5>;
2836 aed = <0x1a>;
2837 };
2838
2839 i2c3: i2c3@11c43000 {
2840 compatible = "mediatek,i2c";
2841 id = <3>;
2842 reg = <0 0x11c43000 0 0x1000>,
2843 <0 0x10217200 0 0x80>;
2844 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
2845 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C3_RO>,
2846 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2847 clock-names = "main", "dma";
2848 clock-div = <5>;
2849 aed = <0x1a>;
2850 };
2851
2852 i2c4: i2c4@11c44000 {
2853 compatible = "mediatek,i2c";
2854 id = <4>;
2855 reg = <0 0x11c44000 0 0x1000>,
2856 <0 0x10217280 0 0x80>;
2857 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2858 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C4_RO>,
2859 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2860 clock-names = "main", "dma";
2861 clock-div = <5>;
2862 aed = <0x1a>;
2863 };
2864
2865 i2c5: i2c5@11c45000 {
2866 compatible = "mediatek,i2c";
2867 id = <5>;
2868 reg = <0 0x11c45000 0 0x1000>,
2869 <0 0x10217300 0 0x80>;
2870 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
2871 clocks = <&imp_iic_wrap_e_clk CLK_IMPE_AP_CLOCK_I2C5_RO>,
2872 <&infracfg_ao_clk CLK_IFRAO_I2C3>;
2873 clock-names = "main", "dma";
2874 clock-div = <5>;
2875 aed = <0x1a>;
2876 };
2877
2878 ssusb: usb@11201000 {
2879 compatible = "mediatek,mtu3";
2880 reg = <0 0x11201000 0 0x2e00>,
2881 <0 0x11203e00 0 0x0100>;
2882 reg-names = "mac", "ippc";
2883 vusb33-supply = <&mt6330_vusb_ldo_reg>;
2884 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2885
2886 phy-cells = <1>;
2887 phys = <&u2port0 PHY_TYPE_USB2>,
2888 <&u3port0 PHY_TYPE_USB3>;
2889 plat_type = <1>; /* 0: FPGA 1: ASIC */
2890 dr_mode = "peripheral";
2891 maximum-speed = "super-speed";
2892 clocks = <&infracfg_ao_clk CLK_IFRAO_SSUSB>,
2893 <&infracfg_ao_clk CLK_IFRAO_SSUSB_XHCI>;
2894 clock-names = "sys_ck","ref_ck";
2895 power-domains = <&scpsys MT6890_POWER_DOMAIN_SSUSB>;
2896 usb-role-switch;
2897 mediatek,force-vbus;
2898 mediatek,usb3-drd;
2899
2900 #address-cells = <2>;
2901 #size-cells = <2>;
2902 ranges;
2903
2904 usb_host: xhci0@11200000 {
2905 compatible = "mediatek,mtk-xhci";
2906 reg = <0 0x11200000 0 0x1000>;
2907 reg-names = "mac";
2908 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2909 clocks = <&clk26m>;
2910 clock-names = "sys_ck";
2911 };
2912 };
2913
2914 u3fpgaphy: usb-phy {
2915 compatible = "mediatek,fpga-u3phy";
2916 mediatek,ippc = <0x11203e00>;
2917 #address-cells = <2>;
2918 #size-cells = <2>;
2919 fpga_i2c_physical_base = <0x11c42000>;
2920 status = "disabled";
2921
2922 u3fpgaport0: usb-phy@0 {
2923 chip-id= <0xa60931a>;
2924 port = <0>;
2925 pclk_phase = <23>;
2926 #phy-cells = <1>;
2927 };
2928 };
2929
2930 u3phy: usb-phy@11e30000 {
2931 compatible = "mediatek,generic-tphy-v2";
2932 clocks = <&clk26m>;
2933 clock-names = "u3phya_ref";
2934 #address-cells = <2>;
2935 #size-cells = <2>;
2936 ranges;
2937
2938 u2port0: usb2-phy0@11e30000 {
2939 reg = <0 0x11e30000 0 0x700>;
2940 #phy-cells = <1>;
2941 mediatek,eye-rev6 = <1>;
2942 mediatek,eye-vrt = <5>;
2943 mediatek,eye-term = <5>;
2944 mediatek,rx-sqth = <5>;
2945 status = "okay";
2946 };
2947
2948 u3port0: usb3-phy0@11e30700 {
2949 reg = <0 0x11e30700 0 0x900>;
2950 #phy-cells = <1>;
2951 status = "okay";
2952 };
2953 };
2954
2955 apdma: dma-controller@0x10217000 {
2956 compatible = "mediatek, mt6873-uart-dma",
2957 "mediatek,mt6577-uart-dma";
2958 reg = <0 0x10217380 0 0x80>,
2959 <0 0x10217400 0 0x80>,
2960 <0 0x10217480 0 0x80>,
2961 <0 0x10217500 0 0x80>,
2962 <0 0x10217580 0 0x80>,
2963 <0 0x10217600 0 0x80>;
2964 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2965 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2966 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2967 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2968 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2969 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2970 dma-requests = <6>;
2971 dma-bits = <34>;
2972 clocks = <&clk26m>;
2973 #dma-cells = <1>;
2974 };
2975
2976 auxadc: auxadc@11001000 {
2977 compatible = "mediatek,mt6765-auxadc";
2978 reg = <0 0x11001000 0 0x1000>;
2979 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
2980 clocks = <&infracfg_ao_clk CLK_IFRAO_AUXADC>;
2981 clock-names = "main";
2982 #io-channel-cells = <1>;
2983 /* Auxadc efuse calibration */
2984 /* 1. Auxadc cali on/off bit shift */
2985 mediatek,cali-en-bit = <20>;
2986 /* 2. Auxadc cali ge bits shift */
2987 mediatek,cali-ge-bit = <10>;
2988 /* 3. Auxadc cali oe bits shift */
2989 mediatek,cali-oe-bit = <0>;
2990 /* 4. Auxadc cali efuse reg offset */
2991 mediatek,cali-efuse-reg-offset = <0xf8>;
2992 nvmem = <&efuse>;
2993 nvmem-names = "mtk_efuse";
2994 #interconnect-cells = <1>;
2995 };
2996
2997 uart0: serial@11002000 {
2998 compatible = "mediatek,mt6873-uart",
2999 "mediatek,mt6577-uart";
3000 reg = <0 0x11002000 0 0x1000>;
3001 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
3002 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART0>;
3003 clock-names = "baud", "bus";
3004 dmas = <&apdma 0
3005 &apdma 1>;
3006 dma-names = "tx", "rx";
3007 };
3008
3009 uart1: serial@11003000 {
3010 compatible = "mediatek,mt6873-uart",
3011 "mediatek,mt6577-uart";
3012 reg = <0 0x11003000 0 0x1000>;
3013 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
3014 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART1>;
3015 clock-names = "baud", "bus";
3016 dmas = <&apdma 2
3017 &apdma 3>;
3018 dma-names = "tx", "rx";
3019 };
3020
3021 uart2: serial@11004000 {
3022 compatible = "mediatek,mt6873-uart",
3023 "mediatek,mt6577-uart";
3024 reg = <0 0x11004000 0 0x1000>;
3025 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
3026 clocks = <&clk26m>, <&infracfg_ao_clk CLK_IFRAO_UART2>;
3027 clock-names = "baud", "bus";
3028 dmas = <&apdma 4
3029 &apdma 5>;
3030 dma-names = "tx", "rx";
3031 };
3032
3033 nandc: nfi@11005000 {
3034 compatible = "mediatek,mt6880-nfc";
3035 reg = <0 0x11005000 0 0x1000>,
3036 <0 0x11006000 0 0x1000>;
3037 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
3038 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
3039 status = "ok";
3040 };
3041
3042 nor: nor_flash@0x11250000 {
3043 compatible = "mediatek,mt8173-nor";
3044 reg = <0 0x11250000 0 0x1000>;
3045 clocks =<&topckgen_clk CLK_TOP_SFLASH_SEL>,
3046 <&infracfg_ao_clk CLK_IFRAO_RG_FLASHIF_SFLASH>;
3047 clock-names = "spi", "sf";
3048 #address-cells = <1>;
3049 #size-cells = <0>;
3050 status = "ok";
3051 };
3052
3053 pd-sgmii_0_phy {
3054 compatible = "mediatek,sgmii-bring-up";
3055 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
3056 };
3057
3058 pd-sgmii_0_top {
3059 compatible = "mediatek,sgmii-bring-up";
3060 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
3061 };
3062
3063 pd-sgmii_1_phy {
3064 compatible = "mediatek,sgmii-bring-up";
3065 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
3066 };
3067
3068 pd-sgmii_1_top {
3069 compatible = "mediatek,sgmii-bring-up";
3070 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
3071 };
3072
3073 sgmiisys_0: sgmiisys@10060000 {
3074 compatible = "mediatek,colgin-sgmiisys_0", "syscon";
3075 reg = <0 0x10060000 0 0x1000>;
3076 #clock-cells = <1>;
3077 mediatek,physpeed = "2500";
3078 /*modify by CLK SW Pei-hsuan Cheng */
3079 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_TOP>;
3080 };
3081
3082 sgmiisys_1: sgmiisys@10070000 {
3083 compatible = "mediatek,colgin-sgmiisys_1", "syscon";
3084 reg = <0 0x10070000 0 0x1000>;
3085 #clock-cells = <1>;
3086 mediatek,physpeed = "2500";
3087 /*modify by CLK SW Pei-hsuan Cheng */
3088 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_TOP>;
3089 };
3090
3091 sgmiisys_phy_0: sgmiiphy@11ED0000 {
3092 compatible = "mediatek,colgin-sgmiisys_phy_0", "syscon";
3093 reg = <0 0x11ED0000 0 0x1000>;
3094 #clock-cells = <1>;
3095 /*modify by CLK SW Pei-hsuan Cheng */
3096 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_0_PHY>;
3097 };
3098
3099 sgmiisys_phy_1: sgmiiphy@11EE0000 {
3100 compatible = "mediatek,colgin-sgmiisys_phy_1", "syscon";
3101 reg = <0 0x11EE0000 0 0x1000>;
3102 #clock-cells = <1>;
3103 /*modify by CLK SW Pei-hsuan Cheng */
3104 power-domains = <&scpsys MT6890_POWER_DOMAIN_SGMII_1_PHY>;
3105 };
3106
3107 ethsys: ethsys@15000000 {
3108 #address-cells = <1>;
3109 #size-cells = <1>;
3110 compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
3111 reg = <0 0x15000000 0 0x1000>;
3112 #clock-cells = <1>;
3113 #reset-cells = <1>;
3114
3115 ethsysrst: reset-controller {
3116 compatible = "ti,syscon-reset";
3117 #reset-cells = <1>;
3118 ti,reset-bits = <
3119 0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET) /* 4: wocpu_rst */
3120 >;
3121 };
3122 };
3123
3124 wo: wo@15195000 {
3125 compatible = "mediatek,leopard-ethsys", "syscon", "simple-mfd";
3126 reg = <0 0x15195000 0 0x1000>;
3127 };
3128
3129 eth: ethernet@15100000 {
3130 compatible = "mediatek,mt6890-eth",
3131 "syscon";
3132 reg = <0 0x15100000 0 0x20000>;
3133 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
3134 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
3135 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
3136 clocks = <&topckgen_clk CLK_TOP_NETSYS_SEL>,
3137 <&topckgen_clk CLK_TOP_MEDSYS_SEL>,
3138 <&topckgen_clk CLK_TOP_NETSYS_500M_SEL>,
3139 <&topckgen_clk CLK_TOP_NETSYS_MED_MCU_SEL>,
3140 <&topckgen_clk CLK_TOP_NETSYS_WED_MCU_SEL>,
3141 <&topckgen_clk CLK_TOP_NETSYS_2X_SEL>,
3142 <&topckgen_clk CLK_TOP_SGMII_SEL>,
3143 <&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
3144 clock-names = "net_sel", "med_sel", "net_500_sel",
3145 "med_mcu_sel", "wed_mcu_sel",
3146 "net_2x_sel", "sgmii_sel", "sgmii_sbus_sel";
3147 /*modify by CLK SW Pei-hsuan Cheng
3148 power-domains = <&scpsys MT6890_POWER_DOMAIN_NETSYS>;*/
3149 mediatek,ethsys = <&ethsys>;
3150 mediatek,wo = <&wo>;
3151 mediatek,sgmiisys = <&sgmiisys_0>,<&sgmiisys_1>;
3152 mediatek,sgmiisys_phy = <&sgmiisys_phy_0>,<&sgmiisys_phy_1>;
3153 #address-cells = <1>;
3154 #size-cells = <0>;
3155 status = "disabled";
3156 };
3157
3158 stmmac_axi_setup: stmmac-axi-config {
3159 snps,wr_osr_lmt = <0x7>;
3160 snps,rd_osr_lmt = <0x7>;
3161 snps,blen = <0 0 0 0 16 8 4>;
3162 };
3163
3164 mtl_rx_setup: rx-queues-config {
3165 snps,rx-queues-to-use = <1>;
3166 snps,rx-sched-sp;
3167 queue0 {
3168 snps,dcb-algorithm;
3169 snps,map-to-dma-channel = <0x0>;
3170 snps,priority = <0x0>;
3171 };
3172 queue1 {
3173 snps,dcb-algorithm;
3174 snps,map-to-dma-channel = <0x1>;
3175 snps,priority = <0x0>;
3176 snps,route-ptp;
3177 };
3178 queue2 {
3179 snps,dcb-algorithm;
3180 snps,map-to-dma-channel = <0x2>;
3181 snps,priority = <0x0>;
3182 snps,route-multi-broad;
3183 };
3184 };
3185
3186 mtl_tx_setup: tx-queues-config {
3187 snps,tx-queues-to-use = <3>;
3188 snps,tx-sched-wrr;
3189 queue0 {
3190 snps,weight = <0x10>;
3191 snps,dcb-algorithm;
3192 snps,priority = <0x0>;
3193 };
3194
3195 queue1 {
3196 snps,weight = <0x11>;
3197 snps,dcb-algorithm;
3198 snps,priority = <0x1>;
3199 };
3200
3201 queue2 {
3202 snps,weight = <0x12>;
3203 snps,dcb-algorithm;
3204 snps,priority = <0x2>;
3205 };
3206 };
3207
3208 snps_mac: ethernet@11021000 {
3209 compatible = "mediatek,mt2735-gmac";
3210 reg = <0 0x11021000 0 0x1300>;
3211 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3212 interrupt-names = "macirq";
3213 mac-address = [00 55 7b b5 7d f7];
3214 clock-names = "mac_main",
3215 "ptp_ref",
3216 "eth_cg",
3217 "eth_rmii",
3218 "sgmii_sel",
3219 "sgmii_sbus_sel";
3220 clocks = <&topckgen_clk CLK_TOP_SNPS_ETH_312P5M_SEL>,
3221 <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>,
3222 <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>,
3223 <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>,
3224 <&topckgen_clk CLK_TOP_SGMII_SEL>,
3225 <&topckgen_clk CLK_TOP_SGMII_SBUS_SEL>;
3226 mediatek,pericfg = <&infracfg_ao>;
3227 snps,axi-config = <&stmmac_axi_setup>;
3228 snps,mtl-rx-config = <&mtl_rx_setup>;
3229 snps,mtl-tx-config = <&mtl_tx_setup>;
3230 /*modify by CLK SW Pei-hsuan Cheng */
3231 power-domains = <&scpsys MT6890_POWER_DOMAIN_ETH>;
3232 mediatek,sgmiisys = <&sgmiisys_0>;
3233 mediatek,sgmiisys_phy = <&sgmiisys_phy_0>;
3234 snps,txpbl = <1>;
3235 snps,rxpbl = <1>;
3236 clk_csr = <0>;
3237 status = "disabled";
3238 };
3239
3240 crypto: crypto@10320000 {
3241 /* compatible = "mediatek,eip97-crypto"; */
3242 /* compatible = "safexcel-ip-97-mob"; */
3243 compatible = "inside-secure,safexcel-eip97";
3244 reg = <0 0x10320000 0 0x40000>;
3245 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
3246 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
3247 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
3248 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3249 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
3250 interrupt-names = "ring0", "ring1", "ring2", "ring3";
3251 clocks = <&topckgen_clk CLK_TOP_EIP97_SEL>,
3252 <&topckgen_clk CLK_TOP_NET2PLL>,
3253 <&topckgen_clk CLK_TOP_MAINPLL_D5_D2>;
3254 clock-names = "clk-mux", "net2pll", "D5_D2";
3255 power-domains = <&scpsys MT6890_POWER_DOMAIN_EIP97>;
3256 };
3257
3258 dramc_ch1_top0@10240000 {
3259 compatible = "mediatek,dramc_ch1_top0";
3260 reg = <0 0x10240000 0 0x2000>;
3261 };
3262
3263 dramc_ch1_top1@10242000 {
3264 compatible = "mediatek,dramc_ch1_top1";
3265 reg = <0 0x10242000 0 0x2000>;
3266 };
3267
3268 dramc_ch1_top2@10244000 {
3269 compatible = "mediatek,dramc_ch1_top2";
3270 reg = <0 0x10244000 0 0x1000>;
3271 };
3272
3273 dramc_ch1_top3@10245000 {
3274 compatible = "mediatek,dramc_ch1_top3";
3275 reg = <0 0x10245000 0 0x1000>;
3276 };
3277
3278 dramc_ch1_top4@10246000 {
3279 compatible = "mediatek,dramc_ch1_top4";
3280 reg = <0 0x10246000 0 0x2000>;
3281 };
3282
3283 dramc_ch1_top5@10248000 {
3284 compatible = "mediatek,dramc_ch1_top5";
3285 reg = <0 0x10248000 0 0x2000>;
3286 };
3287
3288 dramc_ch1_top6@1024a000 {
3289 compatible = "mediatek,dramc_ch1_top6";
3290 reg = <0 0x1024a000 0 0x2000>;
3291 };
3292
3293 ap_ccif4@1024c000 {
3294 compatible = "mediatek,ap_ccif4";
3295 reg = <0 0x1024c000 0 0x1000>;
3296 };
3297
3298 md_ccif4@1024d000 {
3299 compatible = "mediatek,md_ccif4";
3300 reg = <0 0x1024d000 0 0x1000>;
3301 };
3302
3303 md_ccif4@1024e000 {
3304 compatible = "mediatek,md_ccif4";
3305 reg = <0 0x1024e000 0 0x1000>;
3306 };
3307
3308 dramc_ch2_top0@10250000 {
3309 compatible = "mediatek,dramc_ch2_top0";
3310 reg = <0 0x10250000 0 0x2000>;
3311 };
3312
3313 dramc_ch2_top1@10252000 {
3314 compatible = "mediatek,dramc_ch2_top1";
3315 reg = <0 0x10252000 0 0x2000>;
3316 };
3317
3318 dramc_ch2_top2@10254000 {
3319 compatible = "mediatek,dramc_ch2_top2";
3320 reg = <0 0x10254000 0 0x1000>;
3321 };
3322
3323 dramc_ch2_top3@10255000 {
3324 compatible = "mediatek,dramc_ch2_top3";
3325 reg = <0 0x10255000 0 0x1000>;
3326 };
3327
3328 dramc_ch2_top4@10256000 {
3329 compatible = "mediatek,dramc_ch2_top4";
3330 reg = <0 0x10256000 0 0x2000>;
3331 };
3332
3333 dramc_ch2_top5@10258000 {
3334 compatible = "mediatek,dramc_ch2_top5";
3335 reg = <0 0x10258000 0 0x2000>;
3336 };
3337
3338 dramc_ch2_top6@1025a000 {
3339 compatible = "mediatek,dramc_ch2_top6";
3340 reg = <0 0x1025a000 0 0x2000>;
3341 };
3342
3343 ap_ccif5@1025c000 {
3344 compatible = "mediatek,ap_ccif5";
3345 reg = <0 0x1025c000 0 0x1000>;
3346 };
3347
3348 md_ccif5@1025d000 {
3349 compatible = "mediatek,md_ccif5";
3350 reg = <0 0x1025d000 0 0x1000>;
3351 };
3352
3353 mm_vpu_m0_sub_common@1025e000 {
3354 compatible = "mediatek,mm_vpu_m0_sub_common";
3355 reg = <0 0x1025e000 0 0x1000>;
3356 };
3357
3358 mm_vpu_m1_sub_common@1025f000 {
3359 compatible = "mediatek,mm_vpu_m1_sub_common";
3360 reg = <0 0x1025f000 0 0x1000>;
3361 };
3362
3363 dramc_ch3_top0@10260000 {
3364 compatible = "mediatek,dramc_ch3_top0";
3365 reg = <0 0x10260000 0 0x2000>;
3366 };
3367
3368 dramc_ch3_top1@10262000 {
3369 compatible = "mediatek,dramc_ch3_top1";
3370 reg = <0 0x10262000 0 0x2000>;
3371 };
3372
3373 dramc_ch3_top2@10264000 {
3374 compatible = "mediatek,dramc_ch3_top2";
3375 reg = <0 0x10264000 0 0x1000>;
3376 };
3377
3378 dramc_ch3_top3@10265000 {
3379 compatible = "mediatek,dramc_ch3_top3";
3380 reg = <0 0x10265000 0 0x1000>;
3381 };
3382
3383 dramc_ch3_top4@10266000 {
3384 compatible = "mediatek,dramc_ch3_top4";
3385 reg = <0 0x10266000 0 0x2000>;
3386 };
3387
3388 dramc_ch3_top5@10268000 {
3389 compatible = "mediatek,dramc_ch3_top5";
3390 reg = <0 0x10268000 0 0x2000>;
3391 };
3392
3393 dramc_ch3_top6@1026a000 {
3394 compatible = "mediatek,dramc_ch3_top6";
3395 reg = <0 0x1026a000 0 0x2000>;
3396 };
3397
3398 bcrm_peri@10272000 {
3399 compatible = "mediatek,bcrm_peri";
3400 reg = <0 0x10272000 0 0x1000>;
3401 };
3402
3403 bcrm_peri2@10273000 {
3404 compatible = "mediatek,bcrm_peri2";
3405 reg = <0 0x10273000 0 0x1000>;
3406 };
3407
3408 devapc_peri@10274000 {
3409 compatible = "mediatek,devapc_peri";
3410 reg = <0 0x10274000 0 0x1000>;
3411 };
3412
3413 devapc_peri2@10275000 {
3414 compatible = "mediatek,devapc_peri2";
3415 reg = <0 0x10275000 0 0x1000>;
3416 };
3417
3418 bcrm_fmem@10276000 {
3419 compatible = "mediatek,bcrm_fmem";
3420 reg = <0 0x10276000 0 0x1000>;
3421 };
3422
3423 mm_vpu_m0_sub_common@10309000 {
3424 compatible = "mediatek,mm_vpu_m0_sub_common";
3425 reg = <0 0x10309000 0 0x1000>;
3426 };
3427
3428 mm_vpu_m1_sub_common@1030a000 {
3429 compatible = "mediatek,mm_vpu_m1_sub_common";
3430 reg = <0 0x1030a000 0 0x1000>;
3431 };
3432
3433 mm_vpu_m1_sub_common@1030b000 {
3434 compatible = "mediatek,mm_vpu_m1_sub_common";
3435 reg = <0 0x1030b000 0 0x1000>;
3436 };
3437
3438 mm_vpu_m1_sub_common@1030c000 {
3439 compatible = "mediatek,mm_vpu_m1_sub_common";
3440 reg = <0 0x1030c000 0 0x1000>;
3441 };
3442
3443 mm_vpu_m1_sub_common@1030d000 {
3444 compatible = "mediatek,mm_vpu_m1_sub_common";
3445 reg = <0 0x1030d000 0 0x1000>;
3446 };
3447
3448 sys_cirq1@10312000 {
3449 compatible = "mediatek,sys_cirq1";
3450 reg = <0 0x10312000 0 0x1000>;
3451 };
3452
3453 sys_cirq2@10313000 {
3454 compatible = "mediatek,sys_cirq2";
3455 reg = <0 0x10313000 0 0x1000>;
3456 };
3457
3458 dbg_tracker@10314000 {
3459 compatible = "mediatek,dbg_tracker";
3460 reg = <0 0x10314000 0 0x1000>;
3461 };
3462
3463 pwrmcu@10400000 {
3464 compatible = "mediatek,pwrmcu";
3465 reg = <0 0x10400000 0 0x100000>;
3466 };
3467
3468 sspm@10400000 {
3469 compatible = "mediatek,sspm";
3470 reg = <0 0x10400000 0 0x28000>,
3471 <0 0x10440000 0 0x10000>,
3472 <0 0x10450000 0 0x100>,
3473 <0 0x10451000 0 0x4>,
3474 <0 0x10451004 0 0x4>,
3475 <0 0x10460000 0 0x100>,
3476 <0 0x10461000 0 0x4>,
3477 <0 0x10461004 0 0x4>,
3478 <0 0x10470000 0 0x100>,
3479 <0 0x10471000 0 0x4>,
3480 <0 0x10471004 0 0x4>,
3481 <0 0x10480000 0 0x100>,
3482 <0 0x10481000 0 0x4>,
3483 <0 0x10481004 0 0x4>,
3484 <0 0x10490000 0 0x100>,
3485 <0 0x10491000 0 0x4>,
3486 <0 0x10491004 0 0x4>;
3487
3488 reg-names = "sspm_base",
3489 "cfgreg",
3490 "mbox0_base",
3491 "mbox0_set",
3492 "mbox0_clr",
3493 "mbox1_base",
3494 "mbox1_set",
3495 "mbox1_clr",
3496 "mbox2_base",
3497 "mbox2_set",
3498 "mbox2_clr",
3499 "mbox3_base",
3500 "mbox3_set",
3501 "mbox3_clr",
3502 "mbox4_base",
3503 "mbox4_set",
3504 "mbox4_clr";
3505
3506 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3509 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3510 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3512
3513 interrupt-names = "ipc",
3514 "mbox0",
3515 "mbox1",
3516 "mbox2",
3517 "mbox3",
3518 "mbox4";
3519 };
3520
3521 tinsys@10500000 {
3522 compatible = "mediatek,tinsys";
3523 reg = <0 0x10500000 0 0x0>;
3524 };
3525
3526 dramc_ch1_rsv0@10900000 {
3527 compatible = "mediatek,dramc_ch1_rsv0";
3528 reg = <0 0x10900000 0 0x40000>;
3529 };
3530
3531 dramc_ch1_rsv1@10940000 {
3532 compatible = "mediatek,dramc_ch1_rsv1";
3533 reg = <0 0x10940000 0 0xc0000>;
3534 };
3535
3536 mali: mali@13000000 {
3537 compatible = "mediatek,mali", "arm,mali-midgard", "arm,mali-bifrost";
3538 reg = <0 0x13000000 0 0x4000>;
3539 interrupts =
3540 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
3541 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
3544 interrupt-names =
3545 "GPU",
3546 "MMU",
3547 "JOB",
3548 "EVENT";
3549 operating-points-v2 = <&gpu_mali_opp>;
3550 #cooling-cells = <2>;
3551 gpufreq-supply = <&gpufreq>;
3552 };
3553
3554 gpu_mali_opp: opp-table0 {
3555 compatible = "operating-points-v2";
3556 opp00 {
3557 opp-hz = /bits/ 64 <780000000>;
3558 opp-microvolt = <750000>;
3559 };
3560 opp01 {
3561 opp-hz = /bits/ 64 <570000000>;
3562 opp-microvolt = <650000>;
3563 };
3564 opp02 {
3565 opp-hz = /bits/ 64 <360000000>;
3566 opp-microvolt = <600000>;
3567 };
3568 opp03 {
3569 opp-hz = /bits/ 64 <300000000>;
3570 opp-microvolt = <550000>;
3571 };
3572 };
3573
3574 gpufreq: gpufreq {
3575 compatible = "mediatek,gpufreq";
3576 clocks =
3577 <&topckgen_clk CLK_TOP_MFG_SEL>,
3578 <&topckgen_clk CLK_TOP_MFGPLL>,
3579 <&topckgen_clk CLK_TOP_MFG_REF_SEL>,
3580 <&mfgsys_clk CLK_MFGCFG_BG3D>;
3581 clock-names =
3582 "clk_mux", /* switch main/sub */
3583 "clk_main_parent", /* main pll freq */
3584 "clk_sub_parent", /* default 218.4 MHz */
3585 "cg_bg3d";
3586 /* power-domains = <&scpsys MT6890_POWER_DOMAIN_MFG0>; */
3587 status = "disabled";
3588 };
3589
3590 mmc0: mmc@11230000 {
3591 compatible = "mediatek,mt6880-mmc";
3592 reg = <0 0x11230000 0 0x1000>,
3593 <0 0x11f10000 0 0x1000>;
3594 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
3595 clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
3596 <&infracfg_ao_clk CLK_IFRAO_MSDC0>,
3597 <&infracfg_ao_clk CLK_IFRAO_MSDC0_SRC_CLK>;
3598 clock-names = "source", "hclk", "source_cg";
3599 power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
3600 status = "disabled";
3601 };
3602
3603 mmc1: mmc@11240000 {
3604 compatible = "mediatek,mt6880-mmc";
3605 reg = <0 0x11240000 0 0x1000>,
3606 <0 0x11f20000 0 0x1000>;
3607 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3608 clocks = <&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
3609 <&infracfg_ao_clk CLK_IFRAO_MSDC1>,
3610 <&infracfg_ao_clk CLK_IFRAO_MSDC1_SRC_CLK>;
3611 clock-names = "source", "hclk", "source_cg";
3612 power-domains = <&scpsys MT6890_POWER_DOMAIN_MSDC>;
3613 status = "disabled";
3614 };
3615
3616 lvts: lvts@1100b000 {
3617 compatible = "mediatek,mt6880-lvts";
3618 reg = <0 0x1100b000 0 0x1000>,
3619 <0 0x11278000 0 0x1000>,
3620 <0 0x10001000 0 0x1000>;
3621 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
3623 clocks = <&infracfg_ao_clk CLK_IFRAO_THERM>;
3624 clock-names = "lvts_clk";
3625
3626 resets = <&infracfg_rst 0>,
3627 <&infracfg_rst 1>;
3628
3629 nvmem-cells = <&lvts_e_data1>;
3630 nvmem-cell-names = "e_data1";
3631 #thermal-sensor-cells = <1>;
3632 };
3633
3634 disp_pwm: disp_pwm0@1100e000 {
3635 compatible = "mediatek,disp_pwm0",
3636 "mediatek,mt6890-disp-pwm";
3637 reg = <0 0x1100e000 0 0x1000>;
3638 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
3639 #pwm-cells = <2>;
3640 clocks = <&infracfg_ao CLK_IFRAO_DISP_PWM>,
3641 <&topckgen CLK_TOP_DISP_PWM_SEL>;
3642 clock-names = "main", "mm";
3643 };
3644
3645 pcie0: pcie@11280000 {
3646 compatible = "mediatek,mt2735-pcie";
3647 reg = <0 0x11280000 0 0x2000>;
3648 reg-names = "pcie-mac";
3649 linux,pci-domain = <0>;
3650 #address-cells = <3>;
3651 #size-cells = <2>;
3652 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
3653 bus-range = <0x00 0xff>;
3654 ranges = <0x82000000 0 0x00000000
3655 0x0 0x30000000 0 0x10000000>;
3656 status = "disabled";
3657
3658 clocks = <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_26M>,
3659 <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_96M>,
3660 <&infracfg_ao_clk CLK_IFRAO_PCIE_TL_32K>,
3661 <&infracfg_ao_clk CLK_IFRAO_PCIE_PERI_26M>,
3662 <&infracfg_ao_clk CLK_IFRAO_RG_133M_PCIE_P0>;
3663
3664 phys = <&pciephy0>;
3665 phy-names = "pcie-phy";
3666 power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1>;
3667
3668 #interrupt-cells = <1>;
3669 interrupt-map-mask = <0 0 0 7>;
3670 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
3671 <0 0 0 2 &pcie_intc0 1>,
3672 <0 0 0 3 &pcie_intc0 2>,
3673 <0 0 0 4 &pcie_intc0 3>;
3674 pcie_intc0: legacy-interrupt-controller {
3675 interrupt-controller;
3676 #address-cells = <0>;
3677 #interrupt-cells = <1>;
3678 };
3679 };
3680
3681 pciephy0: phy0@11e40000 {
3682 compatible = "mediatek,mt2735-pcie-phy";
3683 #address-cells = <2>;
3684 #size-cells = <2>;
3685 #phy-cells = <0>;
3686 reg = <0 0x11e40000 0 0x10000>,
3687 <0 0x11e50000 0 0x10000>;
3688 reg-names = "phy-sif", "phy-ckm";
3689 nvmem = <&efuse>;
3690 nvmem-names = "mtk_efuse";
3691 nvmem-cells = <&efuse_segment>;
3692 nvmem-cell-names = "efuse_segment_cell";
3693
3694 power-domains = <&scpsys MT6890_POWER_DOMAIN_PEXTP_D_2LX1_PHY>;
3695 };
3696
3697 efuse: efuse@11ec0000 {
3698 compatible = "mediatek,devinfo";
3699 reg = <0 0x11ec0000 0 0x10000>;
3700 #address-cells = <1>;
3701 #size-cells = <1>;
3702 efuse_segment: segment@78 {
3703 reg = <0x78 0x4>;
3704 };
3705
3706 lvts_e_data1: data1 {
3707 reg = <0x1E0 0x24>;
3708 };
3709 };
3710
3711 dfd@13e00000 {
3712 compatible = "mediatek,dfd";
3713 reg = <0 0x13e00000 0 0x40000>;
3714 };
3715
3716 g3d_dvfs@13fbc000 {
3717 compatible = "mediatek,g3d_dvfs";
3718 reg = <0 0x13fbc000 0 0x1000>;
3719 };
3720
3721 g3d_testbench@13fbd000 {
3722 compatible = "mediatek,g3d_testbench";
3723 reg = <0 0x13fbd000 0 0x1000>;
3724 };
3725
3726 g3d_config@13fbf000 {
3727 compatible = "mediatek,g3d_config";
3728 reg = <0 0x13fbf000 0 0x1000>;
3729 };
3730
3731 mmsys_config: mmsys_config@14000000 {
3732 compatible = "mediatek,mmsys_config";
3733 reg = <0 0x14000000 0 0x1000>;
3734 };
3735
3736 disp_mutex0@14001000 {
3737 compatible = "mediatek,disp_mutex0";
3738 reg = <0 0x14001000 0 0x1000>;
3739 };
3740
3741 mdp_rdma0@14002000 {
3742 compatible = "mediatek,mdp_rdma0";
3743 reg = <0 0x14002000 0 0x1000>;
3744 };
3745
3746 mdp_rsz0@14003000 {
3747 compatible = "mediatek,mdp_rsz0";
3748 reg = <0 0x14003000 0 0x1000>;
3749 };
3750
3751 mdp_wrot0@14004000 {
3752 compatible = "mediatek,mdp_wrot0";
3753 reg = <0 0x14004000 0 0x1000>;
3754 };
3755
3756 mdp_tdshp0@14005000 {
3757 compatible = "mediatek,mdp_tdshp0";
3758 reg = <0 0x14005000 0 0x1000>;
3759 };
3760
3761 disp_ovl0@14006000 {
3762 compatible = "mediatek,disp_ovl0";
3763 reg = <0 0x14006000 0 0x1000>;
3764 };
3765
3766 disp_rdma0@14007000 {
3767 compatible = "mediatek,disp_rdma0";
3768 reg = <0 0x14007000 0 0x1000>;
3769 };
3770
3771 disp_color0@14008000 {
3772 compatible = "mediatek,disp_color0";
3773 reg = <0 0x14008000 0 0x1000>;
3774 };
3775
3776 disp_ccorr0@14009000 {
3777 compatible = "mediatek,disp_ccorr0";
3778 reg = <0 0x14009000 0 0x1000>;
3779 };
3780
3781 disp_aal0@1400a000 {
3782 compatible = "mediatek,disp_aal0";
3783 reg = <0 0x1400a000 0 0x1000>;
3784 };
3785
3786 disp_gamma0@1400b000 {
3787 compatible = "mediatek,disp_gamma0";
3788 reg = <0 0x1400b000 0 0x1000>;
3789 };
3790
3791 disp_dither0@1400c000 {
3792 compatible = "mediatek,disp_dither0";
3793 reg = <0 0x1400c000 0 0x1000>;
3794 };
3795
3796 disp_wdma0@1400d000 {
3797 compatible = "mediatek,disp_wdma0";
3798 reg = <0 0x1400d000 0 0x1000>;
3799 };
3800
3801 dsi0@1400e000 {
3802 compatible = "mediatek,dsi0";
3803 reg = <0 0x1400e000 0 0x1000>;
3804 };
3805
3806 dbpi0@1400f000 {
3807 compatible = "mediatek,dbpi0";
3808 reg = <0 0x1400f000 0 0x1000>;
3809 };
3810
3811 smi_sub_common0@14010000 {
3812 compatible = "mediatek,smi_sub_common0";
3813 reg = <0 0x14010000 0 0x1000>;
3814 };
3815
3816 smi_common0@14016000 {
3817 compatible = "mediatek,smi_common0";
3818 reg = <0 0x14016000 0 0x1000>;
3819 };
3820
3821 smi_larb0: larb@14017000 {
3822 compatible = "mediatek,smi_larb0";
3823 reg = <0 0x14017000 0 0x1000>;
3824 mediatek,larb-id = <0>;
3825 };
3826
3827 spi0: spi0@1100a000 {
3828 compatible = "mediatek,mt6765-spi";
3829 mediatek,pad-select = <0>;
3830 reg = <0 0x1100a000 0 0x100>;
3831 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
3832 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3833 <&topckgen_clk CLK_TOP_SPI_SEL>,
3834 <&infracfg_ao_clk CLK_IFRAO_SPI0>;
3835 clock-names = "parent-clk", "sel-clk", "spi-clk";
3836 };
3837
3838 spi1: spi1@11010000 {
3839 compatible = "mediatek,mt6765-spi";
3840 mediatek,pad-select = <0>;
3841 reg = <0 0x11010000 0 0x100>;
3842 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3843 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3844 <&topckgen_clk CLK_TOP_SPI_SEL>,
3845 <&infracfg_ao_clk CLK_IFRAO_SPI1>;
3846 clock-names = "parent-clk", "sel-clk", "spi-clk";
3847 };
3848
3849 spi2: spi2@11012000 {
3850 compatible = "mediatek,mt6765-spi";
3851 mediatek,pad-select = <0>;
3852 reg = <0 0x11012000 0 0x100>;
3853 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
3854 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3855 <&topckgen_clk CLK_TOP_SPI_SEL>,
3856 <&infracfg_ao_clk CLK_IFRAO_SPI2>;
3857 clock-names = "parent-clk", "sel-clk", "spi-clk";
3858 };
3859
3860 spi3: spi3@11013000 {
3861 compatible = "mediatek,mt6765-spi";
3862 mediatek,pad-select = <0>;
3863 reg = <0 0x11013000 0 0x100>;
3864 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
3865 clocks = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D2>,
3866 <&topckgen_clk CLK_TOP_SPI_SEL>,
3867 <&infracfg_ao_clk CLK_IFRAO_SPI3>;
3868 clock-names = "parent-clk", "sel-clk", "spi-clk";
3869 };
3870
3871 iommu0: iommu@14011000 {
3872 compatible = "mediatek,mt6880-m4u";
3873 reg = <0 14011000 0 0x1000>;
3874 mediatek,larbs = <&smi_larb0>;
3875 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3876#if 0
3877 clocks = <&dispsys_config MM_SMI_INFRA>,
3878 <&dispsys_config MM_SMI_IOMMU>,
3879 <&scpsys SCP_SYS_DIS>;
3880 clock-names = "disp-infra-ck", "disp-iommu-ck", "power";
3881#endif
3882 #iommu-cells = <1>;
3883 };
3884
3885 amms_control {
3886 compatible = "mediatek,amms";
3887 interrupts = <GIC_SPI 425 IRQ_TYPE_EDGE_RISING>;
3888 };
3889
3890 mtk_m4u_debug {
3891 compatible = "mediatek,mt6880-m4u-debug";
3892#if 0
3893 iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
3894 <&iommu0 M4U_PORT_OVL_RDMA0_HDR>,
3895 <&iommu0 M4U_PORT_OVL_RDMA0>,
3896 <&iommu0 M4U_PORT_DISP_FAKE0>;
3897#endif
3898 };
3899
3900 reserved@14018000 {
3901 compatible = "mediatek,reserved";
3902 reg = <0 0x14018000 0 0x1000>;
3903 };
3904
3905 reserved@14019000 {
3906 compatible = "mediatek,reserved";
3907 reg = <0 0x14019000 0 0x1000>;
3908 };
3909
3910 reserved@1401a000 {
3911 compatible = "mediatek,reserved";
3912 reg = <0 0x1401a000 0 0x1000>;
3913 };
3914
3915 reserved@1401b000 {
3916 compatible = "mediatek,reserved";
3917 reg = <0 0x1401b000 0 0x1000>;
3918 };
3919
3920 reserved@1401c000 {
3921 compatible = "mediatek,reserved";
3922 reg = <0 0x1401c000 0 0x1000>;
3923 };
3924
3925 reserved@1401d000 {
3926 compatible = "mediatek,reserved";
3927 reg = <0 0x1401d000 0 0x1000>;
3928 };
3929
3930 reserved@1401e000 {
3931 compatible = "mediatek,reserved";
3932 reg = <0 0x1401e000 0 0x1000>;
3933 };
3934
3935 reserved@1401f000 {
3936 compatible = "mediatek,reserved";
3937 reg = <0 0x1401f000 0 0x1000>;
3938 };
3939
3940 reserved@14020000 {
3941 compatible = "mediatek,reserved";
3942 reg = <0 0x14020000 0 0x1000>;
3943 };
3944
3945 reserved@14021000 {
3946 compatible = "mediatek,reserved";
3947 reg = <0 0x14021000 0 0x1000>;
3948 };
3949
3950 reserved@14022000 {
3951 compatible = "mediatek,reserved";
3952 reg = <0 0x14022000 0 0x1000>;
3953 };
3954
3955 reserved@14023000 {
3956 compatible = "mediatek,reserved";
3957 reg = <0 0x14023000 0 0x1000>;
3958 };
3959
3960 reserved@14024000 {
3961 compatible = "mediatek,reserved";
3962 reg = <0 0x14024000 0 0x1000>;
3963 };
3964
3965 reserved@14025000 {
3966 compatible = "mediatek,reserved";
3967 reg = <0 0x14025000 0 0x1000>;
3968 };
3969
3970 reserved@14026000 {
3971 compatible = "mediatek,reserved";
3972 reg = <0 0x14026000 0 0xda000>;
3973 };
3974
3975 medmcu: medmcu@15f00000 {
3976 compatible = "mediatek,medmcu";
3977 status = "okay";
3978 reg = <0 0x15d00000 0 0x20000>, /* tcm */
3979 <0 0x15f24000 0 0x1000>, /* cfg */
3980 <0 0x15f21000 0 0x1000>, /* clk*/
3981 <0 0x15f30000 0 0x1000>, /* cfg core0 */
3982 <0 0x15f40000 0 0x1000>, /* cfg core1 */
3983 <0 0x15f52000 0 0x1000>, /* bus tracker */
3984 <0 0x15f60000 0 0x40000>, /* llc */
3985 <0 0x15fa5000 0 0x4>, /* cfg_sec */
3986 <0 0x15ffb000 0 0x100>, /* mbox0 base */
3987 <0 0x15ffb100 0 0x4>, /* mbox0 set */
3988 <0 0x15ffb10c 0 0x4>, /* mbox0 clr */
3989 <0 0x15fa5020 0 0x4>, /* mbox0 init */
3990 <0 0x15ffc000 0 0x100>, /* mbox1 base */
3991 <0 0x15ffc100 0 0x4>, /* mbox1 set */
3992 <0 0x15ffc10c 0 0x4>, /* mbox1 clr */
3993 <0 0x15fa5024 0 0x4>, /* mbox1 init */
3994 <0 0x15ffd000 0 0x100>, /* mbox2 base */
3995 <0 0x15ffd100 0 0x4>, /* mbox2 set */
3996 <0 0x15ffd10c 0 0x4>, /* mbox2 clr */
3997 <0 0x15fa5028 0 0x4>, /* mbox2 init */
3998 <0 0x15ffe000 0 0x100>, /* mbox3 base */
3999 <0 0x15ffe100 0 0x4>, /* mbox3 set */
4000 <0 0x15ffe10c 0 0x4>, /* mbox3 clr */
4001 <0 0x15fa502c 0 0x4>, /* mbox3 init */
4002 <0 0x15fff000 0 0x100>, /* mbox4 base */
4003 <0 0x15fff100 0 0x4>, /* mbox4 set */
4004 <0 0x15fff10c 0 0x4>, /* mbox4 clr */
4005 <0 0x15fa5030 0 0x4>; /* mbox4 init */
4006
4007 reg-names = "scp_sram_base",
4008 "scp_cfgreg",
4009 "scp_clkreg",
4010 "scp_cfgreg_core0",
4011 "scp_cfgreg_core1",
4012 "scp_bus_tracker",
4013 "scp_l1creg",
4014 "scp_cfgreg_sec",
4015 "mbox0_base",
4016 "mbox0_set",
4017 "mbox0_clr",
4018 "mbox0_init",
4019 "mbox1_base",
4020 "mbox1_set",
4021 "mbox1_clr",
4022 "mbox1_init",
4023 "mbox2_base",
4024 "mbox2_set",
4025 "mbox2_clr",
4026 "mbox2_init",
4027 "mbox3_base",
4028 "mbox3_set",
4029 "mbox3_clr",
4030 "mbox3_init",
4031 "mbox4_base",
4032 "mbox4_set",
4033 "mbox4_clr",
4034 "mbox4_init";
4035
4036 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4037 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4038 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4039 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4040 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
4041
4042 interrupt-names = "mbox0",
4043 "mbox1",
4044 "mbox2",
4045 "mbox3",
4046 "mbox4";
4047
4048 core_0 = "enable";
4049 scp_sramSize = <0x00020000>;
4050 };
4051
4052 consys: consys@18000000 {
4053 compatible = "mediatek,mt6880-consys";
4054 #thermal-sensor-cells = <0>;
4055 /* conn_infra_rgu */
4056 reg = <0 0x18000000 0 0x1000>,
4057 /* conn_infra_cfg */
4058 <0 0x18001000 0 0x1000>,
4059 /* conn_host_csr_top */
4060 <0 0x18060000 0 0x10000>,
4061 /* infracfg_ao */
4062 <0 0x10001000 0 0x1000>,
4063 /* TOP RGU */
4064 <0 0x10007000 0 0x1000>,
4065 /* SPM */
4066 <0 0x10006000 0 0x1000>,
4067 /* INFRACFG */
4068 <0 0x1020e000 0 0x1000>,
4069 /* conn_wt_slp_ctl_reg */
4070 <0 0x18005000 0 0x1000>,
4071 /* conn_afe_ctl */
4072 <0 0x18003000 0 0x1000>,
4073 /* GPIO */
4074 <0 0x10005000 0 0x1000>,
4075 /* conn_rf_spi_mst_reg */
4076 <0 0x18004000 0 0x1000>,
4077 /* conn_semaphore */
4078 <0 0x18070000 0 0x10000>,
4079 /* conn_top_therm_ctl */
4080 <0 0x18002000 0 0x1000>,
4081 /* IOCFG_BM */
4082 <0 0x11d10000 0 0x1000>,
4083 /* debug_ctrl */
4084 <0 0x1800f000 0 0x1000>,
4085 /* conn_infra_clkgen_on_top */
4086 <0 0x18009000 0 0x1000>,
4087 /* conn_infra_bus_cr */
4088 <0 0x1800e000 0 0x400>,
4089 /* conn_infra_debug_ctrl_ao */
4090 <0 0x1802f000 0 0x430>;
4091 power-domains = <&scpsys MT6890_POWER_DOMAIN_CONN>;
4092 };
4093
4094 gps: gps@18C00000 {
4095 compatible = "mediatek,connac2-gps";
4096 reg = <0 0x18000000 0 0x100000>,
4097 <0 0x18C00000 0 0x100000>,
4098 <0 0x10003304 0 0x4>,
4099 <0 0x1001C000 0 0x4>,
4100 <0 0x1001C030 0 0x4>;
4101 reg-names = "conn_infra_base", "conn_gps_base",
4102 "status_dummy_cr", "tia2_gps_on", "tia2_gps_rc_sel";
4103 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
4104 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
4105 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
4106 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
4107 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
4110 memory-region = <&gps_mem>;
4111 pmic = <&pmic_efuse>;
4112 mtk-vcore-supply = <&dvfsrc_vcore>;
4113 };
4114
4115 odm: odm {
4116 compatible = "simple-bus";
4117 /* reserved for overlay by odm */
4118 };
4119
4120 pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
4121 compatible = "mediatek,pmic_clock_buffer";
4122 mediatek,clkbuf-quantity = <7>;
4123 mediatek,clkbuf-config = <2 1 1 2 0 0 2>;
4124 mediatek,clkbuf-output-impedance = <3 4 3 4 0 0 3>;
4125 mediatek,clkbuf-controls-for-desense = <0 4 0 3 0 0 0>;
4126 mediatek,bblpm-support = "enable";
4127
4128 pwrap-dcxo-en = <0x24 4 0x28 1 0x28 0>;
4129 pwrap-dcxo-conn = <0x5c 0 0x5c 16 0x60 0 0x60 16>;
4130 pwrap-dcxo-nfc = <0x64 0 0x64 16 0x68 0 0x68 16>;
4131
4132 spm-pwr-status = <0x16c 0 0x16c 1>;
4133 spm-io-en = <0x2c 7>;
4134 spm-power-on-val = <0x8 21 0x8 14>;
4135 spm-sck-con = <0xc 24>;
4136 pcm-reg7-rf = <0x10c 21>;
4137
4138 pwrap = <&spmi_bus>;
4139 sleep = <&sleep>;
4140 };
4141 typec_switch: typec_switch {
4142 compatible = "mediatek,typec_switch";
4143 };
4144
4145 afe: mt6880-afe-pcm@11210000 {
4146 compatible = "mediatek,mt6880-sound";
4147 reg = <0 0x11210000 0 0x1000>;
4148 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
4149 i2s3-share = "I2S0";
4150 topckgen = <&topckgen_clk>;
4151 power-domains = <&scpsys MT6890_POWER_DOMAIN_AUDIO>;
4152 clocks = <&audsys_clk CLK_AUDSYS_AFE>,
4153 <&audsys_clk CLK_AUDSYS_DAC>,
4154 <&audsys_clk CLK_AUDSYS_DAC_PREDIS>,
4155 <&audsys_clk CLK_AUDSYS_ADC>,
4156 <&audsys_clk CLK_AUDSYS_22M>,
4157 <&audsys_clk CLK_AUDSYS_24M>,
4158 <&audsys_clk CLK_AUDSYS_APLL_TUNER>,
4159 <&audsys_clk CLK_AUDSYS_APLL2_TUNER>,
4160 <&audsys_clk CLK_AUDSYS_TDM>,
4161 <&audsys_clk CLK_AUDSYS_TML>,
4162 <&infracfg_ao_clk CLK_IFRAO_AUDIO>,
4163 <&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>,
4164 <&topckgen_clk CLK_TOP_AUDIO_SEL>,
4165 <&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
4166 <&topckgen_clk CLK_TOP_MMPLL_D4_D4>,
4167 <&topckgen_clk CLK_TOP_AUD_1_SEL>,
4168 <&topckgen_clk CLK_TOP_APLL1>,
4169 <&topckgen_clk CLK_TOP_AUD_2_SEL>,
4170 <&topckgen_clk CLK_TOP_APLL2>,
4171 <&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
4172 <&topckgen_clk CLK_TOP_APLL1_D8>,
4173 <&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
4174 <&topckgen_clk CLK_TOP_APLL2_D8>,
4175 <&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
4176 <&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
4177 <&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
4178 <&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
4179 <&topckgen_clk CLK_TOP_APLL_TDMOUT_MCK_SEL>,
4180 <&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
4181 <&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
4182 <&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
4183 <&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
4184 <&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
4185 <&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
4186 <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
4187 <&topckgen_clk CLK_TOP_APLL12_CK_DIV_TDMOUT_B>,
4188 <&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
4189 <&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
4190 <&topckgen_clk CLK_TOP_TCK_26M_MX9>;
4191 clock-names = "aud_afe_clk",
4192 "aud_dac_clk",
4193 "aud_dac_predis_clk",
4194 "aud_adc_clk",
4195 "aud_apll22m_clk",
4196 "aud_apll24m_clk",
4197 "aud_apll1_tuner_clk",
4198 "aud_apll2_tuner_clk",
4199 "aud_tdm_clk",
4200 "aud_tml_clk",
4201 "aud_infra_clk",
4202 "mtkaif_26m_clk",
4203 "top_mux_audio",
4204 "top_mux_audio_int",
4205 "top_mainpll_d2_d4",
4206 "top_mux_aud_1",
4207 "top_apll1_ck",
4208 "top_mux_aud_2",
4209 "top_apll2_ck",
4210 "top_mux_aud_eng1",
4211 "top_apll1_d8",
4212 "top_mux_aud_eng2",
4213 "top_apll2_d8",
4214 "top_i2s0_m_sel",
4215 "top_i2s1_m_sel",
4216 "top_i2s2_m_sel",
4217 "top_i2s4_m_sel",
4218 "top_tdm_m_sel",
4219 "top_i2s5_m_sel",
4220 "top_i2s6_m_sel",
4221 "top_apll12_div0",
4222 "top_apll12_div1",
4223 "top_apll12_div2",
4224 "top_apll12_div4",
4225 "top_apll12_divm",
4226 "top_apll12_divb",
4227 "top_apll12_div5",
4228 "top_apll12_div6",
4229 "top_clk26m_clk";
4230 pinctrl-names = "aud_gpio_i2s0_off",
4231 "aud_gpio_i2s0_on",
4232 "aud_gpio_i2s1_off",
4233 "aud_gpio_i2s1_on",
4234 "aud_gpio_i2s2_off",
4235 "aud_gpio_i2s2_on",
4236 "aud_gpio_i2s3_off",
4237 "aud_gpio_i2s3_on",
4238 "aud_gpio_i2s4_off",
4239 "aud_gpio_i2s4_on",
4240 "aud_gpio_i2s5_off",
4241 "aud_gpio_i2s5_on",
4242 "aud_gpio_i2s6_off",
4243 "aud_gpio_i2s6_on",
4244 "aud_gpio_proslic_off",
4245 "aud_gpio_proslic_on",
4246 "aud_gpio_tdm_off",
4247 "aud_gpio_tdm_on",
4248 "extamp-pullhigh",
4249 "extamp-pulllow";
4250 pinctrl-0 = <&aud_gpio_i2s0_off>;
4251 pinctrl-1 = <&aud_gpio_i2s0_on>;
4252 pinctrl-2 = <&aud_gpio_i2s1_off>;
4253 pinctrl-3 = <&aud_gpio_i2s1_on>;
4254 pinctrl-4 = <&aud_gpio_i2s2_off>;
4255 pinctrl-5 = <&aud_gpio_i2s2_on>;
4256 pinctrl-6 = <&aud_gpio_i2s3_off>;
4257 pinctrl-7 = <&aud_gpio_i2s3_on>;
4258 pinctrl-8 = <&aud_gpio_i2s4_off>;
4259 pinctrl-9 = <&aud_gpio_i2s4_on>;
4260 pinctrl-10 = <&aud_gpio_i2s5_off>;
4261 pinctrl-11 = <&aud_gpio_i2s5_on>;
4262 pinctrl-12 = <&aud_gpio_i2s6_off>;
4263 pinctrl-13 = <&aud_gpio_i2s6_on>;
4264 pinctrl-14 = <&aud_gpio_proslic_off>;
4265 pinctrl-15 = <&aud_gpio_proslic_on>;
4266 pinctrl-16 = <&aud_gpio_tdm_off>;
4267 pinctrl-17 = <&aud_gpio_tdm_on>;
4268 pinctrl-18 = <&aud_pins_extamp_high>;
4269 pinctrl-19 = <&aud_pins_extamp_low>;
4270 };
4271 sound: sound {
4272 compatible = "mediatek,mt6880-mt6359-sound";
4273 mediatek,platform = <&afe>;
4274 };
4275
4276 audio_sram@11211000 {
4277 compatible = "mediatek,audio_sram";
4278 reg = <0 0x11211000 0 0x10000>;
4279 prefer_mode = <1>;
4280 mode_size = <0xC000 0x10000>;
4281 block_size = <0x1000>;
4282 };
4283
4284 smart_pa: smart_pa {
4285 };
4286
4287 extcon_usb: extcon_usb {
4288 compatible = "mediatek,extcon-usb";
4289 dev-conn = <&ssusb>;
4290 };
4291};
4292
4293&spmi_bus {
4294 mt6315_5: mt6315@5 {
4295 compatible = "mediatek,mt6315", "mtk,spmi-pmic";
4296 reg = <0x5 SPMI_USID 0xb SPMI_GSID>;
4297 #address-cells = <1>;
4298 #size-cells = <0>;
4299 mt6315_5_regulator: mt6315_5_regulator {
4300 compatible = "mediatek,mt6315_5-regulator";
4301 #interrupt-cells = <2>;
4302 interrupt-controller;
4303 interrupt-parent = <&pio>;
4304 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
4305 };
4306 };
4307
4308 md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
4309 };
4310
4311 md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
4312 };
4313};
4314#include "mt6890-clkao.dtsi"
4315#include "mt6330.dtsi"
4316#include "cust_mt6890_msdc.dtsi"
4317
4318&pmic {
4319 mt63xx_ot_debug: mt63xx-ot-debug {
4320 compatible = "mediatek,mt63xx-ot-debug";
4321 interrupt-parent = <&mt6315_5_regulator>;
4322 /* INT_TEMP_H */
4323 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
4324 };
4325};