Gitiles
Code Review Sign In
192.168.1.100 / T800 / e2381fbede2313f15e12a3dea9726ff3dc828f34 / . / src / kernel / modules / netsys_driver / nat / include / raether.h
blob: 81e27b7239ee1be677c0d2a55bdc3d2a22a3a9d8 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/* Copyright 2016 MediaTek Inc.
2 * Author: Nelson Chang <nelson.chang@mediatek.com>
3 * Author: Carlos Huang <carlos.huang@mediatek.com>
4 * Author: Harry Huang <harry.huang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef RA2882ETHEND_H
16#define RA2882ETHEND_H
17
18#include "raeth_config.h"
19#include "raeth_reg.h"
20#include "ra_dbg_proc.h"
21#include "ra_ioctl.h"
22
23#include <linux/module.h>
24#include <linux/version.h>
25#include <linux/kernel.h>
26#include <linux/types.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/skbuff.h>
30#include <linux/if_vlan.h>
31#include <linux/if_ether.h>
32#include <linux/fs.h>
33#include <linux/mii.h>
34#include <linux/uaccess.h>
35#if defined(CONFIG_RAETH_TSO)
36#include <linux/tcp.h>
37#include <net/ipv6.h>
38#include <linux/ip.h>
39#include <net/ip.h>
40#include <net/tcp.h>
41#include <linux/in.h>
42#include <linux/ppp_defs.h>
43#include <linux/if_pppox.h>
44#endif
45#include <linux/netdevice.h>
46#include <linux/if_vlan.h>
47#include <linux/ppp_defs.h>
48
49/* LRO support */
50#include <linux/inet_lro.h>
51
52#include <linux/delay.h>
53#include <linux/sched.h>
54
55#include <asm-generic/pci-dma-compat.h>
56
57#include <linux/of_device.h>
58#include <linux/of_address.h>
59#include <linux/of_net.h>
60#include <linux/of_irq.h>
61#include <linux/of_gpio.h>
62#include <linux/mfd/syscon.h>
63#include <linux/regmap.h>
64#include <linux/clk.h>
65#include <linux/regulator/consumer.h>
66
67#include <linux/dma-mapping.h>
68
69#if defined(CONFIG_MACH_MT7623)
70#include <linux/delay.h>
71#endif
72#include <linux/kthread.h>
73#include <linux/prefetch.h>
74
75#include <linux/platform_device.h>
76#include <linux/pm_runtime.h>
77
78#if defined(CONFIG_RA_HW_NAT) || defined(CONFIG_RA_HW_NAT_MODULE)
79#include <net/ra_nat.h>
80#endif
81
82#ifndef TRUE
83#define TRUE 1
84#endif
85#ifndef FALSE
86#define FALSE 0
87#endif
88
89#define ETH_GPIO_BASE 0x10005000
90
91#if defined(CONFIG_QDMA_MQ)
92#define GMAC1_TXQ_NUM 3
93#define GMAC1_TXQ_TXD_NUM 512
94#define GMAC1_TXD_NUM (GMAC1_TXQ_NUM * GMAC1_TXQ_TXD_NUM)
95#define GMAC2_TXQ_NUM 1
96#define GMAC2_TXQ_TXD_NUM 128
97#define GMAC2_TXD_NUM (GMAC2_TXQ_NUM * GMAC2_TXQ_TXD_NUM)
98#define NUM_TX_DESC (GMAC1_TXD_NUM + GMAC2_TXD_NUM)
99#define TOTAL_TXQ_NUM (GMAC1_TXQ_NUM + GMAC2_TXQ_NUM)
100#else
101#define TOTAL_TXQ_NUM 2
102#endif
103
104#if defined(CONFIG_MACH_MT7623)
105#define NUM_RX_DESC 2048
106#define NUM_QRX_DESC 16
107#define NUM_PQ_RESV 4
108#define FFA 2048
109#define QUEUE_OFFSET 0x10
110#else
111#define NUM_QRX_DESC 16
112#define NUM_PQ_RESV 4
113#define FFA 512
114#define QUEUE_OFFSET 0x10
115#endif
116
117#if defined(CONFIG_PINCTRL_MT7622)
118#define NUM_PQ 64
119#else
120#define NUM_PQ 16
121#endif
122/* #define NUM_TX_MAX_PROCESS NUM_TX_DESC */
123#define NUM_RX_MAX_PROCESS 16
124
125#define MAX_RX_RING_NUM 4
126#define NUM_LRO_RX_DESC 16
127
128#define MAX_RX_LENGTH 1536
129
130#if defined(CONFIG_SUPPORT_OPENWRT)
131#define DEV_NAME "eth0"
132#define DEV2_NAME "eth1"
133#else
134#define DEV_NAME "eth2"
135#define DEV2_NAME "eth3"
136#endif
137
138#if defined(CONFIG_MACH_MT7623)
139#define GMAC0_OFFSET 0xE000
140#define GMAC2_OFFSET 0xE006
141#else
142#define GMAC0_OFFSET 0x28
143#define GMAC2_OFFSET 0x22
144#endif
145
146#if defined(CONFIG_MACH_MT7623)
147#define IRQ_ENET0 232
148#define IRQ_ENET1 231
149#define IRQ_ENET2 230
150#else
151/* NOTE(Nelson): prom version started from 20150806 */
152#define IRQ_ENET0 255
153#define IRQ_ENET1 256
154#define IRQ_ENET2 257
155#endif
156#define MTK_NAPI_WEIGHT 64
157
158#define RAETH_VERSION "STD_v0.1"
159
160/* MT7623 PSE reset workaround */
161#define FE_RESET_POLLING_MS (5000)
162
163/*LEOPARD POLLING*/
164#define PHY_POLLING_MS (1000)
165#define FE_DEFAULT_LAN_IP "192.168.1.1"
166#define IP4_ADDR_LEN 16
167
168#if defined(CONFIG_SOC_MT7621)
169#define MT_TRIGGER_LOW 0
170#else
171#define MT_TRIGGER_LOW IRQF_TRIGGER_LOW
172#endif
173
174/* This enum allows us to identify how the clock is defined on the array of the
175 * clock in the order
176 */
177enum mtk_clks_map {
178 MTK_CLK_ETHIF,
179 MTK_CLK_ESW,
180 MTK_CLK_GP0,
181 MTK_CLK_GP1,
182 MTK_CLK_GP2,
183 MTK_CLK_SGMII_TX250M,
184 MTK_CLK_SGMII_RX250M,
185 MTK_CLK_SGMII_CDR_REF,
186 MTK_CLK_SGMII_CDR_FB,
187 MTK_CLK_SGMII1_TX250M,
188 MTK_CLK_SGMII1_RX250M,
189 MTK_CLK_SGMII1_CDR_REF,
190 MTK_CLK_SGMII1_CDR_FB,
191 MTK_CLK_TRGPLL,
192 MTK_CLK_SGMIPLL,
193 MTK_CLK_ETH1PLL,
194 MTK_CLK_ETH2PLL,
195 MTK_CLK_FE,
196 MTK_CLK_SGMII_TOP,
197 MTK_CLK_MAX
198};
199
200struct END_DEVICE {
201 struct device *dev;
202 unsigned int tx_cpu_owner_idx0;
203#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
204 unsigned int rx_calc_idx[MAX_RX_RING_NUM];
205#endif
206 unsigned int tx_ring_full;
207 unsigned int tx_full; /* NOTE(Nelso): unused, can remove */
208
209 /* PDMA TX PTR */
210 dma_addr_t phy_tx_ring0;
211
212 /* QDMA TX PTR */
213 struct platform_device *qdma_pdev;
214 /* struct sk_buff *free_skb[NUM_TX_DESC]; */
215 struct sk_buff **free_skb;
216 unsigned int tx_dma_ptr;
217 unsigned int tx_cpu_ptr;
218 unsigned int tx_cpu_idx;
219 unsigned int rls_cpu_idx;
220 /* atomic_t free_txd_num[TOTAL_TXQ_NUM]; */
221 atomic_t *free_txd_num;
222 /* unsigned int free_txd_head[TOTAL_TXQ_NUM]; */
223 /* unsigned int free_txd_tail[TOTAL_TXQ_NUM]; */
224 unsigned int *free_txd_head;
225 unsigned int *free_txd_tail;
226 struct QDMA_txdesc *txd_pool;
227 dma_addr_t phy_txd_pool;
228 /* unsigned int txd_pool_info[NUM_TX_DESC]; */
229 unsigned int *txd_pool_info;
230 struct QDMA_txdesc *free_head;
231 unsigned int phy_free_head;
232 unsigned int *free_page_head;
233 dma_addr_t phy_free_page_head;
234 struct PDMA_rxdesc *qrx_ring;
235 dma_addr_t phy_qrx_ring;
236
237 /* TSO */
238 unsigned int skb_txd_num;
239
240 /* MT7623 workaround */
241 struct work_struct reset_task;
242
243 /* workqueue_bh */
244 struct work_struct rx_wq;
245
246 /* tasklet_bh */
247 struct tasklet_struct rx_tasklet;
248
249 /* struct sk_buff *skb_free[NUM_TX_DESC]; */
250 struct sk_buff **skb_free;
251 unsigned int free_idx;
252
253 struct net_device_stats stat; /* The new statistics table. */
254 spinlock_t page_lock; /* spin_lock for cr access critial section */
255 spinlock_t irq_lock; /* spin_lock for isr critial section */
256 spinlock_t mdio_lock; /* spin_lock for mdio reg access */
257 struct PDMA_txdesc *tx_ring0;
258 struct PDMA_rxdesc *rx_ring[MAX_RX_RING_NUM];
259 dma_addr_t phy_rx_ring[MAX_RX_RING_NUM];
260
261 /* void *netrx_skb_data[MAX_RX_RING_NUM][NUM_RX_DESC]; */
262 void **netrx_skb_data[MAX_RX_RING_NUM];
263
264 /* struct sk_buff *netrx0_skbuf[NUM_RX_DESC]; */
265 /*struct sk_buff **netrx0_skbuf;*/
266 void **netrx0_skb_data;
267 /* napi */
268 struct napi_struct napi;
269 struct napi_struct napi_rx;
270 struct napi_struct napi_rx_rss0;
271 struct napi_struct napi_rx_rss1;
272 struct napi_struct napi_rx_rss2;
273 struct napi_struct napi_rx_rss3;
274 struct napi_struct napi_tx;
275 struct net_device dummy_dev;
276
277 /* clock control */
278 struct clk *clks[MTK_CLK_MAX];
279
280 /* gsw device node */
281 struct device_node *switch_np;
282
283 /* GE1 support */
284 struct net_device *netdev;
285 /* GE2 support */
286 struct net_device *pseudo_dev;
287 unsigned int is_pseudo;
288
289 struct mii_if_info mii_info;
290 struct lro_counters lro_counters;
291 struct net_lro_mgr lro_mgr;
292 struct net_lro_desc lro_arr[8];
293 struct vlan_group *vlgrp;
294
295 /* virtual base addr from device tree */
296 void __iomem *ethdma_sysctl_base;
297
298 unsigned int irq0;
299 unsigned int irq1;
300 unsigned int irq2;
301 unsigned int irq3;
302 unsigned int esw_irq;
303 void __iomem *fe_tx_int_status;
304 void __iomem *fe_tx_int_enable;
305 void __iomem *fe_rx_int_status;
306 void __iomem *fe_rx_int_enable;
307
308 unsigned int features;
309 unsigned int chip_name;
310 unsigned int architecture;
311
312 /* IP address */
313 char lan_ip4_addr[IP4_ADDR_LEN];
314
315 /* Function pointers */
316 int (*ei_start_xmit)(struct sk_buff *skb, struct net_device *netdev,
317 int gmac_no);
318 int (*ei_xmit_housekeeping)(struct net_device *netdev, int budget);
319 int (*ei_eth_recv)(struct net_device *dev,
320 struct napi_struct *napi,
321 int budget);
322 int (*ei_eth_recv_rss0)(struct net_device *dev,
323 struct napi_struct *napi,
324 int budget);
325 int (*ei_eth_recv_rss1)(struct net_device *dev,
326 struct napi_struct *napi,
327 int budget);
328 int (*ei_eth_recv_rss2)(struct net_device *dev,
329 struct napi_struct *napi,
330 int budget);
331 int (*ei_eth_recv_rss3)(struct net_device *dev,
332 struct napi_struct *napi,
333 int budget);
334 int (*ei_fill_tx_desc)(struct net_device *dev,
335 unsigned long *tx_cpu_owner_idx,
336 struct sk_buff *skb, int gmac_no);
337
338 /* MT7623 PSE reset workaround */
339 struct task_struct *kreset_task;
340 struct task_struct *kphy_poll_task;
341 unsigned int fe_reset_times;
342 unsigned int tx_mask;
343 unsigned int rx_mask;
344 unsigned int *rls_cnt;
345};
346
347#ifdef CONFIG_INET_LRO
348static inline void ei_lro_flush_all(struct net_lro_mgr *lro_mgr)
349{
350 lro_flush_all(lro_mgr);
351}
352#else
353static inline void ei_lro_flush_all(struct net_lro_mgr *lro_mgr)
354{
355}
356#endif
357
358struct net_device_stats *ra_get_stats(struct net_device *dev);
359
360int ei_open(struct net_device *dev);
361int ei_close(struct net_device *dev);
362
363int ra2882eth_init(void);
364void ra2882eth_cleanup_module(void);
365
366u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
367u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
368u32 mii_mgr_cl45_set_address(u32 port_num, u32 dev_addr, u32 reg_addr);
369u32 mii_mgr_read_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
370 u32 *read_data);
371u32 mii_mgr_write_cl45(u32 port_num, u32 dev_addr, u32 reg_addr,
372 u32 write_data);
373
374/* HNAT functions */
375#if defined(CONFIG_RA_NAT_NONE)
376static int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
377static int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
378#else
379extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
380extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
381#endif
382
383/* PDMA functions */
384int fe_pdma_wait_dma_idle(void);
385int fe_pdma_rx_dma_init(struct net_device *dev);
386int fe_pdma_tx_dma_init(struct net_device *dev);
387void fe_pdma_rx_dma_deinit(struct net_device *dev);
388void fe_pdma_tx_dma_deinit(struct net_device *dev);
389void set_fe_pdma_glo_cfg(void);
390int ei_pdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
391 int gmac_no);
392int ei_pdma_xmit_housekeeping(struct net_device *netdev,
393 int budget);
394int fe_fill_tx_desc(struct net_device *dev,
395 unsigned long *tx_cpu_owner_idx,
396 struct sk_buff *skb,
397 int gmac_no);
398int fe_fill_tx_desc_tso(struct net_device *dev,
399 unsigned long *tx_cpu_owner_idx,
400 struct sk_buff *skb,
401 int gmac_no);
402void fe_set_sw_lro_my_ip(char *lan_ip_addr);
403
404/* QDMA functions */
405int fe_qdma_wait_dma_idle(void);
406int fe_qdma_rx_dma_init(struct net_device *dev);
407int fe_qdma_tx_dma_init(struct net_device *dev);
408void fe_qdma_rx_dma_deinit(struct net_device *dev);
409void fe_qdma_tx_dma_deinit(struct net_device *dev);
410void set_fe_qdma_glo_cfg(void);
411int ei_qdma_start_xmit(struct sk_buff *skb, struct net_device *dev,
412 int gmac_no);
413int ei_qdma_xmit_housekeeping(struct net_device *netdev, int budget);
414int ei_qdma_ioctl(struct net_device *dev, struct ifreq *ifr,
415 struct qdma_ioctl_data *ioctl_data);
416int ephy_ioctl(struct net_device *dev, struct ifreq *ifr,
417 struct ephy_ioctl_data *ioctl_data);
418/* HW LRO functions */
419int fe_hw_lro_init(struct net_device *dev);
420void fe_hw_lro_deinit(struct net_device *dev);
421int fe_hw_lro_recv(struct net_device *dev,
422 struct napi_struct *napi,
423 int budget);
424void fe_set_hw_lro_my_ip(char *lan_ip_addr);
425
426int fe_rss_4ring_init(struct net_device *dev);
427void fe_rss_4ring_deinit(struct net_device *dev);
428int fe_rss_2ring_init(struct net_device *dev);
429void fe_rss_2ring_deinit(struct net_device *dev);
430int fe_rss0_recv(struct net_device *dev,
431 struct napi_struct *napi,
432 int budget);
433int fe_rss1_recv(struct net_device *dev,
434 struct napi_struct *napi,
435 int budget);
436int fe_rss2_recv(struct net_device *dev,
437 struct napi_struct *napi,
438 int budget);
439int fe_rss3_recv(struct net_device *dev,
440 struct napi_struct *napi,
441 int budget);
442static inline void *raeth_alloc_skb_data(size_t size, gfp_t flags)
443{
444#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
445 return kmalloc(size, flags);
446#else
447 return netdev_alloc_frag(size);
448#endif
449}
450
451static inline void raeth_free_skb_data(void *addr)
452{
453#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
454 kfree(addr);
455#else
456 skb_free_frag(addr);
457#endif
458}
459
460static inline struct sk_buff *raeth_build_skb(void *data,
461 unsigned int frag_size)
462{
463#ifdef CONFIG_ETH_SLAB_ALLOC_SKB
464 return build_skb(data, 0);
465#else
466 return build_skb(data, frag_size);
467#endif
468}
469
470extern u32 gmac1_txq_num;
471extern u32 gmac1_txq_txd_num;
472extern u32 gmac1_txd_num;
473extern u32 gmac2_txq_num;
474extern u32 gmac2_txq_txd_num;
475extern u32 gmac2_txd_num;
476extern u32 num_rx_desc;
477extern u32 num_tx_max_process;
478extern u32 num_tx_desc;
479extern u32 total_txq_num;
480extern u32 mac_to_gigaphy_mode_addr;
481extern u32 mac_to_gigaphy_mode_addr2;
482#endif