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192.168.1.100 / T800 / ef0c61a9eff718df29b0497ab8c346f7698fc85a / . / src / kernel / linux / v4.19 / drivers / clk / mediatek / clk-mt6779-aud.c
blob: 6bbc58ef4b78cda37e0562b8fcf2948ec6347f34 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
19 .id = _id, \
20 .name = _name, \
21 .parent_name = _parent, \
22 .regs = &audio0_cg_regs, \
23 .shift = _shift, \
24 .ops = &mtk_clk_gate_ops_no_setclr, \
25 }
26
27#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
28 .id = _id, \
29 .name = _name, \
30 .parent_name = _parent, \
31 .regs = &audio1_cg_regs, \
32 .shift = _shift, \
33 .ops = &mtk_clk_gate_ops_no_setclr, \
34 }
35
36
37
38static const struct mtk_gate_regs audio0_cg_regs = {
39 .set_ofs = 0x0,
40 .clr_ofs = 0x0,
41 .sta_ofs = 0x0,
42};
43
44static const struct mtk_gate_regs audio1_cg_regs = {
45 .set_ofs = 0x4,
46 .clr_ofs = 0x4,
47 .sta_ofs = 0x4,
48};
49
50static const struct mtk_gate audio_clks[] = {
51 /* AUDIO0 */
52 GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel",
53 2),
54 GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel",
55 8),
56 GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel",
57 9),
58 GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "aud_eng2_sel",
59 18),
60 GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "aud_eng1_sel",
61 19),
62 GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel",
63 20),
64 GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel",
65 24),
66 GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel",
67 25),
68 GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "audio_sel",
69 26),
70 GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel",
71 27),
72 GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel",
73 28),
74 /* AUDIO1: hf_faudio_ck/hf_faud_engen1_ck/hf_faud_engen2_ck */
75 GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk", "audio_sel",
76 4),
77 GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk", "audio_sel",
78 5),
79 GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk", "audio_sel",
80 6),
81 GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk", "audio_sel",
82 7),
83 GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk", "audio_sel",
84 8),
85
86 GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s", "audio_sel",
87 12),
88 GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1", "audio_sel",
89 13),
90 GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2", "audio_sel",
91 14),
92 GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires", "audio_h_sel",
93 15),
94 GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "audio_h_sel",
95 16),
96 GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "audio_h_sel",
97 17),
98
99 GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc", "audio_sel",
100 20),
101 GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
102 "audio_h_sel",
103 21),
104 GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
105 28),
106 GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "audio_sel",
107 29),
108 GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "audio_sel",
109 30),
110 GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "audio_h_sel",
111 31),
112};
113
114static const struct of_device_id of_match_clk_mt6779_aud[] = {
115 { .compatible = "mediatek,mt6779-audio", },
116 {}
117};
118
119static int clk_mt6779_aud_probe(struct platform_device *pdev)
120{
121 struct clk_onecell_data *clk_data;
122 struct device_node *node = pdev->dev.of_node;
123
124 clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
125
126 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
127 clk_data);
128
129 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
130}
131
132static struct platform_driver clk_mt6779_aud_drv = {
133 .probe = clk_mt6779_aud_probe,
134 .driver = {
135 .name = "clk-mt6779-aud",
136 .of_match_table = of_match_clk_mt6779_aud,
137 },
138};
139
140builtin_platform_driver(clk_mt6779_aud_drv);