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192.168.1.100 / T800 / fbdee0f7567a076a99dc7ff764a60ff4706d93be / . / src / kernel / linux / v4.19 / drivers / mmc / host / mtk-legacy-sdio.h
blob: da35f08d5bd3970f1e344fd5342e6221dbf646c5 [file] [log] [blame]
xjb04a4022021-11-25 15:01:52 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7#define MAX_BD_NUM 1024
8
9/*--------------------------------------------------------------------------*/
10/* Common Definition */
11/*--------------------------------------------------------------------------*/
12#define MSDC_BUS_1BITS 0x0
13#define MSDC_BUS_4BITS 0x1
14#define MSDC_BUS_8BITS 0x2
15
16#define MSDC_BURST_64B 0x6
17
18/*--------------------------------------------------------------------------*/
19/* Register Offset */
20/*--------------------------------------------------------------------------*/
21#define MSDC_CFG 0x0
22#define MSDC_IOCON 0x04
23#define MSDC_PS 0x08
24#define MSDC_INT 0x0c
25#define MSDC_INTEN 0x10
26#define MSDC_FIFOCS 0x14
27#define MSDC_TXDATA 0x18
28#define MSDC_RXDATA 0x1c
29#define SDC_CFG 0x30
30#define SDC_CMD 0x34
31#define SDC_ARG 0x38
32#define SDC_STS 0x3c
33#define SDC_RESP0 0x40
34#define SDC_RESP1 0x44
35#define SDC_RESP2 0x48
36#define SDC_RESP3 0x4c
37#define SDC_BLK_NUM 0x50
38#define EMMC_IOCON 0x7c
39#define SDC_ACMD_RESP 0x80
40#define MSDC_DMA_SA 0x90
41#define MSDC_DMA_CTRL 0x98
42#define MSDC_DMA_CFG 0x9c
43#define MSDC_DBG_SEL 0xa0
44#define MSDC_DBG_OUT 0xa4
45#define MSDC_DMA_LEN 0xa8
46#define MSDC_PATCH_BIT0 0xb0
47#define MSDC_PATCH_BIT1 0xb4
48#define MSDC_PATCH_BIT2 0xb8
49#define DAT0_TUNE_CRC 0xc0
50#define DAT1_TUNE_CRC 0xc4
51#define DAT2_TUNE_CRC 0xc8
52#define DAT3_TUNE_CRC 0xcc
53#define CMD_TUNE_CRC 0xd0
54#define SDIO_TUNE_WIND 0xd4
55#define MSDC_PAD_TUNE0 0xf0
56#define MSDC_PAD_TUNE1 0xf4
57#define MSDC_DAT_RDDLY0 0xf8
58#define MSDC_DAT_RDDLY1 0xfc
59#define MSDC_DAT_RDDLY2 0x100
60#define MSDC_DAT_RDDLY3 0x104
61#define MSDC_HW_DBG 0x110
62#define MSDC_VERSION 0x114
63#define MSDC_ECO_VER 0x118
64#define EMMC50_PAD_CTL0 0x180
65#define EMMC50_PAD_DS_CTL0 0x184
66#define EMMC50_PAD_DS_TUNE 0x188
67#define EMMC50_PAD_CMD_TUNE 0x18c
68#define EMMC50_PAD_DAT01_TUNE 0x190
69#define EMMC50_PAD_DAT23_TUNE 0x194
70#define EMMC50_PAD_DAT45_TUNE 0x198
71#define EMMC50_PAD_DAT67_TUNE 0x19c
72#define EMMC51_CFG0 0x204
73#define EMMC50_CFG0 0x208
74#define EMMC50_CFG1 0x20c
75#define EMMC50_CFG2 0x21c
76#define EMMC50_CFG3 0x220
77#define EMMC50_CFG4 0x224
78#define MSDC_SDC_FIFO_CFG 0x228
79
80#define MAX_REGISTER_ADDR 0x228
81
82/*--------------------------------------------------------------------------*/
83/*Top Register Offset */
84/*--------------------------------------------------------------------------*/
85#define MSDC_TOP_CONTROL (0x00)
86#define MSDC_TOP_CMD (0x04)
87#define MSDC_TOP_PAD_CTRL0 (0x08)
88#define MSDC_TOP_PAD_DS_TUNE (0x0c)
89#define MSDC_TOP_PAD_DAT0_TUNE (0x10)
90#define MSDC_TOP_PAD_DAT1_TUNE (0x14)
91#define MSDC_TOP_PAD_DAT2_TUNE (0x18)
92#define MSDC_TOP_PAD_DAT3_TUNE (0x1c)
93
94/*--------------------------------------------------------------------------*/
95/* Register Mask */
96/*--------------------------------------------------------------------------*/
97
98/* MSDC_CFG mask */
99#define MSDC_CFG_MODE (0x1 << 0) /* RW */
100#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
101#define MSDC_CFG_RST (0x1 << 2) /* RW */
102#define MSDC_CFG_PIO (0x1 << 3) /* RW */
103#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
104#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
105#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
106#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
107#define MSDC_CFG_CKDIV (0xfff << 8) /* RW */
108#define MSDC_CFG_CKDIV_BITS (12)
109#define MSDC_CFG_CKMOD (0x3 << 20) /* RW */
110#define MSDC_CFG_CKMOD_BITS (2)
111#define MSDC_CFG_HS400_CK_MODE (0x1 << 22) /* RW */
112#define MSDC_CFG_START_BIT (0x3 << 23) /* RW */
113#define MSDC_CFG_SCLK_STOP_DDR (0x1 << 25) /* RW */
114#define MSDC_CFG_DVFS_EN (0x1 << 30) /* RW */
115
116/* MSDC_IOCON mask */
117#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
118#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
119#define MSDC_IOCON_R_D_SMPL (0x1 << 2) /* RW */
120#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
121#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
122#define MSDC_IOCON_R_D_SMPL_SEL (0x1 << 5) /* RW */
123#define MSDC_IOCON_W_D_SMPL (0x1 << 8) /* RW */
124#define MSDC_IOCON_W_D_SMPL_SEL (0x1 << 9) /* RW */
125#define MSDC_IOCON_W_D0SPL (0x1 << 10) /* RW */
126#define MSDC_IOCON_W_D1SPL (0x1 << 11) /* RW */
127#define MSDC_IOCON_W_D2SPL (0x1 << 12) /* RW */
128#define MSDC_IOCON_W_D3SPL (0x1 << 13) /* RW */
129#define MSDC_IOCON_R_D0SPL (0x1 << 16) /* RW */
130#define MSDC_IOCON_R_D1SPL (0x1 << 17) /* RW */
131#define MSDC_IOCON_R_D2SPL (0x1 << 18) /* RW */
132#define MSDC_IOCON_R_D3SPL (0x1 << 19) /* RW */
133#define MSDC_IOCON_R_D4SPL (0x1 << 20) /* RW */
134#define MSDC_IOCON_R_D5SPL (0x1 << 21) /* RW */
135#define MSDC_IOCON_R_D6SPL (0x1 << 22) /* RW */
136#define MSDC_IOCON_R_D7SPL (0x1 << 23) /* RW */
137
138/* MSDC_PS mask */
139#define MSDC_PS_CDEN (0x1 << 0) /* RW */
140#define MSDC_PS_CDSTS (0x1 << 1) /* R */
141#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
142#define MSDC_PS_DAT (0xff << 16) /* R */
143#define MSDC_PS_DATA1 (0x1 << 17) /* R */
144#define MSDC_PS_CMD (0x1 << 24) /* R */
145#define MSDC_PS_WP (0x1 << 31) /* R */
146
147/* MSDC_INT mask */
148#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
149#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
150#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
151#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
152#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
153#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
154#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
155#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
156#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
157#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
158#define MSDC_INT_CSTA (0x1 << 11) /* R */
159#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
160#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
161#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
162#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
163#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
164#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
165#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
166#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
167
168/* MSDC_INTEN mask */
169#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
170#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
171#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
172#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
173#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
174#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
175#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
176#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
177#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
178#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
179#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
180#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
181#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
182#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
183#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
184#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
185#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
186#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
187#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
188
189/* MSDC_FIFOCS mask */
190#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
191#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
192#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
193
194/* SDC_CFG mask */
195#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
196#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
197#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
198#define SDC_CFG_SDIO (0x1 << 19) /* RW */
199#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
200#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
201#define SDC_CFG_DTOC (0xff << 24) /* RW */
202
203/* SDC_STS mask */
204#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
205#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
206#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
207
208/* MSDC_DMA_CTRL mask */
209#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
210#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
211#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
212#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
213#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
214#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
215
216/* MSDC_DMA_CFG mask */
217#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
218#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
219#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
220#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
221#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
222
223/* MSDC_PATCH_BIT0 mask */
224#define MSDC_PB0_RESV1 (0x1 << 0)
225#define MSDC_PB0_EN_8BITSUP (0x1 << 1)
226#define MSDC_PB0_DIS_RECMDWR (0x1 << 2)
227#define MSDC_PB0_RD_DAT_SEL (0x1 << 3)
228#define MSDC_PB0_RESV2 (0x3 << 4)
229#define MSDC_PB0_DESCUP (0x1 << 6)
230#define MSDC_PB0_INT_DAT_LATCH_CK_SEL (0x7 << 7)
231#define MSDC_PB0_CKGEN_MSDC_DLY_SEL (0x1F<<10)
232#define MSDC_PB0_FIFORD_DIS (0x1 << 15)
233#define MSDC_PB0_BLKNUM_SEL (0x1 << 16)
234#define MSDC_PB0_SDIO_INTCSEL (0x1 << 17)
235#define MSDC_PB0_SDC_BSYDLY (0xf << 18)
236#define MSDC_PB0_SDC_WDOD (0xf << 22)
237#define MSDC_PB0_CMDIDRTSEL (0x1 << 26)
238#define MSDC_PB0_CMDFAILSEL (0x1 << 27)
239#define MSDC_PB0_SDIO_INTDLYSEL (0x1 << 28)
240#define MSDC_PB0_SPCPUSH (0x1 << 29)
241#define MSDC_PB0_DETWR_CRCTMO (0x1 << 30)
242#define MSDC_PB0_EN_DRVRSP (0x1UL << 31)
243
244/* MSDC_PATCH_BIT1 mask */
245#define MSDC_PB1_WRDAT_CRCS_TA_CNTR (0x7 << 0)
246#define MSDC_PB1_CMD_RSP_TA_CNTR (0x7 << 3)
247#define MSDC_PB1_GET_BUSY_MA (0x1 << 6)
248#define MSDC_PB1_GET_CRC_MA (0x1 << 7)
249#define MSDC_PB1_STOP_DLY_SEL (0xf << 8)
250#define MSDC_PB1_BIAS_EN18IO_28NM (0x1 << 12)
251#define MSDC_PB1_BIAS_EXT_28NM (0x1 << 13)
252#define MSDC_PB1_RESV2 (0x1 << 14)
253#define MSDC_PB1_RESET_GDMA (0x1 << 15)
254#define MSDC_PB1_SINGLE_BURST (0x1 << 16)
255#define MSDC_PB1_FROCE_STOP (0x1 << 17)
256#define MSDC_PB1_POP_MARK_WATER (0x1 << 19)
257#define MSDC_PB1_STATE_CLEAR (0x1 << 20)
258#define MSDC_PB1_DCM_EN (0x1 << 21)
259#define MSDC_PB1_AXI_WRAP_CKEN (0x1 << 22)
260#define MSDC_PB1_CKCLK_GDMA_EN (0x1 << 23)
261#define MSDC_PB1_CKSPCEN (0x1 << 24)
262#define MSDC_PB1_CKPSCEN (0x1 << 25)
263#define MSDC_PB1_CKVOLDETEN (0x1 << 26)
264#define MSDC_PB1_CKACMDEN (0x1 << 27)
265#define MSDC_PB1_CKSDEN (0x1 << 28)
266#define MSDC_PB1_CKWCTLEN (0x1 << 29)
267#define MSDC_PB1_CKRCTLEN (0x1 << 30)
268#define MSDC_PB1_CKSHBFFEN (0x1UL << 31)
269
270/* MSDC_PATCH_BIT2 mask */
271#define MSDC_PB2_ENHANCEGPD (0x1 << 0)
272#define MSDC_PB2_SUPPORT64G (0x1 << 1)
273#define MSDC_PB2_RESPWAITCNT (0x3 << 2)
274#define MSDC_PB2_CFGRDATCNT (0x1f << 4)
275#define MSDC_PB2_CFGRDAT (0x1 << 9)
276#define MSDC_PB2_INTCRESPSEL (0x1 << 11)
277#define MSDC_PB2_CFGRESPCNT (0x7 << 12)
278#define MSDC_PB2_CFGRESP (0x1 << 15)
279#define MSDC_PB2_RESPSTENSEL (0x7 << 16)
280#define MSDC_PB2_POPENCNT (0xf << 20)
281#define MSDC_PB2_CFG_CRCSTS_SEL (0x1 << 24)
282#define MSDC_PB2_CFGCRCSTSEDGE (0x1 << 25)
283#define MSDC_PB2_CFGCRCSTSCNT (0x3 << 26)
284#define MSDC_PB2_CFGCRCSTS (0x1 << 28)
285#define MSDC_PB2_CRCSTSENSEL (0x7UL << 29)
286
287#define MSDC_MASK_ACMD53_CRC_ERR_INTR (0x1<<4)
288#define MSDC_ACMD53_FAIL_ONE_SHOT (0X1<<5)
289
290/* MSDC_PAD_TUNE mask */
291#define MSDC_PAD_TUNE0_DATWRDLY (0x1F << 0) /* RW */
292#define MSDC_PAD_TUNE0_DELAYEN (0x1 << 7) /* RW */
293#define MSDC_PAD_TUNE0_DATRRDLY (0x1F << 8) /* RW */
294#define MSDC_PAD_TUNE0_DATRRDLYSEL (0x1 << 13) /* RW */
295#define MSDC_PAD_TUNE0_RXDLYSEL (0x1 << 15) /* RW */
296#define MSDC_PAD_TUNE0_CMDRDLY (0x1F << 16) /* RW */
297#define MSDC_PAD_TUNE0_CMDRRDLYSEL (0x1 << 21) /* RW */
298#define MSDC_PAD_TUNE0_CMDRRDLY (0x1FUL << 22) /* RW */
299#define MSDC_PAD_TUNE0_CLKTXDLY (0x1FUL << 27) /* RW */
300
301/* MSDC_PAD_TUNE1 mask */
302#define MSDC_PAD_TUNE1_DATRRDLY2 (0x1F << 8) /* RW */
303#define MSDC_PAD_TUNE1_DATRRDLY2SEL (0x1 << 13) /* RW */
304#define MSDC_PAD_TUNE1_CMDRDLY2 (0x1F << 16) /* RW */
305#define MSDC_PAD_TUNE1_CMDRRDLY2SEL (0x1 << 21) /* RW */
306
307/* MSDC_DAT_RDDLY0/1/2/3 mask */
308#define MSDC_DAT_RDDLY0_D3 (0x1F << 0) /* RW */
309#define MSDC_DAT_RDDLY0_D2 (0x1F << 8) /* RW */
310#define MSDC_DAT_RDDLY0_D1 (0x1F << 16) /* RW */
311#define MSDC_DAT_RDDLY0_D0 (0x1FUL << 24) /* RW */
312
313#define MSDC_DAT_RDDLY1_D7 (0x1F << 0) /* RW */
314#define MSDC_DAT_RDDLY1_D6 (0x1F << 8) /* RW */
315#define MSDC_DAT_RDDLY1_D5 (0x1F << 16) /* RW */
316#define MSDC_DAT_RDDLY1_D4 (0x1FUL << 24) /* RW */
317
318#define MSDC_DAT_RDDLY2_D3 (0x1F << 0) /* RW */
319#define MSDC_DAT_RDDLY2_D2 (0x1F << 8) /* RW */
320#define MSDC_DAT_RDDLY2_D1 (0x1F << 16) /* RW */
321#define MSDC_DAT_RDDLY2_D0 (0x1FUL << 24) /* RW */
322
323#define MSDC_DAT_RDDLY3_D7 (0x1F << 0) /* RW */
324#define MSDC_DAT_RDDLY3_D6 (0x1F << 8) /* RW */
325#define MSDC_DAT_RDDLY3_D5 (0x1F << 16) /* RW */
326#define MSDC_DAT_RDDLY3_D4 (0x1FUL << 24) /* RW */
327
328/* MSDC_HW_DBG_SEL mask */
329#define MSDC_HW_DBG0_SEL (0xFF << 0)
330#define MSDC_HW_DBG1_SEL (0x3F << 8)
331#define MSDC_HW_DBG2_SEL (0xFF << 16)
332#define MSDC_HW_DBG3_SEL (0x3F << 24)
333#define MSDC_HW_DBG_WRAPTYPE_SEL (0x1 << 30)
334
335/* MSDC_PATCH_BIT mask */
336#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
337#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
338#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
339#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
340#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
341#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
342#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
343#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
344#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
345#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
346#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
347#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
348
349/* MSDC_PATCH_BIT1 mask */
350#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 0)
351#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 3)
352
353/* MSDC_PAD_TUNE mask */
354#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
355#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
356#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
357#define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
358#define MSDC_PAD_TUNE_CLKTXDLY (0x1f << 27) /* RW */
359
360#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
361#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
362#define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
363
364/* MSDC_EMMC50_PAD_CTL0 mask*/
365#define MSDC_EMMC50_PAD_CTL0_DCCSEL (0x1 << 0)
366#define MSDC_EMMC50_PAD_CTL0_HLSEL (0x1 << 1)
367#define MSDC_EMMC50_PAD_CTL0_DLP0 (0x3 << 2)
368#define MSDC_EMMC50_PAD_CTL0_DLN0 (0x3 << 4)
369#define MSDC_EMMC50_PAD_CTL0_DLP1 (0x3 << 6)
370#define MSDC_EMMC50_PAD_CTL0_DLN1 (0x3 << 8)
371
372/* MSDC_EMMC50_PAD_DS_CTL0 mask */
373#define MSDC_EMMC50_PAD_DS_CTL0_SR (0x1 << 0)
374#define MSDC_EMMC50_PAD_DS_CTL0_R0 (0x1 << 1)
375#define MSDC_EMMC50_PAD_DS_CTL0_R1 (0x1 << 2)
376#define MSDC_EMMC50_PAD_DS_CTL0_PUPD (0x1 << 3)
377#define MSDC_EMMC50_PAD_DS_CTL0_IES (0x1 << 4)
378#define MSDC_EMMC50_PAD_DS_CTL0_SMT (0x1 << 5)
379#define MSDC_EMMC50_PAD_DS_CTL0_RDSEL (0x3F << 6)
380#define MSDC_EMMC50_PAD_DS_CTL0_TDSEL (0xf << 12)
381#define MSDC_EMMC50_PAD_DS_CTL0_DRV (0x7 << 16)
382
383/* EMMC50_PAD_DS_TUNE mask */
384#define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL (0x1 << 0)
385#define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1)
386#define MSDC_EMMC50_PAD_DS_TUNE_DLY1 (0x1F << 2)
387#define MSDC_EMMC50_PAD_DS_TUNE_DLY2 (0x1F << 7)
388#define MSDC_EMMC50_PAD_DS_TUNE_DLY3 (0x1F << 12)
389
390/* EMMC50_PAD_CMD_TUNE mask */
391#define MSDC_EMMC50_PAD_CMD_TUNE_DLY3SEL (0x1 << 0)
392#define MSDC_EMMC50_PAD_CMD_TUNE_RXDLY3 (0x1F << 1)
393#define MSDC_EMMC50_PAD_CMD_TUNE_TXDLY (0x1F << 6)
394
395/* EMMC50_PAD_DAT01_TUNE mask */
396#define MSDC_EMMC50_PAD_DAT0_RXDLY3SEL (0x1 << 0)
397#define MSDC_EMMC50_PAD_DAT0_RXDLY3 (0x1F << 1)
398#define MSDC_EMMC50_PAD_DAT0_TXDLY (0x1F << 6)
399#define MSDC_EMMC50_PAD_DAT1_RXDLY3SEL (0x1 << 16)
400#define MSDC_EMMC50_PAD_DAT1_RXDLY3 (0x1F << 17)
401#define MSDC_EMMC50_PAD_DAT1_TXDLY (0x1F << 22)
402
403/* EMMC50_PAD_DAT23_TUNE mask */
404#define MSDC_EMMC50_PAD_DAT2_RXDLY3SEL (0x1 << 0)
405#define MSDC_EMMC50_PAD_DAT2_RXDLY3 (0x1F << 1)
406#define MSDC_EMMC50_PAD_DAT2_TXDLY (0x1F << 6)
407#define MSDC_EMMC50_PAD_DAT3_RXDLY3SEL (0x1 << 16)
408#define MSDC_EMMC50_PAD_DAT3_RXDLY3 (0x1F << 17)
409#define MSDC_EMMC50_PAD_DAT3_TXDLY (0x1F << 22)
410
411/* EMMC50_PAD_DAT45_TUNE mask */
412#define MSDC_EMMC50_PAD_DAT4_RXDLY3SEL (0x1 << 0)
413#define MSDC_EMMC50_PAD_DAT4_RXDLY3 (0x1F << 1)
414#define MSDC_EMMC50_PAD_DAT4_TXDLY (0x1F << 6)
415#define MSDC_EMMC50_PAD_DAT5_RXDLY3SEL (0x1 << 16)
416#define MSDC_EMMC50_PAD_DAT5_RXDLY3 (0x1F << 17)
417#define MSDC_EMMC50_PAD_DAT5_TXDLY (0x1F << 22)
418
419/* EMMC50_PAD_DAT67_TUNE mask */
420#define MSDC_EMMC50_PAD_DAT6_RXDLY3SEL (0x1 << 0)
421#define MSDC_EMMC50_PAD_DAT6_RXDLY3 (0x1F << 1)
422#define MSDC_EMMC50_PAD_DAT6_TXDLY (0x1F << 6)
423#define MSDC_EMMC50_PAD_DAT7_RXDLY3SEL (0x1 << 16)
424#define MSDC_EMMC50_PAD_DAT7_RXDLY3 (0x1F << 17)
425#define MSDC_EMMC50_PAD_DAT7_TXDLY (0x1F << 22)
426
427/* EMMC51_CFG0 mask */
428#define MSDC_EMMC51_CFG_CMDQEN (0x1 << 0)
429#define MSDC_EMMC51_CFG_NUM (0x3F << 1)
430#define MSDC_EMMC51_CFG_RSPTYPE (0x7 << 7)
431#define MSDC_EMMC51_CFG_DTYPE (0x3 << 10)
432#define MSDC_EMMC51_CFG_RDATCNT (0x3FF << 12)
433#define MSDC_EMMC51_CFG_WDATCNT (0x3FF << 22)
434
435/* EMMC50_CFG0 mask */
436#define MSDC_EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)
437#define MSDC_EMMC50_CFG_CRC_STS_CNT (0x3 << 1)
438#define MSDC_EMMC50_CFG_CRC_STS_EDGE (0x1 << 3)
439#define MSDC_EMMC50_CFG_CRC_STS_SEL (0x1 << 4)
440#define MSDC_EMMC50_CFG_END_BIT_CHK_CNT (0xf << 5)
441#define MSDC_EMMC50_CFG_CMD_RESP_SEL (0x1 << 9)
442#define MSDC_EMMC50_CFG_CMD_EDGE_SEL (0x1 << 10)
443#define MSDC_EMMC50_CFG_ENDBIT_CNT (0x3FF << 11)
444#define MSDC_EMMC50_CFG_READ_DAT_CNT (0x7 << 21)
445#define MSDC_EMMC50_CFG_EMMC50_MON_SEL (0x1 << 24)
446#define MSDC_EMMC50_CFG_MSDC_WR_VALID (0x1 << 25)
447#define MSDC_EMMC50_CFG_MSDC_RD_VALID (0x1 << 26)
448#define MSDC_EMMC50_CFG_MSDC_WR_VALID_SEL (0x1 << 27)
449#define MSDC_EMMC50_CFG_MSDC_RD_VALID_SEL (0x1 << 28)
450#define MSDC_EMMC50_CFG_TXSKEW_SEL (0x1 << 29)
451
452/* EMMC50_CFG1 mask */
453#define MSDC_EMMC50_CFG1_WRPTR_MARGIN (0xFF << 0)
454#define MSDC_EMMC50_CFG1_CKSWITCH_CNT (0x7 << 8)
455#define MSDC_EMMC50_CFG1_RDDAT_STOP (0x1 << 11)
456#define MSDC_EMMC50_CFG1_WAITCLK_CNT (0xF << 12)
457#define MSDC_EMMC50_CFG1_DBG_SEL (0xFF << 16)
458#define MSDC_EMMC50_CFG1_PSHCNT (0x7 << 24)
459#define MSDC_EMMC50_CFG1_PSHPSSEL (0x1 << 27)
460#define MSDC_EMMC50_CFG1_DSCFG (0x1 << 28)
461#define MSDC_EMMC50_CFG1_SPARE1 (0x7UL << 29)
462
463/* EMMC50_CFG2_mask */
464/*#define MSDC_EMMC50_CFG2_AXI_GPD_UP (0x1 << 0)*/
465#define MSDC_EMMC50_CFG2_AXI_IOMMU_WR_EMI (0x1 << 1)
466#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_WR_EMI (0x1 << 2)
467#define MSDC_EMMC50_CFG2_AXI_IOMMU_RD_EMI (0x1 << 7)
468#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_RD_EMI (0x1 << 8)
469#define MSDC_EMMC50_CFG2_AXI_BOUND_128B (0x1 << 13)
470#define MSDC_EMMC50_CFG2_AXI_BOUND_256B (0x1 << 14)
471#define MSDC_EMMC50_CFG2_AXI_BOUND_512B (0x1 << 15)
472#define MSDC_EMMC50_CFG2_AXI_BOUND_1K (0x1 << 16)
473#define MSDC_EMMC50_CFG2_AXI_BOUND_2K (0x1 << 17)
474#define MSDC_EMMC50_CFG2_AXI_BOUND_4K (0x1 << 18)
475#define MSDC_EMMC50_CFG2_AXI_RD_OUTS_NUM (0x1F << 19)
476#define MSDC_EMMC50_CFG2_AXI_SET_LEN (0xf << 24)
477#define MSDC_EMMC50_CFG2_AXI_RESP_ERR_TYPE (0x3 << 28)
478#define MSDC_EMMC50_CFG2_AXI_BUSY (0x1 << 30)
479
480/* EMMC50_CFG3_mask */
481#define MSDC_EMMC50_CFG3_OUTS_WR (0x1F << 0)
482#define MSDC_EMMC50_CFG3_ULTRA_SET_WR (0x3F << 5)
483#define MSDC_EMMC50_CFG3_PREULTRA_SET_WR (0x3F << 11)
484#define MSDC_EMMC50_CFG3_ULTRA_SET_RD (0x3F << 17)
485#define MSDC_EMMC50_CFG3_PREULTRA_SET_RD (0x3F << 23)
486
487/* EMMC50_CFG4_mask */
488#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_WR (0xFF << 0)
489#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_RD (0xFF << 8)
490#define MSDC_EMMC50_CFG4_ULTRA_EN (0x3 << 16)
491#define MSDC_EMMC50_CFG4_AXI_WRAP_DBG_SEL (0x1F << 18)
492
493/* EMMC50_BLOCK_LENGTH mask */
494#define MSDC_EMMC50_BLOCK_LENGTH_MASK (0x1FF << 0)
495
496#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
497#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
498#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
499
500/* EMMC_TOP_CONTROL mask */
501#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
502#define PAD_DAT_RD_RXDLY2 (0x1F << 2) /* RW */
503#define PAD_DAT_RD_RXDLY (0x1F << 7) /* RW */
504#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
505#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
506#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
507
508/* EMMC_TOP_CMD mask */
509#define PAD_CMD_RXDLY2 (0x1F << 0) /* RW */
510#define PAD_CMD_RXDLY (0x1F << 5) /* RW */
511#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
512#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
513
514/* TOP_EMMC50_PAD_CTL0 mask */
515#define MSDC_PAD_CLK_TXDLY (0x1F << 10) /* RW */
516
517/* TOP_EMMC50_PAD_DS_TUNE mask */
518#define PAD_DS_DLY3 (0x1F << 0) /* RW */
519#define PAD_DS_DLY2 (0x1F << 5) /* RW */
520#define PAD_DS_DLY1 (0x1F << 10) /* RW */
521#define PAD_DS_DLY2_SEL (0x1 << 15) /* RW */
522#define PAD_DS_DLY_SEL (0x1 << 16) /* RW */
523
524#ifdef CONFIG_MMC_MTK_LEGACY_SDIO
525#define SUPPORT_LEGACY_SDIO
526#endif
527
528#ifdef SUPPORT_LEGACY_SDIO
529#define SDIO_USE_PORT0 0
530#define SDIO_USE_PORT1 1
531#define SDIO_USE_PORT2 2
532#define SDIO_USE_PORT3 3
533#define SDIO_USE_PORT SDIO_USE_PORT2
534
535typedef void (*sdio_irq_handler_t)(void *); /* external irq handler */
536typedef void (*pm_callback_t)(pm_message_t state, void *data);
537
538struct sdio_ops {
539 void (*sdio_request_eirq)(sdio_irq_handler_t irq_handler, void *data);
540 void (*sdio_enable_eirq)(void);
541 void (*sdio_disable_eirq)(void);
542 void (*sdio_register_pm)(pm_callback_t pm_cb, void *data);
543};
544extern struct sdio_ops mt_sdio_ops[4];
545#endif
546
547#define REQ_CMD_EIO (0x1 << 0)
548#define REQ_CMD_TMO (0x1 << 1)
549#define REQ_DAT_ERR (0x1 << 2)
550#define REQ_STOP_EIO (0x1 << 3)
551#define REQ_STOP_TMO (0x1 << 4)
552#define REQ_CMD_BUSY (0x1 << 5)
553
554#define MSDC_PREPARE_FLAG (0x1 << 0)
555#define MSDC_ASYNC_FLAG (0x1 << 1)
556#define MSDC_MMAP_FLAG (0x1 << 2)
557
558#define MTK_MMC_AUTOSUSPEND_DELAY 50
559#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
560#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
561
562#define PAD_DELAY_MAX 32 /* PAD delay cells */
563
564#define AUTOK_RECOVERABLE_ERROR -1
565#define AUTOK_NONE_RECOVERABLE_ERROR -2
566
567/*--------------------------------------------------------------------------*/
568/* Descriptor Structure */
569/*--------------------------------------------------------------------------*/
570struct mt_gpdma_desc {
571 u32 gpd_info;
572#define GPDMA_DESC_HWO (0x1 << 0)
573#define GPDMA_DESC_BDP (0x1 << 1)
574#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
575#define GPDMA_DESC_INT (0x1 << 16)
576 u32 next;
577 u32 ptr;
578 u32 gpd_data_len;
579#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
580#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
581 u32 arg;
582 u32 blknum;
583 u32 cmd;
584};
585
586struct mt_bdma_desc {
587 u32 bd_info;
588#define BDMA_DESC_EOL (0x1 << 0)
589#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
590#define BDMA_DESC_BLKPAD (0x1 << 17)
591#define BDMA_DESC_DWPAD (0x1 << 18)
592 u32 next;
593 u32 ptr;
594 u32 bd_data_len;
595#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
596};
597
598struct msdc_dma {
599 struct scatterlist *sg; /* I/O scatter list */
600 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
601 struct mt_bdma_desc *bd; /* pointer to bd array */
602 dma_addr_t gpd_addr; /* the physical address of gpd array */
603 dma_addr_t bd_addr; /* the physical address of bd array */
604};
605
606struct msdc_save_para {
607 u32 msdc_cfg;
608 u32 iocon;
609 u32 sdc_cfg;
610 u32 pad_tune0;
611 u32 pad_tune1;
612 u32 patch_bit0;
613 u32 patch_bit1;
614 u32 patch_bit2;
615 u32 pad_ds_tune;
616 u32 emmc50_cfg0;
617 u32 msdc_inten;
618};
619
620struct msdc_tune_para {
621 u32 iocon;
622 u32 pad_tune0;
623 u32 pad_tune1;
624};
625
626struct msdc_delay_phase {
627 u8 maxlen;
628 u8 start;
629 u8 final_phase;
630};
631
632struct mt81xx_sdio_compatible {
633 bool v3_plus;
634 bool top_reg;
635};
636
637struct msdc_host {
638 struct device *dev;
639 struct mmc_host *mmc; /* mmc structure */
640 int cmd_rsp;
641
642 spinlock_t lock;
643 spinlock_t irqlock;
644 struct mmc_request *mrq;
645 struct mmc_command *cmd;
646 struct mmc_data *data;
647 int error;
648
649 void __iomem *base; /* host base address */
650 void __iomem *base_top; /* host top base address */
651 void __iomem *base_gpio; /* host top base address */
652 void __iomem *infra_reset; /* infra reset 0x10001030 */
653
654 struct msdc_dma dma; /* dma channel */
655 u64 dma_mask;
656
657 u32 timeout_ns; /* data timeout ns */
658 u32 timeout_clks; /* data timeout clks */
659 u32 tune_latch_ck_cnt;
660
661 struct pinctrl *pinctrl;
662 struct pinctrl_state *pins_default;
663 struct pinctrl_state *pins_uhs;
664 struct pinctrl_state *pins_dat1;
665 struct pinctrl_state *pins_dat1_eint;
666 struct delayed_work req_timeout;
667 int irq; /* host interrupt */
668 int eint_irq;
669 int sdio_clk_cnt;
670 int sdio_irq_cnt; /* irq enable cnt */
671 bool irq_thread_alive;
672
673 struct clk *src_clk; /* msdc source clock */
674 struct clk *h_clk; /* msdc bus_clk */
675 struct clk *src_clk_cg;
676 u32 mclk; /* mmc subsystem clock frequency */
677 u32 src_clk_freq; /* source clock frequency */
678 u32 sclk; /* SD/MS bus clock frequency */
679 bool clock_on;
680 unsigned char timing;
681 bool vqmmc_enabled;
682 u32 hs400_ds_delay;
683 u32 module_reset_bit;
684 bool hs400_mode; /* current eMMC will run at hs400 mode */
685 struct msdc_save_para save_para; /* used when gate HCLK */
686 struct msdc_tune_para def_tune_para; /* default tune setting */
687 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
688 bool autok_done;
689 int autok_error;
690
691#ifdef SUPPORT_LEGACY_SDIO
692 bool cap_eirq;
693 int suspend;
694 /* external sdio irq operations */
695 void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler,
696 void *data);
697 void (*enable_sdio_eirq)(void);
698 void (*disable_sdio_eirq)(void);
699
700 /* power management callback for external module */
701 void (*register_pm)(pm_callback_t pm_cb, void *data);
702#endif
703 const struct mt81xx_sdio_compatible *dev_comp;
704};