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xjb04a4022021-11-25 15:01:52 +08001/*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17
18
19#ifndef _MEI_INTERFACE_H_
20#define _MEI_INTERFACE_H_
21
22#include <linux/irqreturn.h>
23#include <linux/pci.h>
24#include <linux/mei.h>
25
26#include "mei_dev.h"
27#include "client.h"
28
29/*
30 * mei_cfg - mei device configuration
31 *
32 * @fw_status: FW status
33 * @quirk_probe: device exclusion quirk
34 * @dma_size: device DMA buffers size
35 * @fw_ver_supported: is fw version retrievable from FW
36 */
37struct mei_cfg {
38 const struct mei_fw_status fw_status;
39 bool (*quirk_probe)(struct pci_dev *pdev);
40 size_t dma_size[DMA_DSCR_NUM];
41 u32 fw_ver_supported:1;
42};
43
44
45#define MEI_PCI_DEVICE(dev, cfg) \
46 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
47 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
48 .driver_data = (kernel_ulong_t)(cfg),
49
50#define MEI_ME_RPM_TIMEOUT 500 /* ms */
51
52/**
53 * struct mei_me_hw - me hw specific data
54 *
55 * @cfg: per device generation config and ops
56 * @mem_addr: io memory address
57 * @pg_state: power gating state
58 * @d0i3_supported: di03 support
59 * @hbuf_depth: depth of hardware host/write buffer in slots
60 */
61struct mei_me_hw {
62 const struct mei_cfg *cfg;
63 void __iomem *mem_addr;
64 enum mei_pg_state pg_state;
65 bool d0i3_supported;
66 u8 hbuf_depth;
67};
68
69#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
70
71/**
72 * enum mei_cfg_idx - indices to platform specific configurations.
73 *
74 * Note: has to be synchronized with mei_cfg_list[]
75 *
76 * @MEI_ME_UNDEF_CFG: Lower sentinel.
77 * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices.
78 * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10
79 * @MEI_ME_PCH6_CFG: Platform Controller Hub platforms (Gen6).
80 * @MEI_ME_PCH7_CFG: Platform Controller Hub platforms (Gen7).
81 * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
82 * with quirk for Node Manager exclusion.
83 * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer
84 * client platforms.
85 * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer
86 * servers platforms with quirk for
87 * SPS firmware exclusion.
88 * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
89 * @MEI_ME_NUM_CFG: Upper Sentinel.
90 */
91enum mei_cfg_idx {
92 MEI_ME_UNDEF_CFG,
93 MEI_ME_ICH_CFG,
94 MEI_ME_ICH10_CFG,
95 MEI_ME_PCH6_CFG,
96 MEI_ME_PCH7_CFG,
97 MEI_ME_PCH_CPT_PBG_CFG,
98 MEI_ME_PCH8_CFG,
99 MEI_ME_PCH8_SPS_CFG,
100 MEI_ME_PCH12_CFG,
101 MEI_ME_NUM_CFG,
102};
103
104const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
105
106struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
107 const struct mei_cfg *cfg);
108
109int mei_me_pg_enter_sync(struct mei_device *dev);
110int mei_me_pg_exit_sync(struct mei_device *dev);
111
112irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
113irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
114
115#endif /* _MEI_INTERFACE_H_ */