| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2012 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /******************************************************************************* |
| * Filename: |
| * --------- |
| * pll_gen97.c |
| * |
| * Project: |
| * -------- |
| * UMOLYE |
| * |
| * Description: |
| * ------------ |
| * PLL Related Functions |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| * ========================================================================== |
| * $Log$ |
| * |
| * 11 24 2020 e-lin.ho |
| * [MOLY00593429] [Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow |
| * |
| * [Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow |
| * |
| * 07 29 2020 e-lin.ho |
| * [MOLY00521672] [Gen97] Colgin SB Branch & Call for Check-in |
| * |
| * . |
| * |
| * 07 15 2020 e-lin.ho |
| * [MOLY00546221] [Palmer call for check-in] Add Macro for MT6833 |
| * |
| * [Palmer call for check-in] Add Macro for MT6833 |
| * |
| * 06 17 2020 jun-ying.huang |
| * [MOLY00535069] [MMRFD][UCNT] Read D die PLL CNT at exception flow |
| * Add PLL related function |
| * |
| * 03 20 2020 jun-ying.huang |
| * [MOLY00505554] [VMOLY][Mouton]Sync/Update Mouton Bring up code |
| * . |
| * |
| * 01 16 2020 jun-ying.huang |
| * [MOLY00474985] [MOUTON call for check-in] Add Macro for MT6853 |
| * . |
| * |
| * 11 05 2019 jun-ying.huang |
| * [MOLY00457260] [MARGAUX call for check-in]Update related driver for MARGAUX |
| * . |
| * |
| * 09 23 2019 jun-ying.huang |
| * [MOLY00442314] [MARGAUX call for check-in] Add Macro for MT6873 |
| * . |
| * |
| * 09 03 2019 jun-ying.huang |
| * [MOLY00431611] [VMOLY][Petrus]Update related driver for Petrus. |
| * Update AMIF&PLL driver |
| * |
| * 08 20 2019 jun-ying.huang |
| * [MOLY00431611] [VMOLY][Petrus]Update related driver for Petrus. |
| * Update DCM and PLL driver |
| * |
| * 06 26 2019 jun-ying.huang |
| * [MOLY00416732] [APOLLO][VMOLY]Update PLL setting |
| * Change NR_TXBSRP clock from 624 to 450Mhz due to TXBSRP issue |
| * |
| * 06 11 2019 jun-ying.huang |
| * [MOLY00406229] [VMOLY][MT6885]Update PLL init setting |
| * Update MDMCUPLL |
| * |
| * 05 14 2019 jun-ying.huang |
| * [MOLY00406229] [VMOLY][MT6885]Update PLL init setting |
| * Update PLL setting for Petrus |
| * |
| * 12 21 2018 jun-ying.huang |
| * [MOLY00370736] [MT6885]Update PLL for MT6885 |
| * PLL init setting change for APOLLO request |
| * |
| * 12 05 2018 jun-ying.huang |
| * [MOLY00370736] [MT6885]Update PLL for MT6885 |
| * . |
| * |
| * 11 29 2018 jun-ying.huang |
| * [MOLY00368816] [MT6297][APOLLO]Update PLL driver |
| * Bus fix for frequency meter |
| * |
| * 11 01 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * Update PLL init |
| * |
| * 09 11 2018 jun-ying.huang |
| * [MOLY00351556] [MT6297]Remove 26M status check in BASIC/MD only load |
| * . |
| * |
| * 08 17 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 08 09 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 07 30 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 07 13 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 07 06 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 06 06 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * 1st version of PLL driver |
| * |
| * 06 06 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * . |
| * |
| * 05 30 2018 jun-ying.huang |
| * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97 |
| * draft version |
| * |
| * |
| * |
| ****************************************************************************/ |
| |
| #ifdef __MTK_TARGET__ /* should NOT be compiled on MODIS */ |
| |
| /******************************************************************************* |
| * Locally Used Options |
| *******************************************************************************/ |
| |
| /******************************************************************************* |
| * Include header files |
| *******************************************************************************/ |
| |
| #include "pll.h" |
| #include "kal_public_api.h" |
| #include "sync_data.h" |
| #include "us_timer.h" |
| #include "sleepdrv_common.h" |
| #include "ex_public.h" |
| |
| /******************************************************************************* |
| * external functions |
| *******************************************************************************/ |
| extern void PLL_SEC_SW_VERSION_ENHANCE(); |
| |
| /* Below for debugging */ |
| const char PLL_FM_clock[PLL_FM_NUM][32] = |
| { |
| "AD_MDNRPLL5", /* 0 */ |
| "AD_MDNRPLL4_1", |
| "AD_MDNRPLL4_0", |
| "AD_MDNRPLL3", |
| "AD_MDNRPLL2", |
| "AD_MDNRPLL1", /* 5 */ |
| "AD_MDNRPLL0", |
| "MDSYS_NRL2_CLOCK", |
| "MDRXSYS_DFESYNC_CLOCK", |
| #if defined(MT6297)/* APOLLO */ |
| "MDTOP_F208M_CLOCK", |
| "TRACE_MON_CLOCK", /* 10 */ |
| "MDSYS_208M_CLOCK", |
| #else/* PETRUS and later */ |
| "MDTOP_F216P7M_CLOCK", |
| "TRACE_MON_CLOCK", /* 10 */ |
| "MDSYS_216P7M_CLOCK", |
| #endif |
| "MDRXSYS_RAKE_CLOCK", |
| "MDRXSYS_BRP_CLOCK", |
| "MDRXSYS_VDSP_CLOCK", |
| "MDTOP_LOG_ATB_CLOCK", /* 15 */ |
| "FESYS_CSYS_CLOCK", |
| "MDSYS_SHAOLIN_CLOCK", |
| "FESYS_BSI_CLOCK", |
| "MDSYS_MDCORE_CLOCK", |
| "MDSYS_BUS2X_NODCM_CLOCK",/* 20 */ |
| "MDSYS_BUS4X_CLOCK", |
| "MDTOP_DBG_CLOCK", |
| "AD_MDBPI_PLL_D7", |
| "AD_MDBPI_PLL_D5", |
| "AD_MDBPI_PLL_D4", /* 25 */ |
| "AD_MDBPI_PLL_D3", |
| "AD_MDBPI_PLL_D2", |
| "AD_MDBRP_PLL", |
| "AD_MDVDSP_PLL", |
| "AD_MDMCU_PLL", /* 30 */ |
| #if defined(MT6297)/* APOLLO */ |
| "MDTOP_BUS4X_CLOCK", |
| "RXCPC_CPC_CLOCK", |
| "RXDDMBRP_RXCSI_CLOCK", |
| "RXDDMBRP_RXDBRP_CLOCK", |
| "RXDDMBRP_RXDDM_CLOCK", /* 35 */ |
| "MCORE_MCORE_CLOCK", |
| "VCOREHRAM_VCORE_CLOCK", |
| "VCOREHRAM_HRAM_CLOCK", |
| "FESYS_TXBSRP_CLOCK", |
| "FESYS_MDPLL_CLOCK", /* 40 */ |
| "TX_CS_NR_RXT2F_NR_CLOCK", |
| "TX_CS_NR_TXBSRP_NR_CLOCK", |
| "TX_CS_NR_CM_NR_CLOCK", |
| "TX_CS_NR_CS_NR_CLOCK", |
| /* below no use */ |
| "null_45", /* 45 */ |
| "null_46", |
| "null_47" |
| #else/* PETRUS and later */ |
| "DFESYS_RXDFE_BB_CORE_CLOCK", |
| "AD_MDNRPLL4_2", |
| "MDTOP_BUS4X_FIXED_CLOCK", |
| "DA_DRF_26M_CLOCK", |
| "MDTOP_BUS4X_CLOCK", /* 35 */ |
| "RXCPC_CPC_CLOCK", |
| "RXDDMBRP_RXDBRP_CLOCK", |
| "RXDDMBRP_RXDDM_CLOCK", |
| "MCORE_MCORE_CLOCK", |
| "VCOREHRAM_VCORE_CLOCK", /* 40 */ |
| "VCOREHRAM_HRAM_CLOCK", |
| "FESYS_TXBSRP_CLOCK", |
| "FESYS_MDPLL_CLOCK", |
| "TX_CS_NR_RXT2F_NR_CLOCK", |
| "TX_CS_NR_TXBSRP_NR_CLOCK",/* 45 */ |
| "TX_CS_NR_CM_NR_CLOCK", |
| "TX_CS_NR_CS_NR_CLOCK" |
| /* we couldn't add more PLL here... */ |
| #endif |
| }; |
| |
| PLL_CLK_INFO g_pll_info = {0}; |
| |
| /* Above for debugging */ |
| |
| /** |
| * This function is used to detect ASIC or FPGA version of Palladium |
| */ |
| __PLL_CODE_IN_BOOT__ kal_bool PLL_FPGA_IS_ASIC(void) |
| { |
| #if defined(__FPGA__) |
| kal_uint32 asic_flag = *((volatile kal_uint32 *)(0xA0000018)) & (0x1 << 7); |
| |
| if (asic_flag == 0) |
| return KAL_TRUE; |
| else |
| return KAL_FALSE; |
| #else |
| return KAL_TRUE; |
| #endif |
| } |
| |
| __PLL_CODE_IN_BOOT__ void INT_SetPLL_Gen97(void) |
| { |
| #if defined(MT6297)/* APOLLO */ |
| // Default md_srclkena_ack settle time = 150T 32K |
| *REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL = (0x02021C00|SYS_CLK_SETTLE); |
| |
| //Change ABBPLL_SETTLE_26M to 0x2F2==>29us |
| *REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL = 0x17920803; |
| |
| // Set HRAM to 800Mhz for initial |
| *REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL = 0x21; |
| *REG_MDTOP_CLKSW_IA_DFS_FLEXCKGEN_SEL = 0x0; |
| *REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL = 0x30; // to NRPLL4_1_CK 800Mhz |
| *REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL = 0x11; // to BPIPLL |
| *REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL = 0x10; // to NRPLL1 |
| *REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL = 0x21; // NRL2 spec to 450Mhz |
| *REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL = 0x10; // MCORE spec to 900Mhz |
| *REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL = 0x10; // VCORE spec to 900Mhz |
| |
| *REG_MDTOP_CLKSW_CLK_DUMMY = 0x00F7FFFF; // NR0/1/2/4/5 PLL turn on |
| |
| *REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1 &= 0xFFFEFFFF; // set FBKSEL=0 |
| *REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1 &= 0xFFFEFFFF; // set FBKSEL=0 |
| |
| *REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 = 0x80117B13; // Fixed Fvco = 1818Mhz (for HRAM to 910Mhz). (/2)909M, (/3)606M, (/4)454M, (/5)363M, (/6)303M, (/7)259M |
| *REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 = 0x8023D800; // Fvco = 3728Mhz. 3728/4 = 932Mhz |
| *REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 = 0x80229E00; // Fvco = 3600Mhz. 3600/4 = 900Mhz |
| *REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 = 0x8019F626; // Fvco = 2700Mhz. 2700/3 = 900Mhz |
| |
| *REG_MDTOP_PLLMIXED_MDPLL_CTL0 = 0x80180000; // Fvco = 2496Mhz. 2496/4 = 624Mhz |
| *REG_MDTOP_PLLMIXED_MDPLL_CTL1 = 0x12; |
| |
| *REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0 = 0x80133C00; // Fvco = 2000Mhz. 2000/2 = 1000Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0 = 0x80171400; // Fvco = 2400Mhz. 2400/2 = 1200Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0 = 0x801AEC00; // Fvco = 2800Mhz. 2800/2 = 1400Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0 = 0x80180000; // Fvco = 2496Mhz. 2496/4 = 624Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0 = 0x800F6200; // Fvco = 1600Mhz. 1600/1 = 1600Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0 = 0x801CD800; // Fvco = 3000Mhz. 3000/2 = 1500Mhz |
| |
| //#if defined(MT6297_IA)/* 97 IA */ |
| // *REG_MDTOP_PLLMIXED_PLL_ON_CTL = 0xDC00DC0; // force NR0/1/2/4/5 PLL turn on |
| //#else/* 97 SHAOLIN */ |
| // *REG_MDTOP_PLLMIXED_PLL_ON_CTL = 0x5C005C0; // force NR0/1/2/4 PLL turn on |
| //#endif |
| |
| #else /* PETRUS, MARGAUX, MOUTON, COLGIN, Palmer */ |
| // Default md_srclkena_ack settle time = SYS_CLK_SETTLE T 32K in sleepdrv_common.h |
| *REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL = (0x02021C00|SYS_CLK_SETTLE); |
| |
| //Change ABBPLL_SETTLE_26M to 0x2F2==>29us |
| *REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL = 0x17920803; |
| |
| #if defined(MT6297) || defined(MT6885) || defined(MT6873) /* APOLLO or PETRUS or MARGAUX */ |
| /* keep default value */ |
| #else /* COLGIN, MOUTON and later... */ |
| *REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE = 0x0; |
| #endif |
| *REG_MDTOP_CLKSW_CLK_DUMMY = 0x00DFFFFF; |
| *REG_MDTOP_PLLMIXED_PLL_SRC_SEL = 0x0; |
| |
| *REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL = 0x10; // to NRPLL1 |
| *REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL = 0x11; // to BPIPLL |
| *REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL = 0x30; // to NRPLL4_1_CK 800Mhz |
| *REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL=0x01; |
| *REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL=0x00; |
| *REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL=0x00; |
| *REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL=0x00; |
| |
| *REG_MDTOP_PLLMIXED_PLL_DIV_EN0 = 0x2F020202; |
| *REG_MDTOP_PLLMIXED_PLL_DIV_EN3 = 0x00000003; |
| |
| *REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 = 0x80114EC5; // Fixed Fvco = 1800Mhz |
| #if defined(MT6833) /* Palmer */ |
| *REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 = 0x80143140; // Fvco = 2100Mhz. 2100/3 = 700Mhz more setting in PLL_SEC_SW_VERSION_ENHANCE() |
| #else |
| *REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 = 0x801FBB13; // Fvco = 3300Mhz. 3300/3 = 1100Mhz more setting in PLL_SEC_SW_VERSION_ENHANCE() |
| #endif |
| *REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 = 0x801D2276; // Fvco = 3030Mhz. 3030/3 = 1010Mhz |
| #if defined(MT6885)/* PETRUS *//* Only for PETRUS */ |
| *REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 = 0x801F189E; // Fvco = 3234Mhz. 3234/3 = 1078Mhz |
| #else/* MARGAUX and later... */ |
| *REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 = 0x801FBB13; // Fvco = 3300Mhz. 3300/3 = 1100Mhz |
| #endif |
| |
| *REG_MDTOP_PLLMIXED_MDPLL_CTL0 = 0x80190000; // Fvco = 2600Mhz. 2600/4 = 650Mhz |
| *REG_MDTOP_PLLMIXED_MDPLL_CTL1 = 0x12; |
| |
| *REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1 = 0x12; |
| *REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1 = 0x12; |
| |
| *REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0 = 0x80133B13; // Fvco = 2000Mhz. 2000/2 = 1000Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0 = 0x801713B1; // Fvco = 2400Mhz. 2400/2 = 1200Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0 = 0x801AEC4E; // Fvco = 2800Mhz. 2800/4 = 700Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0 = 0x80180000; // Fvco = 2496Mhz. 2496/4 = 624Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0 = 0x800F6276; // Fvco = 1600Mhz. 1600/1 = 1600Mhz |
| *REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0 = 0x801CD890; // Fvco = 3000Mhz. 3000/2 = 1500Mhz |
| #endif |
| |
| *REG_MDTOP_PLLMIXED_PLL_ON_CTL = 0x0; |
| |
| MO_Sync(); |
| |
| /* |
| * Polling until MDMCUPLL complete frequency adjustment |
| * Once MDMCUPLL complete, other PLL should complete too |
| */ |
| while ((*REG_MDTOP_PLLMIXED_MDMCUPLL_STS >> 14)&0x1); |
| |
| #if defined(__PALLADIUM__) |
| if (PLL_FPGA_IS_ASIC() == KAL_TRUE) { |
| while ((*REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS & 0x8000) != 0x8000); |
| } |
| #else // Not PALLADIUM |
| #if !defined(__FPGA__) |
| /* |
| * Wait MD bus clock ready |
| * Once MD bus ready, other clock should be ready too |
| * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA. |
| */ |
| while ((*REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS & 0x8000) != 0x8000); |
| #endif // __FPGA__ |
| #endif // __PALLADIUM__ |
| |
| /* Switch clock source to PLL */ |
| *REG_MDTOP_CLKSW_CLKSEL_CTL |= 0x3; //switch MDMCU & MD BUS clock to PLL frequency |
| |
| *REG_MDTOP_CLKSW_CLKSEL_CTL |= 0xFFFFFFFC; //switch all clock to PLL frequency |
| *REG_MDTOP_CLKSW_CLKSEL_CTL_2 |= 0x4; |
| |
| *REG_MDTOP_CLKSW_CLKON_CTL = 0x3; //Turn off all SW clock request |
| |
| #if defined(MT6297)/* APOLLO */ |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL |= 0x1100011; // switch SDF clock to PLL frequency |
| #else /* PETRUS and later */ |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL |= 0x1104011; // switch SDF clock to PLL frequency |
| #endif |
| MO_Sync(); |
| |
| // Clear PLL ADJ RDY IRQ fired by initial period adjustment |
| *REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ = 0xFFFF; |
| |
| // Mask all PLL ADJ RDY IRQ |
| *REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK = 0xFFFF; |
| MO_Sync(); |
| |
| // Make a record that means MD pll has been initialized. |
| *REG_MDTOP_PLLMIXED_PLL_DUMMY = MD_PLL_MAGIC_NUM; |
| MO_Sync(); |
| } |
| |
| __PLL_CODE_IN_BOOT__ kal_uint8 pll_get_current_vpe_id(void) |
| { |
| unsigned int vpe_id = 0; |
| |
| __asm__ __volatile__( |
| "mfc0 %0, $15, 1" \ |
| : "=r" (vpe_id) \ |
| :); |
| |
| return (vpe_id & 0xF); |
| } |
| |
| /************************************************************************* |
| * FUNCTION |
| * INT_SetPLL |
| * |
| * DESCRIPTION |
| * This function dedicates for PLL setting. |
| * |
| * PARAMETERS |
| * Init mode of PLL |
| * |
| * RETURNS |
| * Note : This function would only call by MD. |
| *************************************************************************/ |
| void INT_SetPLL(void) |
| { |
| #if !defined(__COSIM_BYPASS__) && !defined(__ESL_MASE__) |
| if ((pll_get_current_vpe_id() == 0)) |
| { |
| if (*REG_MDTOP_PLLMIXED_PLL_DUMMY != MD_PLL_MAGIC_NUM) |
| {/* PLL didn't init by BootRom */ |
| PLL_MD_Pll_Init(); |
| |
| // Make a record that means MD pll has init by MD. |
| *REG_MDTOP_PLLMIXED_PLL_DUMMY = MD_PLL_MAGIC_MD; |
| } |
| |
| //Clear 26M ACK Status(There would be false alarm at MD boot up..) here due to BootRom didn't init FRC. |
| PLL_Clear_26M_ACK_Status(); |
| |
| PLL_SEC_SW_VERSION_ENHANCE(); |
| } |
| #endif // __COSIM_BYPASS__ |
| } |
| |
| /************************************************************************* |
| * FUNCTION |
| * PLL_MD_Pll_Init |
| * |
| * DESCRIPTION |
| * This function dedicates for PLL setting. |
| * |
| * PARAMETERS |
| * Init mode of PLL |
| * |
| * RETURNS |
| * Note : This function would call by BootRom and MD!! |
| *************************************************************************/ |
| __PLL_CODE_IN_BOOT__ void PLL_MD_Pll_Init(void) |
| { |
| #if !defined(__COSIM_BYPASS__) && !defined(__ESL_MASE__) |
| INT_SetPLL_Gen97(); |
| #endif // __COSIM_BYPASS__ |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_Check_26M_ACK_Status |
| * Purpose: Check 26M ACK Status to know 26M is ready. |
| * Parameters: |
| * Input: kal_uint32 identifier: Any value to let us confirm the caller. |
| * |
| * Output: None. |
| * |
| * returns : void. |
| * Note : This function would call by Idle_Service_Handler() |
| * |
| *------------------------------------------------------------------------ |
| */ |
| void PLL_Check_26M_ACK_Status(kal_uint32 identifier) |
| { |
| #if defined(__PRODUCTION_RELEASE__) || defined(__MAUI_BASIC__) || defined(__MODEM_ONLY__) |
| /* Do nothing. */ |
| #else |
| /* under construction !*/ |
| #endif |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_Clear_26M_ACK_Status |
| * Purpose: Clear 26M ACK Status. |
| * Parameters: |
| * Input: None. |
| * |
| * Output: None. |
| * |
| * returns : void. |
| * Note : This function could not call by BootRom due to BootRom didn't init FRC. |
| * |
| *------------------------------------------------------------------------ |
| */ |
| void PLL_Clear_26M_ACK_Status(void) |
| { |
| *REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK = 0x80; |
| MO_Sync(); |
| ust_us_busyloop(35);//need wait at least 1T 32K |
| *REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK = 0x0; |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_Set_CLK_To_26M |
| * Purpose: Re-configure all the module clocks from PLL to 26M. |
| * Parameters: |
| * Input: None. |
| * |
| * Output: None. |
| * |
| * returns : void. |
| * Note : This function would call by BootRom!! |
| * |
| *------------------------------------------------------------------------ |
| */ |
| __PLL_CODE_IN_BOOT__ void PLL_Set_CLK_To_26M(void) |
| { |
| *REG_MDTOP_CLKSW_CLKON_CTL = 0x10001; // set to default value |
| *REG_MDTOP_CLKSW_CLKSEL_CTL = 0x14000; //switch all clock to XTAL frequency |
| *REG_MDTOP_CLKSW_CLKSEL_CTL_2 = 0x0; //switch all clock to XTAL frequency |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = 0x100001; // switch SDF clock to XTAL frequency |
| |
| MO_Sync(); |
| // Make a record that means MD pll has been changed to 26M. |
| *REG_MDTOP_PLLMIXED_PLL_DUMMY = MD_PLL_MAGIC_26M; |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_FrequencyMeter_GetFreq |
| * Purpose: Get specified PLL/module's clock(Mhz). |
| * Parameters: |
| * Input: PLL_FM_SOURCE index: The module you want to measure. |
| * |
| * Output: None. |
| * |
| * returns : The PLL/module's clock(Mhz). |
| * Note : This function would spend at least 23us to measure the clock. |
| * |
| *------------------------------------------------------------------------ |
| */ |
| kal_uint32 PLL_FM_FESYS_MDPLL_CNT; |
| kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index) |
| { |
| kal_uint32 count = 5000, output = 0; |
| |
| if (index > PLL_FM_SOURCE_END) |
| return 0; |
| |
| #if defined(MT6297)/* APOLLO */ |
| /* Only need on APOLLO */ |
| if(index == PLL_FM_MDSYS_IA_CLOCK) |
| {/* Use MUX to measure IA's clock */ |
| *REG_MDTOP_CLKSW_CLK_DUMMY = *REG_MDTOP_CLKSW_CLK_DUMMY | 0x80000000; |
| index = PLL_FM_MDSYS_SHAOLIN_CLOCK; |
| } |
| else if(index == PLL_FM_MDSYS_SHAOLIN_CLOCK) |
| {/* Use MUX to measure SHAOLIN's clock */ |
| *REG_MDTOP_CLKSW_CLK_DUMMY = *REG_MDTOP_CLKSW_CLK_DUMMY & 0x7FFFFFFF; |
| } |
| #endif |
| |
| *REG_MDTOP_CLKSW_CKMON_CTL = PLL_FM_MDSYS_BUS4X_CLOCK; //select source to a valid clock to let reset success. |
| |
| *REG_MDTOP_CLKSW_FREQ_METER_CTL = 0; //reset frequency meter |
| |
| MO_Sync(); |
| ust_us_busyloop(2);//let Frequency Meter reset done |
| |
| *REG_MDTOP_CLKSW_CKMON_CTL = index; |
| |
| // Get high precise MDPLL frequency in exception flow |
| if(INT_QueryExceptionStatus()==KAL_TRUE && index== PLL_FM_FESYS_MDPLL_CLOCK) { |
| *REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT = PLL_FM_WIMDOW_EX_MDPLL; |
| count = 5000000; |
| } |
| else { |
| *REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT = PLL_FM_WIMDOW; |
| } |
| |
| *REG_MDTOP_CLKSW_FREQ_METER_CTL = 1; //enable frequency meter |
| MO_Sync(); |
| |
| // wait measure done or timeout |
| while (((*REG_MDTOP_CLKSW_FREQ_METER_CTL) & (1 << 1)) == 0) |
| { |
| count--; |
| if (count == 0) |
| break; |
| } |
| |
| if (count == 0) |
| return 0; |
| |
| // Get MDPLL CLMON_CNT in exception flow |
| if(INT_QueryExceptionStatus()==KAL_TRUE && index== PLL_FM_FESYS_MDPLL_CLOCK) { |
| PLL_FM_FESYS_MDPLL_CNT = *REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT; |
| output = *REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT * 26 / (PLL_FM_WIMDOW_EX_MDPLL+3); |
| } |
| else { |
| output = *REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT * 26 / (PLL_FM_WIMDOW+3); |
| } |
| |
| *REG_MDTOP_CLKSW_CKMON_CTL = PLL_FM_NULL; //select source to NULL to save power in flip-flop, save about 0.07mA in 6293 |
| |
| *REG_MDTOP_CLKSW_FREQ_METER_CTL = 0; //reset frequency meter |
| |
| return output; |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_FrequencyMeter_GetCKMON_CNT |
| * Purpose: Get specified PLL/module's CKMON_CNT & clock(Mhz). |
| * Parameters: |
| * Input: PLL_FM_SOURCE index: The module you want to measure. |
| * kal_uint32 xta_cnt: 26M CNT. Suggest use PLL_FM_WIMDOW directly. (invalid parameter in Gen97) |
| * |
| * Output: kal_uint32 *ckmon_cnt: specified PLL/module's CKMON_CNT. |
| * |
| * returns : The PLL/module's clock(Mhz) or PLL_FM_SOURCE_OCCUPIED. |
| * Note : This function would spend 23 us to measure the clock. |
| * This function could only call in EE flow to avoid race condition. |
| * Request by YW Lee, Yinyan Lin. |
| *------------------------------------------------------------------------ |
| */ |
| kal_uint32 PLL_FrequencyMeter_GetCKMON_CNT(PLL_FM_SOURCE index, kal_uint32 xta_cnt, kal_uint32 *ckmon_cnt) |
| { |
| kal_uint32 output = 0; |
| |
| if(INT_QueryExceptionStatus()!=KAL_TRUE) |
| {//not in EE flow |
| return PLL_FM_SOURCE_OCCUPIED; |
| } |
| |
| output = PLL_FrequencyMeter_GetFreq(index); |
| |
| *ckmon_cnt = *REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT; |
| |
| return output; |
| } |
| |
| void PLL_exception_dump(void) |
| { |
| g_pll_info.AD_MDNRPLL5 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL5); |
| g_pll_info.AD_MDNRPLL4_1 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL4_1); |
| g_pll_info.AD_MDNRPLL4_0 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL4_0); |
| g_pll_info.AD_MDNRPLL3 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL3); |
| g_pll_info.AD_MDNRPLL2 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL2); |
| g_pll_info.AD_MDNRPLL1 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL1); |
| g_pll_info.AD_MDNRPLL0 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL0); |
| g_pll_info.MDSYS_NRL2_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_NRL2_CLOCK); |
| g_pll_info.MDRXSYS_DFESYNC_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDRXSYS_DFESYNC_CLOCK); |
| #if defined(MT6297)/* APOLLO */ |
| g_pll_info.MDTOP_F208M_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_F208M_CLOCK); |
| g_pll_info.TRACE_MON_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TRACE_MON_CLOCK); |
| g_pll_info.MDSYS_208M_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_208M_CLOCK); |
| #else/* PETRUS and later */ |
| g_pll_info.MDTOP_F216P7M_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_F216P7M_CLOCK); |
| g_pll_info.TRACE_MON_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TRACE_MON_CLOCK); |
| g_pll_info.MDSYS_216P7M_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_216P7M_CLOCK); |
| #endif |
| g_pll_info.MDRXSYS_RAKE_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDRXSYS_RAKE_CLOCK); |
| g_pll_info.MDRXSYS_BRP_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDRXSYS_BRP_CLOCK); |
| g_pll_info.MDRXSYS_VDSP_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDRXSYS_VDSP_CLOCK); |
| g_pll_info.MDTOP_LOG_ATB_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_LOG_ATB_CLOCK); |
| g_pll_info.FESYS_CSYS_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_FESYS_CSYS_CLOCK); |
| g_pll_info.MDSYS_SHAOLIN_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_SHAOLIN_CLOCK); |
| g_pll_info.FESYS_BSI_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_FESYS_BSI_CLOCK); |
| g_pll_info.MDSYS_MDCORE_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_MDCORE_CLOCK); |
| g_pll_info.MDSYS_BUS2X_NODCM_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_BUS2X_NODCM_CLOCK); |
| g_pll_info.MDSYS_BUS4X_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDSYS_BUS4X_CLOCK); |
| g_pll_info.MDTOP_DBG_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_DBG_CLOCK); |
| g_pll_info.AD_MDBPI_PLL_D7 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBPI_PLL_D7); |
| g_pll_info.AD_MDBPI_PLL_D5 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBPI_PLL_D5); |
| g_pll_info.AD_MDBPI_PLL_D4 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBPI_PLL_D4); |
| g_pll_info.AD_MDBPI_PLL_D3 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBPI_PLL_D3); |
| g_pll_info.AD_MDBPI_PLL_D2 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBPI_PLL_D2); |
| g_pll_info.AD_MDBRP_PLL = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDBRP_PLL); |
| g_pll_info.AD_MDVDSP_PLL = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDVDSP_PLL); |
| g_pll_info.AD_MDMCU_PLL = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDMCU_PLL); |
| |
| #if defined(MT6297)/* APOLLO */ |
| /* APOLLO didn't support */ |
| #else/* PETRUS and later */ |
| g_pll_info.DFESYS_RXDFE_BB_CORE_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK); |
| g_pll_info.AD_MDNRPLL4_2 = PLL_FrequencyMeter_GetFreq(PLL_FM_AD_MDNRPLL4_2); |
| g_pll_info.MDTOP_BUS4X_FIXED_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_BUS4X_FIXED_CLOCK); |
| g_pll_info.DA_DRF_26M_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_DA_DRF_26M_CLOCK); |
| #endif |
| |
| g_pll_info.MDTOP_BUS4X_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MDTOP_BUS4X_CLOCK); |
| g_pll_info.RXCPC_CPC_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_RXCPC_CPC_CLOCK); |
| |
| #if defined(MT6297)/* Only APOLLO support. */ |
| g_pll_info.RXDDMBRP_RXCSI_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_RXDDMBRP_RXCSI_CLOCK); |
| #endif |
| g_pll_info.RXDDMBRP_RXDBRP_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_RXDDMBRP_RXDBRP_CLOCK); |
| g_pll_info.RXDDMBRP_RXDDM_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_RXDDMBRP_RXDDM_CLOCK); |
| g_pll_info.MCORE_MCORE_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_MCORE_MCORE_CLOCK); |
| g_pll_info.VCOREHRAM_VCORE_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_VCOREHRAM_VCORE_CLOCK); |
| g_pll_info.VCOREHRAM_HRAM_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_VCOREHRAM_HRAM_CLOCK); |
| g_pll_info.FESYS_TXBSRP_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_FESYS_TXBSRP_CLOCK); |
| g_pll_info.FESYS_MDPLL_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_FESYS_MDPLL_CLOCK); |
| g_pll_info.TX_CS_NR_RXT2F_NR_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK); |
| g_pll_info.TX_CS_NR_TXBSRP_NR_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK); |
| g_pll_info.TX_CS_NR_CM_NR_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TX_CS_NR_CM_NR_CLOCK); |
| g_pll_info.TX_CS_NR_CS_NR_CLOCK = PLL_FrequencyMeter_GetFreq(PLL_FM_TX_CS_NR_CS_NR_CLOCK); |
| |
| } |
| |
| |
| /**************************************************************** |
| Function for SDF module. (SIB) |
| ****************************************************************/ |
| /*------------------------------------------------------------------------ |
| * void PLL_CLKSW_SDF_SRC_CKSEL_Get |
| * Purpose: Get the selection of SDF source clock. |
| * Parameters: |
| * Input: None. |
| * |
| * Output: None. |
| * |
| * returns : The selection of SDF source clock. |
| * |
| * Note : |
| * |
| *------------------------------------------------------------------------ |
| */ |
| kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get() |
| { |
| if((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL&(1<<4))==0) |
| { |
| return CLKSW_SDF_SRC_26M; |
| } |
| else |
| { |
| return (((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0x00000180) >> 7); |
| } |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_CLKSW_SDF_SRC_CKSEL_Div_Get |
| * Purpose: Get the selection of SDF source clock Div. |
| * Parameters: |
| * Input: None. |
| * |
| * Output: None. |
| * |
| * returns : The selection of SDF source clock Div |
| * |
| * Note : |
| * |
| *------------------------------------------------------------------------ |
| */ |
| kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get() |
| { |
| return (((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0x00000060) >> 5); |
| } |
| |
| /*------------------------------------------------------------------------ |
| * void PLL_CLKSW_SDF_SRC_CKSEL_Set |
| * Purpose: Set the selection of SDF source clock. |
| * Parameters: |
| * Input: PLL_CLKSW_SDF_SRC src_ck: CLKSW_SDF_SRC_xxx in "Pll_gen97.h", src_clk index. |
| * PLL_CLKSW_SDF_SRC_DIV src_div: CLKSW_SDF_SRC_xxx in "Pll_gen97.h", src_div index. |
| * Output: None. |
| * |
| * returns : KAL_TRUE/KAL_FALSE |
| * |
| * Note : Porting from LR12's PLL_SDF_SRC_CKSEL_SET(). |
| * |
| *------------------------------------------------------------------------ |
| */ |
| kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div) |
| { |
| kal_uint32 /*caller_LR, */tmp = 0; |
| //GET_RETURN_ADDRESS(caller_LR); |
| |
| if (src_clk >= CLKSW_SDF_SRC_END) |
| { |
| //EXT_ASSERT(0, caller_LR, src_clk, 0); |
| return KAL_FALSE; |
| } |
| |
| if(src_clk == CLKSW_SDF_SRC_26M) |
| {/* Restore to default setting */ |
| |
| // SDF clock switch to 26Mhz |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL &= ~(1<<4); |
| |
| //restore SDF clock source |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = ((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0xFFFFFC1F); |
| } |
| else |
| { |
| // SDF clock switch to 26Mhz |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL &= ~(1<<4); |
| |
| //set SDF clock source |
| tmp = (src_clk<<7) | (src_div<<5); |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = ((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0xFFFFFC1F) | (tmp); |
| |
| // SDF clock switch to full speed |
| *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL |= (1<<4); |
| } |
| |
| MO_Sync(); |
| |
| return KAL_TRUE; |
| } |
| |
| #endif /* should NOT be compiled on MODIS */ |