| #ifndef _IDC_EL1CH_ENUM_H |
| #define _IDC_EL1CH_ENUM_H |
| |
| typedef enum |
| { |
| IDC_LTE_DUPLEX_FDD = 0, |
| IDC_LTE_DUPLEX_TDD = 1, |
| IDC_LTE_DUPLEX_FS3 = 2, |
| IDC_LTE_DUPLEX_UNKNOW = 3 |
| }el1_ch_idc_duplex_mode_enum; |
| |
| typedef enum |
| { |
| IDC_LTE_DRX_TYPE_NO_DRX = 0, |
| IDC_LTE_DRX_TYPE_SHORT_DRX = 1, |
| IDC_LTE_DRX_TYPE_LONG_DRX = 2 |
| }el1_ch_idc_drx_type_enum; |
| |
| typedef enum |
| { |
| IDC_LTE_RX_PROTECT_INTRA_CS = 0, |
| IDC_LTE_RX_PROTECT_INTRA_MEAS = 1, |
| IDC_LTE_RX_PROTECT_SRV_BCCH = 2, |
| IDC_LTE_RX_PROTECT_PAGING = 3, |
| IDC_LTE_RX_PROTECT_INTER_CS_MEAS = 4, |
| IDC_LTE_RX_PROTECT_CSR = 5, |
| IDC_LTE_RX_PROTECT_NBR_BCCH = 6, |
| IDC_LTE_RX_PROTECT_DLSYNC_CAL = 7, |
| IDC_LTE_RX_PROTECT_PRESYNC = 8, |
| IDC_LTE_RX_PROTECT_INTRA_POS = 9, |
| IDC_LTE_RX_PROTECT_SCELL_INTRA_RSSI = 10, |
| IDC_LTE_RX_PROTECT_MBMS = 11, |
| IDC_LTE_RX_PROTECT_POS_PRESYNC = 12, |
| IDC_LTE_RX_PROTECT_TYPE_NUM = 13 |
| }idc_el1_phs_rx_protect_type_enum; |
| |
| typedef enum |
| { |
| IDC_LTE_RX_STATUS_NONE = 0, |
| IDC_LTE_RX_STATUS_SUSP = 1, |
| IDC_LTE_RX_STATUS_RESU = 2, |
| IDC_LTE_RX_STATUS_INVALID = 3 |
| }idc_el1_phs_rx_status_enum; |
| |
| typedef enum |
| { |
| LTE_CNF_FAIL = 0, |
| LTE_CNF_SUCCESS = 1, |
| LTE_CNF_INVALID = 2 |
| }el1_phs_idc_cnf_status_enum; |
| |
| typedef enum |
| { |
| EL1_IDC_RAT_STATUS_FLIGHT = 0, |
| EL1_IDC_RAT_STATUS_ACTIVE = 1, |
| EL1_IDC_RAT_STATUS_STANDBY = 2 |
| }el1_idc_rat_status_enum; |
| |
| #if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__))) |
| typedef enum |
| { |
| EL1_IDC_BAND_CALSS_PC3 = 0, |
| EL1_IDC_BAND_CALSS_PC2 = 1 |
| }el1_idc_power_class_enum; |
| #endif |
| |
| #endif |