| #ifndef _IDC_NL1RX_ENUM_H |
| #define _IDC_NL1RX_ENUM_H |
| |
| typedef enum |
| { |
| IDC_NR_DUPLEX_FDD = 0, |
| IDC_NR_DUPLEX_TDD = 1, |
| IDC_NR_DUPLEX_UNKNOWN = 2 |
| }nl1_ctrl_idc_duplex_mode_enum; |
| |
| typedef enum |
| { |
| IDC_NR_DRX_TYPE_NO_DRX = 0, |
| IDC_NR_DRX_TYPE_SHORT_DRX = 1, |
| IDC_NR_DRX_TYPE_LONG_DRX = 2 |
| }nl1_ctrl_idc_drx_type_enum; |
| |
| typedef enum |
| { |
| IDC_NR_RX_PROTECT_INTRA_MEAS = 0, |
| IDC_NR_RX_PROTECT_SRV_BCCH = 1, |
| IDC_NR_RX_PROTECT_PAGING = 2, |
| IDC_NR_RX_PROTECT_INTER_MEAS = 3, |
| IDC_NR_RX_PROTECT_CSR = 4, |
| IDC_NR_RX_PROTECT_NBR_BCCH = 5, |
| IDC_NR_RX_PROTECT_DL_SYNC_CAL = 6, |
| IDC_NR_RX_PROTECT_SYNC = 7, |
| IDC_NR_RX_PROTECT_INTRA_POS = 8, |
| IDC_NR_RX_PROTECT_SCELL_INTRA_RSSI = 9, |
| IDC_NR_RX_PROTECT_TYPE_NUM = 10, |
| IDC_NR_RX_PROTECT_TYPE_INVALID = 11 |
| }idc_nl1_sched_rx_protect_type_enum; |
| |
| typedef enum |
| { |
| IDC_NR_RX_STATUS_NONE = 0, |
| IDC_NR_RX_STATUS_SUSP = 1, |
| IDC_NR_RX_STATUS_RESU = 2, |
| IDC_NR_RX_STATUS_INVALID = 3 |
| }idc_nl1_sched_rx_status_enum; |
| |
| typedef enum |
| { |
| NR_CNF_FAIL = 0, |
| NR_CNF_SUCCESS = 1, |
| NR_CNF_INVALID = 2 |
| }nl1_sched_idc_cnf_status_enum; |
| |
| typedef enum |
| { |
| NL1_RAT_STATUS_FLIGHT = 0, // dont change the order |
| NL1_RAT_STATUS_STANDBY = 1, // dont change the order |
| NL1_RAT_STATUS_ACTIVE = 2 // dont change the order |
| }nl1_rat_status_enum; |
| |
| typedef enum |
| { |
| NL1_IRT_CAUSE_OTHERS = 0, |
| NL1_IRT_CAUSE_ENTER_FLIGHT_MODE = 1, |
| NL1_IRT_CAUSE_LEAVE_FLIGHT_MODE = 2, |
| NL1_IRT_CAUSE_LEAVE_RSVAS_SUSPEND = 3, |
| NL1_IRT_CAUSE_INVALID = 4 |
| }nl1_rat_set_cause_enum; |
| |
| #if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__))) |
| typedef enum |
| { |
| NL1_IDC_BAND_CALSS_PC3 = 0, |
| NL1_IDC_BAND_CALSS_PC2 = 1 |
| }nl1_idc_power_class_enum; |
| #endif |
| |
| #endif |