blob: 52bbccf9fdb405c0a565df09eeb92dac2b2489d5 [file] [log] [blame]
#ifndef _IDC_NL1RX_STR_H
#define _IDC_NL1RX_STR_H
#include "kal_general_types.h"
#include "kal_public_defs.h"
#include "global_type.h"
#include "idc_nr_def.h"
#include "idc_nl1rx_enum.h"
#include "nl1_comm_internal_inter_core_public.h"
typedef struct _idc_nr_time_struct
{
kal_uint64 absTime;
kal_uint32 sfbdTime;
kal_uint16 sfn;
kal_uint8 sf;
}idc_nr_time_struct;
typedef struct _nl1_idc_rx_quality_rpt_struct
{
NL1_SIM_IDX_E sim_index;
kal_uint8 cc_valid_bmp;
kal_int16 os_snr[IDC_NR_CC_NUM];
kal_int16 ar_snr[IDC_NR_CC_NUM];
kal_int16 ma_rsrp[IDC_NR_CC_NUM];
}nl1_idc_rx_quality_rpt_struct;
typedef struct _nl1_ctrl_idc_freq_ntf_struct
{
LOCAL_PARA_HDR
nl1_ctrl_idc_duplex_mode_enum duplexMode[IDC_NR_CC_NUM];
kal_uint8 srvNum;
kal_uint16 band[IDC_NR_CC_NUM];
#if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__)))
nl1_idc_power_class_enum powerclass[IDC_NR_CC_NUM];
#endif
kal_uint32 dlBw[IDC_NR_CC_NUM][MAX_BWP_NUM];
kal_uint32 ulBw[IDC_NR_CC_NUM][MAX_BWP_NUM];
kal_uint32 dlFreq[IDC_NR_CC_NUM][MAX_BWP_NUM];
kal_uint32 ulFreq[IDC_NR_CC_NUM][MAX_BWP_NUM];
kal_uint32 dlARFCN[IDC_NR_CC_NUM][MAX_BWP_NUM];
kal_uint32 ulARFCN[IDC_NR_CC_NUM][MAX_BWP_NUM];
}nl1_ctrl_idc_freq_ntf_struct;
typedef struct _nl1_ctrl_idc_frame_cfg_ntf_struct
{
LOCAL_PARA_HDR
kal_uint8 srv_num;
kal_uint8 frame_cfg_num[IDC_NR_CC_NUM];
kal_uint16 dlSlots[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG];
kal_uint16 flexibleSymbols[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG];
kal_uint16 ulSlots[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG];
kal_uint16 period[IDC_NR_CC_NUM][NR_MAX_FRAME_CFG];
}nl1_ctrl_idc_frame_cfg_ntf_struct;
typedef struct _nl1_ctrl_idc_sch_ntf_struct
{
LOCAL_PARA_HDR
kal_bool enterSch;
}nl1_ctrl_idc_sch_ntf_struct;
typedef struct _nl1_ctrl_idc_bwp_ntf_struct
{
LOCAL_PARA_HDR
kal_uint8 dl_actv_bwp_index[IDC_NR_CC_NUM];
kal_uint8 ul_actv_bwp_index[IDC_NR_CC_NUM];
}nl1_ctrl_idc_bwp_ntf_struct;
typedef struct _nl1_sched_idc_scell_actv_ntf_struct
{
LOCAL_PARA_HDR
kal_uint32 srvActvBmp;
}nl1_sched_idc_scell_actv_ntf_struct;
typedef struct _nl1_ctrl_idc_drx_config_ntf_struct
{
LOCAL_PARA_HDR
kal_bool isNoDRX;
kal_uint32 onDuration;
kal_uint32 startOffst;
kal_uint32 shortDRXCycle;
kal_uint32 longDRXCycle;
nl1_ctrl_idc_drx_type_enum drxType;
}nl1_ctrl_idc_drx_config_ntf_struct;
typedef struct _nl1_ctrl_idc_ho_ntf_struct
{
LOCAL_PARA_HDR
kal_bool isHO;
}nl1_ctrl_idc_ho_ntf_struct;
typedef struct _idc_nl1_sched_rx_protect_status_struct
{
NL1_SIM_IDX_E sim_index;
kal_bool active;
kal_uint8 ccIndex;
kal_uint32 freq;
idc_nl1_sched_rx_protect_type_enum type;
}idc_nl1_sched_rx_protect_status_struct;
typedef struct _nl1_sched_idc_psim_swap_req_struct
{
LOCAL_PARA_HDR
kal_uint8 new_psim_index;
}nl1_sched_idc_psim_swap_req_struct;
typedef struct _idc_nl1_sched_rx_gap_req_struct
{
NL1_SIM_IDX_E sim_idx;
kal_uint8 seq_num;
idc_nl1_sched_rx_status_enum rx_status[IDC_NR_CC_NUM];
}idc_nl1_sched_rx_gap_req_struct;
typedef struct _nl1_sched_idc_rx_gap_susp_cnf_struct
{
LOCAL_PARA_HDR
kal_uint8 ack_num;
nl1_sched_idc_cnf_status_enum cnf_status;
}nl1_sched_idc_rx_gap_susp_cnf_struct;
typedef struct _nl1_ctrl_idc_actv_ntf_struct
{
LOCAL_PARA_HDR
nl1_rat_status_enum nr_rat_status;
nl1_rat_set_cause_enum cause;
}nl1_ctrl_idc_actv_ntf_struct;
typedef struct _idc_nl1_sched_psim_swap_cnf_struct
{
LOCAL_PARA_HDR
kal_uint8 sim_index;
}idc_nl1_sched_psim_swap_cnf_struct;
#if ((defined(__IDC_ENABLED__)) && (defined (__IDC_NRTC_ENABLE__)))
typedef struct _idc_nl1_nrtc_tx_power_breach_threshold_ind_struct
{
LOCAL_PARA_HDR
kal_uint8 cc_idx;
kal_bool breachThreshold;
}idc_nl1_nrtc_tx_power_breach_threshold_ind_struct;
#endif
#endif