| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /***************************************************************************** |
| * |
| * Filename: |
| * --------- |
| * ul1_cnst.h |
| * |
| * Project: |
| * -------- |
| * WCDMA_Software |
| * |
| * Description: |
| * ------------ |
| * Layer 1 related constant and enum definitions for MediaTek WCDMA software |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| *------------------------------------------------------------------------------ |
| * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| |
| #ifndef _UL1_CNST_H |
| #define _UL1_CNST_H |
| |
| #include "ul1_protected_cnst.h" |
| |
| #define UL1_SIM_IDX_INVALID ( 0xFF ) |
| |
| /*-------- BCH related constant ----------------------*/ |
| #define FDD_MAX_SIB_PATTERN 31 /* The maximum number of BCH SIB blocks */ |
| #define FDD_MAX_SIB_SEG_COUNT 16 /* The maximum number of segments in 1 BCH SIB */ |
| |
| /*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/ |
| /* MAUI_02850564 : According to spec 25.306 and MTK implementation, FDD_MAX_DL_DATA should be 956 bytes : |
| FDD_MAX_DL_DATA = 6400 + 24*32 (CRC bits*MaxTBNum) + 7*32 (max bit offset for each TB) |
| + 7*32 (max byte alignment for each TB) + 4*8 (4 bytes report header) = 7648 bits = 956 bytes. |
| But we have seen an overspec case : PS TrCH 336*24 + SRB TrCH 148*1, thus define FDD_MAX_DL_DATA as 1150 bytes. |
| FDD_MAX_DL_DATA = [PS part] 336*24 + 24*24 + 7*24 + 7*24 |
| [SRB part] + 148*1 + 24*1 + 7*1 + 7*1 |
| + 4*8 (4 bytes report header) = 9194 bits = 1149.25 bytes. */ |
| #define FDD_MAX_DL_DATA 1150 /* Maximum DL transport block array size. */ |
| #define FDD_MAX_TRCH_NUM 8 /* Maximum Simultaneous TrCHs */ |
| #define FDD_MAX_DL_TB 32 /* Maximum simultaneous DL TBs */ |
| #define FDD_MAX_DL_TFC 128 /* Maximum number of TFCs per DL CCTrCH */ |
| #define FDD_MAX_DL_TRCH 32 /* Maximum number of DL TrCH */ |
| #define FDD_MAXTF 32 /* Maximum number of TF per UL or DL TrCH TFS */ |
| #define FDD_MAXFACHPCH 8 /* Maximum number of TrCHs per S-CCPCH CCTrCH */ |
| #define FDD_MAX_UL_TFC 64 /* Maximum number of TFCs per UL CCTrCH */ |
| #define FDD_MAX_UL_TB 16 /* Maximum simultaneous DUL TBs */ |
| #define FDD_MAX_UL_TFs 32 /* Maximum numbre of TFs per UL CCTrCH */ |
| #define FDD_MAX_UL_TRCH 32 /* Maximum number of UL TrCH */ |
| |
| /*-------- PhyCh related constant (For UL/DL 384Kbps capability) ----------------------*/ |
| #define FDD_MAX_TGPS 6 /* Maximum number of TGPS sequences */ |
| #define FDD_MAX_PENDING_TGPS_NUM 5 /* Maximum number of pending confiuration for one TGPS */ |
| #define FDD_MAX_TGMP_NUM 5 /* Maximum number of TGMP */ |
| #define FDD_MAX_ASC 8 /* Maximum access service class number */ |
| #define FDD_MAX_DLDPCH 3 /* Maximum number of physical channel codes per DL DPCH CCTrCH */ |
| #define FDD_MAX_ULDPCH 6 /* Maximum number of physical channel codes per UL DPCH CCTrCH */ |
| #define FDD_MAX_RL 8 /* Maximum number of DPCH radio links in active set */ |
| |
| #ifdef __UMTS_R10__ |
| |
| #ifdef __MULTI_CARRIER_HSDPA__ /* __MULTI_CARRIER_HSDPA__ = 3 or 4 */ |
| #define FDD_MAX_ADDI_DC_HSDPA ( __MULTI_CARRIER_HSDPA__ - 2 ) /* [R10] The maximum additional dc-hsdpa frequency */ |
| #else /*__MULTI_CARRIER_HSDPA__*/ |
| #define FDD_MAX_ADDI_DC_HSDPA 1 /* default value is 1. */ |
| #endif /*__MULTI_CARRIER_HSDPA__*/ |
| |
| #endif |
| |
| |
| |
| /*-------- Measurement related constant ----------------------*/ |
| #ifdef __GEMINI__ |
| #define FDD_MAX_FREQ_RANGE 15 /* Max size of frequency ranges for frequency scan. |
| Extend range number for Enhanced Freq Scan in Gemini2.0.*/ |
| #else |
| #define FDD_MAX_FREQ_RANGE 8 /* Max size of frequency ranges for frequency scan. */ |
| #endif /*__GEMINI__*/ |
| |
| #define FDD_MAX_FREQ_EXCLUDE 13 /*Max possible UARFCNs per PLMN*/ |
| #define FDD_MAX_FREQ_LIST 36 /* Max size of stored frequency list for frequency scan */ |
| #define FDD_MAX_PREFERRED_PSC 96 /* Max number of preferred cells on 1 frequency for frequency scan */ |
| #define FDD_MAX_NUM_MEAS_CELL 32 /* Max number of reported cells in the measurement cell indication primitive */ |
| #define FDD_MAX_NUM_MEASURED_CELL 96 /* Max number of monitored cells in the measurement cell request primitive */ |
| #define FDD_MAX_NUM_SFN_CELL 12 /* Max number of cells whose SFN will be read by L1 when nc_nbr_dch=0 */ |
| |
| #ifdef __UMTS_R9_UL1__ |
| #define FDD_MAX_UMTS_FREQ 4 /* Maximum number of FDD frequency supported in a UMTS UE : 1st intra + 2nd intra + inter x 2 */ |
| #else |
| #define FDD_MAX_UMTS_FREQ 3 /* Maximum number of FDD frequency supported in a UMTS UE */ |
| #endif /*__UMTS_R9_UL1__*/ |
| |
| #define FDD_MAX_RSSI_SNIFFER_SCAN_LIST 12 /* Maximum number of RSSI SNIFFER UARFCN (Add by Janet) */ |
| |
| /*-------- Magic value related constant ----------------------*/ |
| #define FDD_TM_VALID 307200 /* Default value representing Tm known. 38400*8 */ |
| #define FDD_TM_INVALID ( -1 ) /* Default value representing Tm unknown. */ |
| #define FDD_OFF_VALID 4096 /* Default valure representing OFF known. */ |
| #define FDD_OFF_INVALID ( -1 ) /* Default value representing OFF unknown. */ |
| #define FDD_RSSI_INVALID ( -32768 ) /* Default value representing RSSI unknown. */ |
| #define FDD_RSCP_INVALID ( -32768 ) /* Default value representing RSCP unknown. */ |
| #define FDD_ECN0_INVALID ( -32768 ) /* Default value representing EcNo unknown. */ |
| #define FDD_UARFCN_INVALID 65535 /* Invalid UARFCN for setting empty freq. entry in meas. config req. */ |
| |
| |
| |
| |
| /*-------- BMC (CTCH) related constant ----------------------*/ |
| #define FDD_BMC_MAX_BITMAP_SIZE 64 /* CTCH level 2 bitmap siz */ |
| |
| /*-------- Activation time related constant ----------------------*/ |
| #define FDD_CFN_IMMEDIATE (kal_int16)(-1) /* Immediate CFN activation time. */ |
| #define FDD_SFN_IMMEDIATE (kal_int16)(-1) /* Immediate SFN activation time. */ |
| |
| /*-------- [R5R6] HS-DSCH related ----------------------*/ |
| #ifdef __MULTI_CARRIER_HSDPA__ |
| #define FDD_MAX_SUPPORT_CELL __MULTI_CARRIER_HSDPA__ /* Possible __MULTI_CARRIER_HSDPA__ value is 3,4 or not defined. */ |
| #else |
| #define FDD_MAX_SUPPORT_CELL 2 /* 1 */ /*Use 3 before __MULTI_CARRIER_HSDPA__ defined in project for easy development*/ |
| #endif |
| |
| #define FDD_MAX_HS_SCCH_NUM 4 |
| #define FDD_MAX_HS_PROCESS_NUM 8 |
| #define FDD_MAX_HS_PDU_NUM_IN_FRAME 5 |
| #ifdef __UMTS_R7__ |
| #define FDD_MAX_HS_PDU_SIZE_IN_BITS 42192 |
| #else |
| #define FDD_MAX_HS_PDU_SIZE_IN_BITS 14411 |
| #endif |
| #define FDD_MAX_HS_PDU_SIZE_IN_BYTES (((FDD_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4) |
| #ifdef __UMTS_R8__ |
| |
| #define FDD_HDA_BUFF_NUM_PRI 45 // 5*8(MAX flow B * HARQ process NUM) + 5 (less mode) |
| #define FDD_HDA_BUFF_NUM_SEC 8 // HARQ process NUM |
| |
| #define FDD_MAX_HS_PDU_BUFF_NUM 160 // for DC hsdpa |
| #define FDD_HDA_BUFF_NUM (FDD_HDA_BUFF_NUM_PRI + FDD_HDA_BUFF_NUM_SEC * (FDD_MAX_SUPPORT_CELL-1)) |
| #else |
| #define FDD_MAX_HS_PDU_BUFF_NUM 40 |
| #endif |
| #define FDD_MAX_HS_RB_NUM 3 |
| #define FDD_MAX_EDCH_RL 4 |
| #define FDD_MAX_REF_ETFCI_NUM 8 |
| #define FDD_MAX_ETFC_NUM 128 |
| #define FDD_MIN_NTX1_10MS 8 /* 25.212 s4.4.4 */ |
| #define FDD_MAX_NTX1_10MS (15 - FDD_MIN_NTX1_10MS + 1) |
| |
| #define FDD_HS_PDU_UL1_CC_DELAY_PREALLOCATION_NUM (FDD_MAX_SUPPORT_CELL*5) |
| #define FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT 0 |
| #define FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT 1 |
| #define FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT 2 |
| #define FDD_PHY_HSDSCH_MAC_EV_RESET_BIT 3 |
| #define FDD_PHY_HSDSCH_MAC_EV_SETUP (0x1 << FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT) /* 0x01 */ |
| #define FDD_PHY_HSDSCH_MAC_EV_RELEASE (0x1 << FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT) /* 0x02 */ |
| #define FDD_PHY_HSDSCH_MAC_EV_MODIFY (0x1 << FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT) /* 0x04 */ |
| #define FDD_PHY_HSDSCH_MAC_EV_RESET (0x1 << FDD_PHY_HSDSCH_MAC_EV_RESET_BIT) /* 0x08 */ |
| |
| /*-----------Add PLMN , RAC and LAC info to Container Req---------------------------*/ |
| #define NUM_PLMN_INFO 3 |
| #define NUM_MCC_MNC 3 |
| |
| #endif |
| |