| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _DEBUG_FLAG_H |
| #define _DEBUG_FLAG_H |
| #include "reg_base.h" |
| #include "drv_comm.h" |
| |
| #define TOP_MDSYS 0 |
| #define TOP_APPERISYS 1 |
| #define TOP_MODEMSYS 2 |
| #define TOP_MODEMSYS2 3 |
| #define TOP_TDDSYS 4 |
| #define TOP_MML1 5 |
| #define TOP_LA_TEST 6 //(only FPGA mode) |
| #define TOP_CLKCTL 7 |
| #define TOP_EFUSE 8 |
| #define TOP_APCIRQ 9 |
| |
| #define MDSYS_RSTCTL 0 |
| #define MDSYS_GPIOMUX 3 |
| #define MDSYS_MDCFG_AHB2APB 4 |
| #define MDSYS_DBSYS 5 |
| #define MDSYS_MD_TOPSM 6 |
| #define MDSYS_MD_OSTIMER 7 |
| #define MDSYS_AP_TOPSM 8 |
| #define MDSYS_AP_OSTIMER 9 |
| #define MDSYS_MEMSYS 10 |
| #define MDSYS_ARM7 11 |
| #define MDSYS_LTEL2 12 |
| #define MDSYS_MDINFRASYS 13 |
| #define MDSYS_MDPERISYS 14 |
| #define MDSYS_MDMCUSYS 15 |
| |
| #define APPERISYS_MD2AP_CLDMA 0 |
| #define APPERISYS_AP2MD_CLDMA 1 |
| #define APPERISYS_MSDC_0P 2 |
| #define APPERISYS_NFI 3 |
| #define APPERISYS_IPSEC 4 |
| #define APPERISYS_USB20 5 |
| #define APPERISYS_ETHER_NIC 6 |
| #define APPERISYS_MSDC_1P 7 |
| #define APPERISYS_AP_UART 9 |
| #define APPERISYS_APGDMA 10 |
| #define APPERISYS_SPI 11 |
| #define APPERISYS_APPERISYS_BUSMON 12 |
| #define APPERISYS_APPERI_DBG0 13 |
| #define APPERISYS_AP_GPTM 14 |
| #define APPERISYS_APMCUSYS 15 |
| #define APPERISYS_SSUSB 17 |
| #define APPERISYS_APMCUSYS_BUSMON 18 |
| #define APPERISYS_PFC 19 |
| #define APPERISYS_TRACE 20 |
| #define APPERISYS_PLAYBACK 21 |
| |
| #define MDPERISYS_MD_UART 0 |
| #define MDPERISYS_SUART0 1 |
| #define MDPERISYS_MD_GDMA 2 |
| #define MDPERISYS_MD_CIRQ 3 |
| #define MDPERISYS_USIM1 4 |
| #define MDPERISYS_USIM2 5 |
| #define MDPERISYS_RTC 6 |
| #define MDPERISYS_SUART1 7 |
| #define MDPERISYS_GPTM 8 |
| #define MDPERISYS_LED 9 |
| #define MDPERISYS_SDIO 10 |
| |
| #define MDINFRASYS_BUS_FABRIC 0 |
| #define MDINFRASYS_BUSMON 1 |
| |
| #define __SET_SEL_64X1(SUBSYS_ID,REG_ADDR0, REG_ADDR1) do{ \ |
| kal_uint32 __sel_id; \ |
| __sel_id = (SUBSYS_ID)&0xff; \ |
| __sel_id = __sel_id | (__sel_id<<8) | (__sel_id <<16) | (__sel_id <<24); \ |
| DRV_WriteReg32((REG_ADDR0),__sel_id); \ |
| DRV_WriteReg32((REG_ADDR1),__sel_id); \ |
| }while(0) |
| |
| #define __SET_SEL_32X2(SUBSYS_ID0,SUBSYS_ID1,REG_ADDR0, REG_ADDR1) do{ \ |
| kal_uint32 __sel_id0,__sel_id1; \ |
| __sel_id0 = (SUBSYS_ID0)&0xff; \ |
| __sel_id1 = (SUBSYS_ID1)&0xff; \ |
| __sel_id0 = __sel_id0 | (__sel_id0<<8) | (__sel_id0 <<16) | (__sel_id0 <<24); \ |
| __sel_id1 = __sel_id1 | (__sel_id1<<8) | (__sel_id1 <<16) | (__sel_id1 <<24); \ |
| DRV_WriteReg32((REG_ADDR0),__sel_id0); \ |
| DRV_WriteReg32((REG_ADDR1),__sel_id1); \ |
| }while(0) |
| |
| #define __SET_SEL_16X4(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3,REG_ADDR0, REG_ADDR1) do{ \ |
| kal_uint32 __sel_id0,__sel_id1; \ |
| __sel_id0 = ((SUBSYS_ID0)&0xff) | (((SUBSYS_ID1)&0xff)<<16); \ |
| __sel_id0 = __sel_id0 | (__sel_id0<<8); \ |
| __sel_id1 = ((SUBSYS_ID2)&0xff) | (((SUBSYS_ID3)&0xff)<<16); \ |
| __sel_id1 = __sel_id1 | (__sel_id1<<8); \ |
| DRV_WriteReg32((REG_ADDR0),__sel_id0); \ |
| DRV_WriteReg32((REG_ADDR1),__sel_id1); \ |
| }while(0) |
| |
| #define __SET_SEL_8X8(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3,SUBSYS_ID4,SUBSYS_ID5,SUBSYS_ID6,SUBSYS_ID7,REG_ADDR0, REG_ADDR1) do{ \ |
| kal_uint32 __sel_id0,__sel_id1; \ |
| __sel_id0 = ((SUBSYS_ID0)&0xff) | (((SUBSYS_ID1)&0xff)<<8)| (((SUBSYS_ID2)&0xff)<<16)| (((SUBSYS_ID3)&0xff)<<24); \ |
| __sel_id1 = ((SUBSYS_ID4)&0xff) | (((SUBSYS_ID5)&0xff)<<8)| (((SUBSYS_ID6)&0xff)<<16)| (((SUBSYS_ID7)&0xff)<<24); \ |
| DRV_WriteReg32((REG_ADDR0),__sel_id0); \ |
| DRV_WriteReg32((REG_ADDR1),__sel_id1); \ |
| }while(0) |
| |
| #define SET_TOPSUBSYS_SEL_64X1(SUBSYS_ID) \ |
| __SET_SEL_64X1(SUBSYS_ID,BASE_ADDR_TOPMISC+0xc,BASE_ADDR_TOPMISC+0x10) |
| |
| |
| #define SET_TOPSUBSYS_SEL_32X2(SUBSYS_ID0,SUBSYS_ID1) \ |
| __SET_SEL_32X2(SUBSYS_ID0,SUBSYS_ID1,BASE_ADDR_TOPMISC+0xc,BASE_ADDR_TOPMISC+0x10) |
| |
| |
| #define SET_TOPSUBSYS_SEL_16X4(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3) \ |
| __SET_SEL_16X4(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3,BASE_ADDR_TOPMISC+0xc,BASE_ADDR_TOPMISC+0x10) |
| |
| |
| #define SET_TOPSUBSYS_SEL_8X8(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3,SUBSYS_ID4,SUBSYS_ID5,SUBSYS_ID6,SUBSYS_ID7) \ |
| __SET_SEL_8X8(SUBSYS_ID0,SUBSYS_ID1,SUBSYS_ID2,SUBSYS_ID3,SUBSYS_ID4,SUBSYS_ID5,SUBSYS_ID6,SUBSYS_ID7,BASE_ADDR_TOPMISC+0xc,BASE_ADDR_TOPMISC+0x10) |
| |
| |
| #define SET_MDSYS_SUBMOD_SEL_64X1(SUBMOD_ID) \ |
| __SET_SEL_64X1(SUBMOD_ID,BASE_ADDR_MDDBGMON+0x8,BASE_ADDR_MDDBGMON+0xc) |
| |
| |
| #define SET_MDSYS_SUBMOD_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1) \ |
| __SET_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1,BASE_ADDR_MDDBGMON+0x8,BASE_ADDR_MDDBGMON+0xc) |
| |
| |
| #define SET_MDSYS_SUBMOD_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3) \ |
| __SET_SEL_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,BASE_ADDR_MDDBGMON+0x8,BASE_ADDR_MDDBGMON+0xc) |
| |
| |
| #define SET_MDSYS_SUBMOD_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7) \ |
| __SET_SEL_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7,BASE_ADDR_MDDBGMON+0x8,BASE_ADDR_MDDBGMON+0xc) |
| |
| #define SET_MDSYS_MOD_FLAG_SEL(FLAG_SEL0,FLAG_SEL1) do{\ |
| DRV_WriteReg32(BASE_ADDR_MDDBGMON,FLAG_SEL0);\ |
| DRV_WriteReg32(BASE_ADDR_MDDBGMON+4,FLAG_SEL1);\ |
| }while(0) |
| |
| #define GET_MDSYS_FLAG0() DRV_Reg32(BASE_ADDR_MDDBGMON+0x10) |
| #define GET_MDSYS_FLAG1() DRV_Reg32(BASE_ADDR_MDDBGMON+0x14) |
| |
| #define SET_APPERISYS_SUBMOD_SEL_64X1(SUBMOD_ID) \ |
| __SET_SEL_64X1(SUBMOD_ID,BASE_ADDR_APDBGMON+0x8,BASE_ADDR_APDBGMON+0xc) |
| |
| |
| #define SET_APPERISYS_SUBMOD_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1) \ |
| __SET_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1,BASE_ADDR_APDBGMON+0x8,BASE_ADDR_APDBGMON+0xc) |
| |
| |
| #define SET_APPERISYS_SUBMOD_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3) \ |
| __SET_SEL_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,BASE_ADDR_APDBGMON+0x8,BASE_ADDR_APDBGMON+0xc) |
| |
| |
| #define SET_APPERISYS_SUBMOD_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7) \ |
| __SET_SEL_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7,BASE_ADDR_APDBGMON+0x8,BASE_ADDR_APDBGMON+0xc) |
| |
| #define SET_APPERISYS_MOD_FLAG_SEL(FLAG_SEL0,FLAG_SEL1) do{\ |
| DRV_WriteReg32(BASE_ADDR_APDBGMON,FLAG_SEL0);\ |
| DRV_WriteReg32(BASE_ADDR_APDBGMON+4,FLAG_SEL1);\ |
| }while(0) |
| |
| #define GET_APPERISYS_FLAG0() DRV_Reg32(BASE_ADDR_APDBGMON+0x10) |
| #define GET_APPERISYS_FLAG1() DRV_Reg32(BASE_ADDR_APDBGMON+0x14) |
| |
| |
| #define SET_MDPERISYS_SUBMOD_SEL_64X1(SUBMOD_ID) \ |
| __SET_SEL_64X1(SUBMOD_ID,BASE_ADDR_MDPERIDBGMON+0x8,BASE_ADDR_MDPERIDBGMON+0xc) |
| |
| |
| #define SET_MDPERISYS_SUBMOD_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1) \ |
| __SET_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1,BASE_ADDR_MDPERIDBGMON+0x8,BASE_ADDR_MDPERIDBGMON+0xc) |
| |
| |
| #define SET_MDPERISYS_SUBMOD_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3) \ |
| __SET_SEL_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,BASE_ADDR_MDPERIDBGMON+0x8,BASE_ADDR_MDPERIDBGMON+0xc) |
| |
| |
| #define SET_MDPERISYS_SUBMOD_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7) \ |
| __SET_SEL_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7,BASE_ADDR_MDPERIDBGMON+0x8,BASE_ADDR_MDPERIDBGMON+0xc) |
| |
| #define SET_MDPERISYS_MOD_FLAG_SEL(FLAG_SEL0,FLAG_SEL1) do{\ |
| DRV_WriteReg32(BASE_ADDR_MDPERIDBGMON,FLAG_SEL0);\ |
| DRV_WriteReg32(BASE_ADDR_MDPERIDBGMON+4,FLAG_SEL1);\ |
| }while(0) |
| |
| #define GET_MDPERISYS_FLAG0() DRV_Reg32(BASE_ADDR_MDPERIDBGMON+0x10) |
| #define GET_MDPERISYS_FLAG1() DRV_Reg32(BASE_ADDR_MDPERIDBGMON+0x14) |
| |
| |
| #define SET_MDINFRASYS_SUBMOD_SEL_64X1(SUBMOD_ID) \ |
| __SET_SEL_64X1(SUBMOD_ID,BASE_ADDR_MDINFRADBGMON+0x8,BASE_ADDR_MDINFRADBGMON+0xc) |
| |
| |
| #define SET_MDINFRASYS_SUBMOD_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1) \ |
| __SET_SEL_32X2(SUBMOD_ID0,SUBMOD_ID1,BASE_ADDR_MDINFRADBGMON+0x8,BASE_ADDR_MDINFRADBGMON+0xc) |
| |
| |
| #define SET_MDINFRASYS_SUBMOD_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3) \ |
| __SET_SEL_16X4(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,BASE_ADDR_MDINFRADBGMON+0x8,BASE_ADDR_MDINFRADBGMON+0xc) |
| |
| |
| #define SET_MDINFRASYS_SUBMOD_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7) \ |
| __SET_SEL_8X8(SUBMOD_ID0,SUBMOD_ID1,SUBMOD_ID2,SUBMOD_ID3,SUBMOD_ID4,SUBMOD_ID5,SUBMOD_ID6,SUBMOD_ID7,BASE_ADDR_MDINFRADBGMON+0x8,BASE_ADDR_MDINFRADBGMON+0xc) |
| |
| #define SET_MDINFRASYS_MOD_FLAG_SEL(FLAG_SEL0,FLAG_SEL1) do{\ |
| DRV_WriteReg32(BASE_ADDR_MDINFRADBGMON,FLAG_SEL0);\ |
| DRV_WriteReg32(BASE_ADDR_MDINFRADBGMON+4,FLAG_SEL1);\ |
| }while(0) |
| |
| #define GET_MDINFRASYS_FLAG0() DRV_Reg32(BASE_ADDR_MDINFRADBGMON+0x10) |
| #define GET_MDINFRASYS_FLAG1() DRV_Reg32(BASE_ADDR_MDINFRADBGMON+0x14) |
| |
| #define DEBUG_FLAG_LA_TEST() do{SET_TOPSUBSYS_SEL_64X1(TOP_CLKCTL);}while(0) |
| #endif |