blob: b09f1e70bf9a0d1dc7575235a1888fda89838f14 [file] [log] [blame]
/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2001
*
*****************************************************************************/
/*****************************************************************************
*
* Filename:
* ---------
* idc_internal.h
*
* Project:
* --------
* MOLY
*
* Description:
* ------------
* Header file of DCL (Driver Common Layer) for IDC.
*
* Author:
* -------
* -------
*
****************************************************************************/
#ifndef __IDC_INTERNAL_H__
#define __IDC_INTERNAL_H__
#include "dcl.h"
#include "kal_general_types.h"
#include "drv_comm.h"
#include "dcl_idc.h"
#define IDC_PM_NUM 5
#define IDC_NEW_PM_IDX 4
#define IDC_UART_TXFIFO_SIZE 128
#define IDC_MAX_NUM_BYTE 9
#if defined(__MD97__) || (defined(__MD97P__))
#define IDC_MAX_EVENT_NUM 32
//Petrus
#define IDC_LTE_STA_EVENT_IDX 1
#define IDC_LTE_MAX_EVENT_IDX 15
#define IDC_NR_STA_EVENT_IDX 17
#define IDC_NR_MAX_EVENT_IDX 31
#define IDC_COMMON_STA_EVENT_IDX 16
#if !defined(MT6297)
#define IDC_SRAM_WRAP_IDX 0xC
//#define IDC_PM_NUM 11 // 4+1+6
#define IDC_NEW_PM_ERR_NUM 6
#define IDC_NEW_PM_ERR_STA_IDX 5
#define IDC_NEW_PM_ERR_STOP_IDX 10
#define IDC_NEW_PM_ERR1_IDX 5
#define IDC_NEW_PM_ERR2_IDX 8
#define IDC_NEW_PM_ERR3_IDX 9
#define IDC_NEW_PM_ERR4_IDX 10
#define IDC_NEW_PM_ERR5_IDX 6
#define IDC_NEW_PM_ERR6_IDX 7
#define IDC_MAX_SRAM_SIZE 156
#define IDC_MAX_SRAM_IDX 39
#define IDC_UART_RXFIFO_SIZE 64
#define IDC_MAX_CC_NUM 6
#define IDC_MAX_REMAPPING_NUM 64
#define IDC_MAX_CC_COMBINATION 4096
#define IDC_NEW_PM_BNUM 7
#else
#define IDC_SRAM_WRAP_IDX 0x0
//#define IDC_PM_NUM 8 // 4+1+3
#define IDC_NEW_PM_ERR_NUM 3
#define IDC_NEW_PM_ERR_STA_IDX 5
#define IDC_NEW_PM_ERR_STOP_IDX 7
#define IDC_NEW_PM_ERR1_IDX 5
#define IDC_NEW_PM_ERR2_IDX 6
#define IDC_NEW_PM_ERR3_IDX 7
#define IDC_MAX_SRAM_SIZE 128
#define IDC_MAX_SRAM_IDX 32
#define IDC_UART_RXFIFO_SIZE 32
#define IDC_MAX_CC_NUM 5
#define IDC_MAX_REMAPPING_NUM 32
#define IDC_MAX_CC_COMBINATION 1024
#define IDC_NEW_PM_BNUM 4
#endif
#else
#define IDC_MAX_EVENT_NUM 16
#define IDC_MAX_SRAM_SIZE 78
#endif
void drv_idc_init(kal_bool is_sm);
void drv_idc_init_uart(void);
void drv_idc_init_m2c_bridge(void);
void drv_idc_init_isr(void);
void drv_idc_uart_activate(void);
void drv_idc_get_support(IDC_SUPPORT_T *support);
void drv_idc_conn_txrx_count(kal_bool is_start);
void drv_idc_open(kal_uint32 mod_id);
void drv_idc_close(void);
void drv_idc_set_dcb_config(IDC_CTRL_DCB_CONFIG_T idc_config);
void drv_idc_get_dcb_config(IDC_CTRL_DCB_CONFIG_T *DCB);
void drv_idc_set_baudrate(kal_uint32 baudrate);
void drv_idc_set_fifo_trigger(kal_uint8 rx_threshold);
void drv_idc_set_pm_config(kal_uint8 pm_idx, kal_uint8 priority, kal_uint8 priority_bit_en, kal_uint8 pattern, kal_uint8 pattern_bit_en);
void drv_idc_get_pm_config(kal_uint8 pm_idx, kal_uint8 *priority, kal_uint8 *priority_bit_en, kal_uint8 *pattern, kal_uint8 *pattern_bit_en);
void drv_idc_send_event(IDC_EVENT_T event, kal_bool sleep_mode);
kal_bool drv_idc_send_event_95(IDC_EVENT_T event, kal_bool sleep_mode);
kal_bool drv_idc_send_event_97(IDC_EVENT_T event, kal_bool sleep_mode);
void drv_idc_schedule_event(IDC_EVENT_T event);
kal_bool drv_idc_schedule_event_95(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
kal_bool drv_idc_schedule_event_97(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
kal_bool drv_idc_schedule_gps_blank_event(kal_uint8 rat_status, kal_bool gps_mode, kal_uint32 frc_time);
void drv_idc_schedule_update(kal_uint32 time);
void drv_idc_schedule_update_95(kal_uint32 time);
void drv_idc_schedule_update_97(kal_uint32 time);
void drv_idc_stop_event(kal_uint32 bitmap);
void drv_idc_stop_event_97(kal_uint32 bitmap);
void drv_idc_purge(UART_buffer dir);
void drv_idc_get_schedule_status(kal_uint32 schedule_status);
void drv_idc_get_schedule_status_2(kal_uint32 schedule_status);
kal_bool drv_idc_check_event_send_out(void);
DCL_STATUS drv_idc_set_pin_config(IDC_PIN_MODE_T pin_mode);
DCL_STATUS drv_idc_get_pin_config(IDC_PIN_MODE_T *pin_mode);
void idc_uart_lisr(kal_uint32 vector);
void idc_uart_hisr(void);
void idc_pm_lisr(kal_uint32 vector);
void idc_pm_hisr(void);
void idc_send_rx_data_by_ilm(void);
void idc_send_rx_data_by_ilm_95(void);
void drv_idc_return_drop_cmd(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd);
int drv_idc_register_pm_callback(kal_uint8 pm_idx, IDC_DRV_TO_EL1_CALLBACK func_ptr , kal_bool private_data) ;
int drv_idc_register_pm_callback_95(kal_uint8 pm_idx, IDC_DRV_TO_EL1_CALLBACK func_ptr , void *private_data);
int drv_idc_unregister_pm_callback(kal_uint8 pm_idx) ;
void drv_idc_set_new_pm_config(kal_uint8 pattern0, kal_uint8 pattern1);
void drv_idc_get_new_pm_config(kal_uint8 *pattern0, kal_uint8 *pattern1);
void drv_idc_force_on_rf(kal_uint8 rf_path);
void drv_idc_set_remapping_config(kal_uint8 remapping_table, kal_uint8 remapping_table_en);
//__MD97__
void idc_set_immediate_event(kal_uint32 event_idx, kal_uint8* buf, kal_uint32 byte_num, kal_uint32 start_sram_idx, kal_uint32 end_sram_idx);
//Petrus
void drv_idc_set_sram_wrap_idx(kal_uint32 start_idx);
void drv_idc_schedule_update_n_return_rftx(kal_uint32 time, kal_uint8 *rf_path);
kal_bool drv_idc_schedule_event_lte_nr(IDC_EVENT_T event, kal_uint8 event_type,IDC_CTRL_DROP_CMD_T *drop_cmd);
void drv_idc_return_drop_cmd_lte_nr(IDC_EVENT_T event, IDC_CTRL_DROP_CMD_T *drop_cmd, kal_uint8 event_type);
void idc_auto_tx_lisr(kal_uint32 vector);
void drv_idc_auto_tx_config(kal_uint8 tx_susp_quota, kal_uint8 reset_quota);
void drv_idc_auto_tx_en(kal_uint8 auto_tx_en);
void drv_idc_auto_tx_dis(void);
void drv_idc_set_enable_rat(kal_uint8 rat_status);
void drv_idc_set_disable_rat(kal_uint8 rat_status);
void drv_idc_wakeup_notify(kal_uint8 rat_status);
void drv_idc_sleep_notify(kal_uint8 rat_status);
//GPS_B13_B14
void drv_idc_gps_b13_b14_set(kal_uint8 rat_status, kal_uint16 raw_data);
//GPS_L1_L5
kal_bool drv_idc_schedule_gps_l1_l5_blank_event(kal_uint8 rat_status, kal_uint8 raw_data, kal_uint32 frc_time);
struct idc_drv_to_el1_callback {
IDC_DRV_TO_EL1_CALLBACK callback_func ;
#if defined(__MD93__)
kal_bool private_data ;
#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
void *private_data ;
#endif
};
typedef struct
{
kal_uint32 owner_id;
kal_uint8 main_state;
kal_bool intr_en;
kal_uint8 schedule_state;
kal_uint8 event_cnt;
kal_uint8 event_pending_cnt; // Pend an event when SRAM is full
kal_uint32 event_offset_table[IDC_MAX_EVENT_NUM];
#if defined(__MD93__)
kal_uint16 event_data_table[IDC_MAX_EVENT_NUM];
#elif defined(__MD95__) || defined(__MD97__) || (defined(__MD97P__))
kal_uint8 event_data_table[IDC_MAX_EVENT_NUM][9];
kal_uint8 sram_table_usage[IDC_MAX_SRAM_SIZE];
kal_uint32 event_byte_num[IDC_MAX_EVENT_NUM];
kal_uint32 event_sram_sta_idx[IDC_MAX_EVENT_NUM];
kal_uint8 sram_w_index;
#endif
kal_uint8 event_w_index;
kal_uint32 event_longest_time;
kal_uint8 event_longest_index;
kal_uint32 event_usage_bit_map;
kal_uint32 event_pending_offset_table[IDC_MAX_EVENT_NUM]; // Store the index that indicates which event is pending
kal_uint16 event_pending_data_table[IDC_MAX_EVENT_NUM];
kal_uint32 rx_buf;
kal_uint32 phy_time;//use for gen93/gen95
kal_uint32 frc_time;//use for gen97
kal_uint8 event_w_index_lte;
kal_uint8 event_w_index_nr;
kal_uint8 event_w_index_com;
IDC_CTRL_DCB_CONFIG_T DCB;
IDC_PIN_MODE_T pin_mode;
struct idc_drv_to_el1_callback pm_cb_handle[IDC_PM_NUM];
} idc_struct_t;
typedef struct
{
#if defined(__MD93__)
kal_uint8 type;
kal_uint16 msg;
#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
kal_uint32 type:4;
kal_uint32 elen:3;
kal_uint32 sub_type:6;
kal_uint32 msg2:10;
kal_uint32 msg1;
#endif
} IDC_ILM_MSG_T;
typedef enum
{
IDC_OPEN,
IDC_IN_USE,
IDC_IN_SLEEP,
IDC_SUSPEND,
IDC_CLOSED
} IDC_MAIN_STATE_T;
typedef enum
{
IDC_PLAN,
IDC_RUN
} IDC_SCHEDULE_STATE_T;
#endif