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192.168.1.100 / T800_MD / 0b80c7188a6089ae59f523c5d460adad05960e1d / . / mcu / interface / driver / hwdrv / sccb_v2.h_
blob: 53481b80b6cb68c50ae77219ae751cbddbf226d6 [file] [log] [blame]
/*****************************************************************************
* Copyright Statement:
* --------------------
* This software is protected by Copyright and the information contained
* herein is confidential. The software may not be copied and the information
* contained herein may not be used or disclosed except with the written
* permission of MediaTek Inc. (C) 2005
*
* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/
/*****************************************************************************
*
* Filename:
* ---------
* sccb_v2.h
*
*
* Description:
* ------------
* SCCB/I2C V2 Driver
*
* Author:
* -------
* Scott Hung (mtk01235)
*
*============================================================================
* HISTORY
* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*------------------------------------------------------------------------------
* $Revision: $
* $Modtime: $
* $Log: $
*
* 04 24 2012 wcpuser_integrator
* [MAUI_03155806] [MSBB2] Global Revise Clear and Uniform Legacy Header File Inclusion Requested by JI Huang
* .
*
* 11 30 2010 guoxin.hong
* [MAUI_02841708] [Drv] MAUI HAL Peripheral Create
* .
*
* 11 23 2010 shuang.han
* [MAUI_02840976] [HAL][Drv] driver feature option files merge back to MAUI
* .
*
* 10 18 2010 shuang.han
* [MAUI_02637814] [RHR][MAUIW1038OF_RHR] Integration to W10.43
* .
*
* May 19 2010 mtk01845
* [MAUI_02529366] [Drv] I2C patch for MT6236 sanity failed
*
*
* May 15 2010 mtk02787
* [MAUI_02524954] I2C "write then read" fail
*
*
* May 6 2010 mtk02787
* [MAUI_02416501] add function definition in sccb_v2.h to avoid build warning
*
*
* Apr 15 2010 mtk02787
* [MAUI_02397396] I2C V1 phase out
*
*
* Apr 14 2010 mtk02787
* [MAUI_02392155] [MEUT] Check in driver on/off function to Maui
*
*
* Mar 31 2010 mtk02787
* [MAUI_02385929] I2C DMA mode
*
*
* Feb 22 2010 mtk01845
* [MAUI_02360180] [Drv][I2C] I2C driver revision for new DMA architecture from MT6276
*
*
* Feb 20 2010 mtk01845
* [MAUI_02360180] [Drv][I2C] I2C driver revision for new DMA architecture from MT6276
*
*
* Oct 12 2009 mtk01845
* [MAUI_01963866] [Drv][I2C] sccb.h define I2C pins
*
*
* May 9 2009 mtk01845
* [MAUI_01319629] [Drv] MEUT check in
*
*
* Jan 12 2009 mtk01845
* [MAUI_01307296] MT6235 charger constant current CC6 and CC7 change to internal use
*
*
* Nov 6 2008 mtk01845
* [MAUI_01269587] [Drv] MT6253T merge back to MAUI
*
*
* Jun 21 2008 mtk01845
* [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
*
*
* Jun 20 2008 mtk01845
* [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
*
*
* Apr 22 2008 mtk01845
* [MAUI_00760971] [Drv][MoDIS] Add driver API functions into MoDIS dummy driver
*
*
* Nov 9 2007 mtk01283
* [MAUI_00573819] [Drv][Compile option] Check in MT6235 compile option to Maui
*
*
* Aug 6 2007 mtk01283
* [MAUI_00529681] [Drv] Remove compile warning in driver codes
*
*
* Mar 19 2007 mtk01235
* [MAUI_00359681] [Drv][Compile Option] Add MT6223 and MT6223P compile option
*
*
* Jan 30 2007 MTK01235
* [MAUI_00363041] [Drv]Driver Feature Management
*
*
* Nov 20 2006 MTK01235
* [MAUI_00338437] [I2C] Check in I2C/SCCB V2 driver
*
*
* Oct 25 2006 mtk01235
* [MAUI_00338437] [I2C] Check in I2C/SCCB V2 driver
*
*------------------------------------------------------------------------------
* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
*============================================================================
*****************************************************************************/
#ifndef __SCCB_V2_H__
#define __SCCB_V2_H__
#include "drv_features_i2c.h"
#if (defined(DRV_I2C_25_SERIES))
//#if (defined(MT6225))
#include "sccb.h"
#include "intrCtrl.h"
#include "drv_comm.h"
#include "sccb_v2_custom.h"
#define SCCB_OWNER_HEADER_FILE_INCLUDED
//MSBB remove #include "kal_non_specific_general_types.h"
#include "reg_base.h"
#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
#define DRV_I2C_ClearBits16(addr, data) DRV_ClearBits(addr,data)
#define DRV_I2C_SetBits16(addr, data) DRV_SetBits(addr,data)
#define DRV_I2C_WriteReg16(addr, data) DRV_WriteReg(addr, data)
#define DRV_I2C_ReadReg16(addr) DRV_Reg(addr)
#define DRV_I2C_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
#define DRV_I2C_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
#define DRV_I2C_SetBits16(addr) DRV_DBG_SetBits(addr)
#define DRV_I2C_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
#define DRV_I2C_ReadReg16(addr) DRV_DBG_Reg(addr)
#define DRV_I2C_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
#define I2C_MODULE_FIFO_DEPTH 8
#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8 // SCCB backward compatible
#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
#define SCCB_CLOCK_RATE 15360 //15.36MHz
#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
#define SCCB_CLOCK_RATE 3000 //3.0MHz
#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
#define SCCB_CLOCK_RATE 13000 //13MHz
#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
#if defined(__MEUT__)
#define I2C_V2_DVT
#endif // #if defined(__MEUT__)
#ifdef I2C_V2_DVT
#if !defined(DRV_I2C_DMA_ENABLED)
#define DRV_I2C_DMA_ENABLED //Only used in DVT
#endif // #if !defined(DRV_I2C_DMA_ENABLED)
#endif // #ifdef I2C_V2_DVT
#if (defined(DRV_I2C_DMA_ENABLED))
#include "dma_hw.h"
#endif // #if (defined(DRV_I2C_DMA_ENABLED))
// Some common structures are defined in sccb.h
typedef enum
{
SCCB_TRANSACTION_COMPLETE,
SCCB_TRANSACTION_FAIL
}SCCB_TRANSACTION_RESULT;
typedef enum
{
SCCB_READY_STATE,
SCCB_BUSY_STATE
}SCCB_STATE;
/* Transaction mode for new SCCB APIs */
typedef enum
{
SCCB_TRANSACTION_FAST_MODE,
SCCB_TRANSACTION_HIGH_SPEED_MODE
}SCCB_TRANSACTION_MODE;
typedef enum
{
#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
// Module source clock is 15.36Mhz
SCCB_100KB, //99.74KB
SCCB_200KB, //196.9KB
SCCB_300KB, //295.4KB
SCCB_400KB, //384.0KB
/* HS Mode */
SCCB_960KB, //960.0KB
SCCB_1280KB, //1280.0KB
SCCB_1536KB, //1536.0KB
SCCB_1920KB, //1920.0KB
SCCB_2560KB, //2560.0KB
SCCB_3840KB //3840.0KB
#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
// Module source clock is 3.0Mhz
SCCB_100KB, //100.0KB
SCCB_200KB, //196.9KB
SCCB_400KB, //384.0KB
/* HS Mode */
SCCB_750KB, //750.0KB
SCCB_1500KB //1500.0KB
#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
// Module source clock is 13Mhz
SCCB_100KB, //101.5KB
SCCB_200KB, //203.1KB
SCCB_300KB, //295.5KB
SCCB_400KB, //382.4KB
/* HS Mode */
SCCB_460KB, //464.3KB
SCCB_540KB, //541.7KB
SCCB_650KB, //650.0KB
SCCB_720KB, //722.0KB
SCCB_810KB, //812.5KB
SCCB_930KB, //928.6KB
SCCB_1100KB, //1083.3KB
SCCB_1300KB, //1300.0KB
SCCB_1625KB, //1625.0KB
SCCB_2150KB, //2166.6KB
SCCB_3250KB //3250.6KB
#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
}SCCB_SPEED_ENUM;
typedef struct
{
kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
kal_bool get_handle_wait; //When get handle wait until the sccb is avaliable
kal_uint8 slave_address; //the address of the slave device
kal_uint8 delay_len; //number of half pulse between transfers in a trasaction
SCCB_TRANSACTION_MODE transaction_mode; //SCCB_TRANSACTION_FAST_MODE or SCCB_TRANSACTION_HIGH_SPEED_MODE
kal_uint32 Fast_Mode_Speed; //The speed of sccb fast mode(Kb)
kal_uint32 HS_Mode_Speed; //The speed of sccb high speed mode(Kb)
#if (defined(DRV_I2C_DMA_ENABLED))
kal_bool is_DMA_enabled; //Transaction via DMA instead of 8-byte FIFO
#endif // #if (defined(DRV_I2C_DMA_ENABLED))
}sccb_config_struct;
typedef struct
{
sccb_config_struct sccb_config;
kal_uint8 fs_sample_cnt_div; //these two parameters are used to specify sccb clock rate
kal_uint8 fs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
kal_uint8 hs_sample_cnt_div; //these two parameters are used to specify sccb clock rate
kal_uint8 hs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
SCCB_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
(SCCB_TRANSACTION_COMPLETE|SCCB_TRANSACTION_FAIL) */
}sccb_handle_struct;
typedef struct
{
volatile SCCB_STATE state;
kal_uint8 owner;
kal_uint8 number_of_read;
kal_uint8* read_buffer;
#if (defined(DRV_I2C_DMA_ENABLED))
kal_bool is_DMA_enabled;
#endif // #if (defined(DRV_I2C_DMA_ENABLED))
}sccb_status_struct;
#if defined(__SUPPORT_SCCB_XXX_API__)
#if(defined(DRV_GPIO_6223_SERIES))
// Need to check the history
// When platform is 6223, without __CUST_NEW__
// The SCL and SDA in sccb.h is 15, 19
// In spec, the SCL, SDA is 45, 46
#if defined(SCCB_SERIAL_CLK_PIN)
// It means someone include sccb_v2.h
// Driver should use the SCL, SDA defined in sccb_v2.h
#undef SCCB_SERIAL_CLK_PIN
#undef SCCB_SERIAL_DATA_PIN
#undef SCCB_GPIO_SCL_MODE
#undef SCCB_GPIO_SDA_MODE
#endif // #if defined(SCCB_SERIAL_CLK_PIN)
#define SCCB_SERIAL_CLK_PIN 45
#define SCCB_SERIAL_DATA_PIN 46
#define SCCB_GPIO_SCL_MODE 3
#define SCCB_GPIO_SDA_MODE 3
#endif // #if(defined(DRV_GPIO_6223_SERIES))
#endif // #if defined(__SUPPORT_SCCB_XXX_API__)
#ifndef DRV_I2C_OFF
/* Register Definitions */
#define REG_I2C_DATA_PORT (I2C_base + 0x00)
#define REG_I2C_SLAVE_ADDR (I2C_base + 0x04)
#define REG_I2C_INT_MASK (I2C_base + 0x08)
#define REG_I2C_INT_STA (I2C_base + 0x0c)
#define REG_I2C_CONTROL (I2C_base + 0x10)
#define REG_I2C_TRANSFER_LEN (I2C_base + 0x14)
#define REG_I2C_TRANSAC_LEN (I2C_base + 0x18)
#define REG_I2C_DELAY_LEN (I2C_base + 0x1c)
#define REG_I2C_TIMING (I2C_base + 0x20)
#define REG_I2C_START (I2C_base + 0x24)
#define REG_I2C_FIFO_STAT (I2C_base + 0x30)
#define REG_I2C_FIFO_THRESH (I2C_base + 0x34)
#define REG_I2C_FIFO_ADDR_CLR (I2C_base + 0x38)
#define REG_I2C_IO_CONFIG (I2C_base + 0x40)
#define REG_I2C_MULTI_MASTER (I2C_base + 0x44)
#define REG_I2C_HS_MODE (I2C_base + 0x48)
#define REG_I2C_SOFTRESET (I2C_base + 0x50)
#endif // DRV_I2C_OFF
/* Register masks */
#define I2C_1_BIT_MASK 0x01
#define I2C_3_BIT_MASK 0x07
#define I2C_4_BIT_MASK 0x0f
#define I2C_6_BIT_MASK 0x3f
#define I2C_8_BIT_MASK 0xff
#define I2C_RX_FIFO_THRESH_MASK 0x0007
#define I2C_RX_FIFO_THRESH_SHIFT 0
#define I2C_TX_FIFO_THRESH_MASK 0x0700
#define I2C_TX_FIFO_THRESH_SHIFT 8
#define I2C_AUX_LEN_MASK 0x1f00
#define I2C_AUX_LEN_SHIFT 8
#define I2C_SAMPLE_CNT_DIV_MASK 0x0700
#define I2C_SAMPLE_CNT_DIV_SHIFT 8
#define I2C_DATA_READ_TIME_MASK 0x7000
#define I2C_DATA_READ_TIME_SHIFT 12
#define I2C_MASTER_READ 0x01
#define I2C_MASTER_WRITE 0x00
//#define I2C_CTL_MODE_BIT 0x01
#define I2C_CTL_RS_STOP_BIT 0x02
#define I2C_CTL_DMA_EN_BIT 0x04
#define I2C_CTL_CLK_EXT_EN_BIT 0x08
#define I2C_CTL_DIR_CHANGE_BIT 0x10
#define I2C_CTL_ACK_ERR_DET_BIT 0x20
#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
#define I2C_DATA_READ_ADJ_BIT 0x8000
#define I2C_SCL_MODE_BIT 0x01
#define I2C_SDA_MODE_BIT 0x02
#define I2C_BUS_DETECT_EN_BIT 0x04
#define I2C_ARBITRATION_BIT 0x01
#define I2C_CLOCK_SYNC_BIT 0x02
#define I2C_BUS_BUSY_DET_BIT 0x04
#define I2C_HS_EN_BIT 0x01
#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
#define I2C_HS_MASTER_CODE_MASK 0x0070
#define I2C_HS_MASTER_CODE_SHIFT 4
#define I2C_HS_STEP_CNT_DIV_MASK 0x0700
#define I2C_HS_STEP_CNT_DIV_SHIFT 8
#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
#define I2C_HS_SAMPLE_CNT_DIV_SHIFT 12
/* I2C Status */
#define I2C_FIFO_FULL_STATUS 0x01
#define I2C_FIFO_EMPTY_STATUS 0x02
/* Register Settings */
#define SET_I2C_SLAVE_ADDRESS(n,rw) do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0);
#define DISABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0);
#define ENABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0);
#define CLEAR_I2C_STA do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0);
//#define SET_I2C_FAST_SPEED_MODE REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
//#define SET_I2C_HIGH_SPEED_MODE REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
#define SET_I2C_ST_BETWEEN_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
#define SET_I2C_RS_BETWEEN_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
#define ENABLE_I2C_DMA_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
#define ENABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
#define ENABLE_I2C_DIR_CHANGE do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
#define ENABLE_I2C_ACK_ERR_DET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
#define ENABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
#define DISABLE_I2C_DMA_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
#define DISABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
#define DISABLE_I2C_DIR_CHANGE do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
#define DISABLE_I2C_ACK_ERR_DET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
#define DISABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0);
#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0);
#define SET_I2C_TRANSACTION_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0);
#define SET_I2C_DELAY_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0);
#define SET_I2C_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0);
#define SET_I2C_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0);
#define SET_I2C_DATA_READ_TIME(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0);
#define ENABLE_I2C_DATA_READ_ADJ do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
#define DISABLE_I2C_DATA_READ_ADJ do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
#define START_I2C_TRANSACTION do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0);
// #define I2C_FIFO_FULL ((REG_I2C_FIFO_STAT>>1)&0x01)
// #define I2C_FIFO_EMPTY (REG_I2C_FIFO_STAT & 0x01)
#define SET_I2C_RX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0);
#define SET_I2C_TX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0);
#define CLEAR_I2C_FIFO do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0);
#define SET_I2C_SCL_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
#define SET_I2C_SCL_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
#define SET_I2C_SDA_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
#define SET_I2C_SDA_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
#define ENABLE_I2C_BUS_DETECT do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
#define DISABLE_I2C_BUS_DETECT do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
#define ENABLE_I2C_CLOCK_SYNC do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
#define ENABLE_DATA_ARBITION do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
#define ENABLE_I2C_BUS_BUSY_DET do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
#define DISABLE_I2C_CLOCK_SYNC do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
#define DISABLE_DATA_ARBITION do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
#define DISABLE_I2C_BUS_BUSY_DET do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
#define SET_I2C_HIGH_SPEED_MODE_800KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0);
#define SET_I2C_HIGH_SPEED_MODE_1000KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0);
#define SET_I2C_FAST_MODE do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
#define SET_I2C_HS_MODE do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
#define ENABLE_I2C_NAKERR_DET do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
#define DISABLE_I2C_NAKERR_DET do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
#define SET_I2C_HS_MASTER_CODE(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0);
#define SET_I2C_HS_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0);
#define SET_I2C_HS_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0);
#define RESET_I2C do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0);
//---------------- DMA ----------------
#if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
//#define DMA_base 0x80030000 -->defined in /inc/reg_base.h
/* Regidter Definitions */
#define REG_DMA_CHANNEL_CONTROL(c) *((volatile unsigned int *) (DMA_base + 0x14+ (c<<8)))
#define REG_DMA_CHANNEL_START(c) *((volatile unsigned int *) (DMA_base + 0x18+ (c<<8)))
#define REG_DMA_PROG_ADDR(c) *((volatile unsigned int *) (DMA_base + 0x2c+ (c<<8)))
#define REG_DMA_TRANSFER_COUNT(c) *((volatile unsigned int *) (DMA_base + 0x10+ (c<<8)))
/* Master Definitions*/
#define DMA_MASTER_I2C_TX DMA_CON_MASTER_I2CTX
#define DMA_MASTER_I2C_RX DMA_CON_MASTER_I2CRX
#define DMA_MASTER_IRDA_TX 0x02
#define DMA_MASTER_IRDA_RX 0x03
#define DMA_I2C_TX_CHANNEL 4
#define DMA_I2C_RX_CHANNEL 5
/* Register masks */
#define DMA_CON_DIR_MASK 0x40000
#define DMA_CON_MAS_MASK 0x01f00000
#define I2C_SET_TX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00000014;\
REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
#define I2C_SET_RX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00040018;\
REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
#define I2C_SET_DMA_PROGRAMMABLE_ADDR(c,addr) REG_DMA_PROG_ADDR(c) = (addr);
#define I2C_SET_DMA_TRANSFER_COUNT(c,size) REG_DMA_TRANSFER_COUNT(c)= size ;
#define I2C_START_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0x8000;
#define I2C_STOP_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0;
#endif // #if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
/****** SW definitions******/
#define I2C_READ_BIT 0x01
#define I2C_WRITE_BIT 0x00
#define I2C_TRANSAC_COMPLETE 0x01
#define I2C_TRANSAC_ACK_ERR 0x02
#define I2C_HS_NACK_ERR 0x04
void i2c_init(void);
void i2c_set_transaction_speed(SCCB_OWNER owner,SCCB_TRANSACTION_MODE mode,kal_uint32* Fast_Mode_Speed,kal_uint32* HS_Mode_Speed);
void i2c_config(SCCB_OWNER owner,sccb_config_struct* para);
void i2c_set_slave_address(SCCB_OWNER owner,kal_uint8 slave_address);
void i2c_set_get_handle_wait(SCCB_OWNER owner,kal_bool enable);
SCCB_TRANSACTION_MODE i2c_get_transaction_mode(SCCB_OWNER owner);
SCCB_TRANSACTION_RESULT i2c_write(SCCB_OWNER owner,kal_uint8* para,kal_uint32 datalen);
SCCB_TRANSACTION_RESULT i2c_read(SCCB_OWNER owner,kal_uint8* para,kal_uint32 datalen);
SCCB_TRANSACTION_RESULT i2c_cont_write(SCCB_OWNER owner, kal_uint8* para, kal_uint32 datalen_in_transfer, kal_uint32 transfer_num);
SCCB_TRANSACTION_RESULT i2c_cont_read(SCCB_OWNER owner, kal_uint8* para, kal_uint32 datalen_in_transfer, kal_uint32 transfer_num);
SCCB_TRANSACTION_RESULT i2c_write_and_read(SCCB_OWNER owner, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len);
#if (defined(DRV_I2C_DMA_ENABLED))
void i2c_set_DMA(SCCB_OWNER owner, kal_bool enable);
#endif // #if (defined(DRV_I2C_DMA_ENABLED))
#if defined(DRV_I2C_25_SERIES)
#if defined(__SUPPORT_SCCB_XXX_API__)
void sccb_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 param);
void sccb_multi_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 *param, kal_uint8 num);
void sccb_cont_write(SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 spec_cmd, kal_uint32 param);
kal_uint32 sccb_read (SCCB_OWNER owner,kal_uint32 cmd);
kal_uint32 sccb_phase3_read (SCCB_OWNER owner,kal_uint32 cmd);
kal_uint32 sccb_cont_read (SCCB_OWNER owner,kal_uint32 cmd, kal_uint32 spec_cmd);
kal_uint8 sccb_multi_read (SCCB_OWNER owner, kal_uint32 cmd, kal_uint32 *param, kal_uint8 num);
#endif // #if defined(__SUPPORT_SCCB_XXX_API__)
#endif // #if defined(DRV_I2C_25_SERIES)
#endif // #if (defined(DRV_I2C_25_SERIES))
#endif // #ifndef __SCCB_V2_H__