| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /******************************************************************************* |
| * |
| * Filename: |
| * --------- |
| * RM_public.h |
| * |
| * Project: |
| * -------- |
| * MT6280 |
| * |
| * Description: |
| * ------------ |
| * Resource Management configuration |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| *------------------------------------------------------------------------------ |
| * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| |
| #ifndef RM_PUBLIC_H |
| #define RM_PUBLIC_H |
| |
| #include "kal_general_types.h" |
| #include "sleepdrv_common.h" |
| #include "l1_rm_public.h" /* for modem related definition move to l1sm_public.h */ |
| |
| |
| typedef enum |
| { |
| /* Resource on MCU RM */ |
| //RM_MCU_BASE = 0, |
| /* Resource on MODEM RM */ |
| MODEM_SLV_START = 0, |
| RM_MD2G_SPEECH = 0, |
| RM_C2K_TRIGGER = 4, |
| RM_LTE_CS = 5, |
| RM_FDD_TD = 6,/* talking & datalink */ |
| RM_FDD_DL = 7, /* datalink */ |
| MODEM_SLV_END = 7, |
| MODEM_DBG_START = 8, |
| RM_TDD_TD = 11, |
| RM_TDD_DL = 12, |
| MODEM_DBG_END = 12, |
| NUMBER_OF_RESOURCE, |
| /*Move original declared into RM_Module. */ |
| RM_MODEM_BASE = 20, |
| RM_MODEM_DSP_1, |
| RM_MODEM_DSP_2, |
| RM_MODEM_L2_COPRO, |
| NUMBER_OF_RM_MODEM |
| } RM_Module; |
| |
| typedef enum |
| { |
| #if defined(__MD93__) |
| CORE0_PWR = 0, |
| CORE1_PWR = 1, |
| USIP0_PWR = 2, |
| USIP1_PWR = 3, |
| MML2_PWR = 4, |
| MDCORE_PWR = 5, |
| MDINFRA_PWR = 6, |
| CM2_PWR = 7, |
| MAX_PWR = 8, |
| #elif defined(__MD95__) |
| CORE0_PWR = 0, |
| CORE1_PWR = 1, |
| CORE2_PWR = 2, |
| USIP0_PWR = 3, |
| MDCORE_PWR = 4, |
| CM2_PWR = 5, |
| MML2_PWR = 6, |
| MAX_PWR = 7, |
| #elif defined(__MD97__) || defined(__MD97P__) |
| CORE0_PWR = 0, |
| CORE1_PWR = 1, |
| CORE2_PWR = 2, |
| CORE3_PWR = 3, |
| USIP0_PWR = 4, |
| MDCORE_PWR = 5, |
| MML2_PWR = 6, |
| CM2_PWR = 11, |
| MAX_PWR = 12, |
| #else |
| #error "no chip match" |
| #endif |
| } MDTOPSM_Power_Domain; |
| |
| typedef enum |
| { |
| L1_COMMRES = 0, |
| EMI = 1, |
| MAX_CT = 2, |
| } MDTOPSM_Cross_Trigger; |
| |
| //#endif |
| |
| void RM_Init( void ); |
| extern void MD_TOPSM_PWR_SW_Control(MDTOPSM_Power_Domain pwr_dom, kal_bool enable); |
| extern void MD_TOPSM_CT_SW_Control(MDTOPSM_Cross_Trigger CT, kal_bool enable); |
| extern void MD_TOPSM_DDR_SW_Control(kal_bool enable); |
| extern void MD_TOPSM_Init_Other_Cores(void); |
| extern void MD_TOPSM_SibAttach(void); |
| extern kal_bool MD_TOPSM_Is_USIP_ForcedOn(void); |
| extern kal_bool MD_TOPSM_Is_Pwr_Domain_Off_to_On(MDTOPSM_Power_Domain pwr_dom); |
| extern void MD_TOPSM_PWR_SW_Control_CM2(kal_bool enable); |
| extern void MD_TOPSM_PWR_SW_Control_MDCORE(kal_bool enable); |
| extern kal_bool MD_TOPSM_Is_Pwr_Domain_on(MDTOPSM_Power_Domain pwr_dom); |
| extern kal_bool MD_TOPSM_GetCsysReqSta(void); |
| extern kal_bool MD_TOPSM_IsMDInfraPowerOn(void); |
| extern kal_bool MD_TOPSM_IsUsipPowerOn(void); |
| extern kal_uint32 MD_TOPSM_Get_F32K_Cnt(void); |
| /* Should remove later */ |
| extern kal_uint32 MD_TOPSM_PollingTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer); |
| extern kal_uint32 MD_TOPSM_GetSync26M(MODEM_TOPSM_TIMER_MODULE timer); |
| extern void MD_TOPSM_ClearTimingSyncSta(MODEM_TOPSM_TIMER_MODULE timer); |
| extern void MD_TOPSM_SetGPSSyncCon0(kal_uint32 value); |
| extern void MD_TOPSM_SetGPSSyncCon1(kal_uint32 value); |
| extern kal_bool MD_TOPSM_GetErrorStatus(void); |
| #endif /* !RM_PUBLIC_H */ |