| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /******************************************************************************* |
| * |
| * Filename: |
| * --------- |
| * ostd_public.h |
| * |
| * Project: |
| * -------- |
| * MTK6276 |
| * |
| * Description: |
| * ------------ |
| * This is the driver layer and corresponding Sleep Mode of ARM OS Timer HW |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *------------------------------------------------------------------------------ |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| * removed! |
| * removed! |
| * |
| * removed! |
| *------------------------------------------------------------------------------ |
| * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| #if 1 |
| |
| #ifndef OSTD_PUBLIC_H |
| #define OSTD_PUBLIC_H |
| |
| #include "kal_general_types.h" |
| #ifndef L1_SIM |
| #include "ps_public_enum.h" |
| #endif |
| |
| typedef void (*AP_STATUS_CHAGE_CALLBACK) (kal_uint32 ap_status); |
| |
| typedef enum |
| { |
| OSTD_SUCCESS_FALSE = 0, /*OSTD read back AFN/UFN and found that current value is <=2*/ |
| OSTD_SUCCESS_TRUE, /*OSTD has successfully set the AFN value into ARM OS Timer HW*/ |
| OSTD_TIME_OUT, /*OSTD failed to poll ready bit*/ |
| OSTD_FAIL, /* Other unknown fail reason */ |
| OSTD_RESULT_NUM |
| } OSTD_RESULT_E; |
| |
| typedef struct _OSTD_FRM_INFO_T |
| { |
| kal_uint32 curr_afn; /* for OSTD to fill back current AFN value */ |
| kal_uint32 curr_ufn; /* for OSTD to fill back current UFN value */ |
| kal_uint32 curr_afn_dly; /* for OSTD to fill back current AFN_DLY value */ |
| } OSTD_FRM_INFO_T; |
| |
| typedef struct |
| { |
| char* module_name; |
| module_type mod_id; |
| AP_STATUS_CHAGE_CALLBACK funp; |
| kal_bool pending_urc; |
| } ostd_urc_src_module_info_struct; |
| |
| typedef enum _OSTD_TIMER_TYPE_E |
| { |
| OSTD_OST, |
| OSTD_2G, |
| OSTD_3G_FDD, |
| OSTD_3G_TDD, |
| OSTD_3G_C2K_1X, |
| OSTD_3G_C2K_DO, |
| OSTD_4G, |
| OSTD_5G, |
| OSTD_TIMER_MAX |
| } OSTD_TIMER_TYPE_E; |
| |
| typedef enum { |
| OSTD_BUSY, |
| OSTD_WAIT, |
| OSTD_DORMANT |
| } kal_checksleep_e; |
| |
| typedef enum { |
| OSTD_ChkSlp_No_InfiniteSleep, |
| OSTD_ChkSlp_EFUN_CFUN, |
| OSTD_ChkSlp_EPOF |
| } kal_chkslp_inf_e; |
| |
| typedef enum { |
| OSTD_IDLE_VPE0_ENTER, |
| OSTD_IDLE_VPE0_LEAVE, |
| OSTD_IDLE_VPE1_ENTER, |
| OSTD_IDLE_VPE1_LEAVE, |
| OSTD_IDLE_CALCULATE, |
| OSTD_IDLE_PRINT |
| } kal_idlerate_e; |
| |
| #if defined(__MD97__) |
| #if defined(CHIP10992) |
| typedef enum |
| { |
| EVENT_l1sm_timer_trig_F32K = 0, |
| EVENT_mdsm_timer_trig_F32K = 1, |
| EVENT_dem_trig_md_int_le_F32K = 2, |
| EVENT_fe_md_share_d12mint1_b_F32K = 3, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4, |
| EVENT_mcu_bus_decerr_irq_F32K = 5, |
| EVENT_usip_ia_ostimer_wakeup_b_F32K = 6, |
| EVENT_cs_nr_irq_F32K = 7, |
| EVENT_cs_err_irq_F32K = 8, |
| EVENT_ulsp_log_md_rt_int_F32K = 9, |
| EVENT_ulsp_log_md_od_int_F32K = 10, |
| EVENT_ulsp_log_dsp4g_rt_int_F32K = 11, |
| EVENT_ulsp_log_dsp4g_od_int_F32K = 12, |
| EVENT_ulsp_log_dsp5g_rt_int_F32K = 13, |
| EVENT_ulsp_log_dsp5g_od_int_F32K = 14, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 17, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 18, |
| EVENT_mml1_dspcsif_top_err_cirq_F32K = 19, |
| EVENT_ap2md_usb_rx_not_empty_F32K = 20, |
| EVENT_ap2md_usb_rx_gpd_done_F32K = 21, |
| EVENT_ap2md_usb_dma_active_F32K = 22, |
| EVENT_ap2md_usb_ip_wakeup_F32K = 23, |
| EVENT_ap2md_usb_mcu_irq_b_F32K = 24, |
| EVENT_ap2md_ssusb_rx_not_empty_F32K = 25, |
| EVENT_ap2md_ssusb_rx_gpd_done_F32K = 26, |
| EVENT_ap2md_ssusb_dma_active_F32K = 27, |
| EVENT_ap2md_ssusb_ip_wakeup_F32K = 28, |
| EVENT_ap2md_ssusb_dev_int_b_F32K = 29, |
| EVENT_ap2md_ccif0_md_event_b_F32K = 30, |
| EVENT_ap2md_ccif1_md_event_b_F32K = 31, |
| EVENT_ap2md_cldma_ip_busy_F32K = 32, |
| EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 33, |
| EVENT_conn2md_pdma_irq_b_F32K = 34, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 35, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 36, |
| EVENT_ipsec_so_int_lv_F32K = 37, |
| EVENT_conn_bt_cvsd_int_b_F32K = 38, |
| EVENT_conn_bt_isoch_irq_b_F32K = 39, |
| EVENT_rgu2md_irq_b_F32K = 40, |
| EVENT_ap2md_ccif2_md_event_b_F32K = 41, |
| EVENT_mhccif_sap2md_event_b_F32K = 42, |
| EVENT_ap2md_apmcu_suspend_irq_F32K = 43, |
| EVENT_ap2md_apmcu_active_irq_F32K = 44, |
| EVENT_eint_event0_F32K = 45, |
| EVENT_eint_event1_F32K = 46, |
| EVENT_eint_event2_F32K = 47, |
| EVENT_eint_event3_F32K = 48, |
| EVENT_eint_event4_F32K = 49, |
| EVENT_eint_event5_F32K = 50, |
| EVENT_eint_event6_F32K = 51, |
| EVENT_eint_event7_F32K = 52, |
| EVENT_eint_event8_F32K = 53, |
| EVENT_eint_event9_F32K = 54, |
| EVENT_eint_event10_F32K = 55, |
| EVENT_eint_event11_F32K = 56, |
| EVENT_ap2md_cldma0_md_ip_busy_lv_md_F32K = 57, |
| EVENT_ap2md_cldma1_md_ip_busy_lv_md_F32K = 58, |
| EVENT_ap2md_cldma2_md_ip_busy_lv_md_F32K = 59, |
| EVENT_ap2md_cldma3_md_ip_busy_lv_md_F32K = 60, |
| EVENT_pcie_interrupt_out_F32K = 61, |
| |
| EVENT_l1sm_timer_trig_NON_F32K = 64, |
| EVENT_mdsm_timer_trig_NON_F32K = 65, |
| EVENT_dem_trig_md_int_le_NON_F32K = 66, |
| EVENT_fe_md_share_d12mint1_b_NON_F32K = 67, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68, |
| EVENT_mcu_bus_decerr_irq_NON_F32K = 69, |
| EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70, |
| EVENT_cs_nr_irq_NON_F32K, |
| EVENT_cs_err_irq_NON_F32K, |
| EVENT_ulsp_log_md_rt_int_NON_F32K = 73, |
| EVENT_ulsp_log_md_od_int_NON_F32K = 74, |
| EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75, |
| EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76, |
| EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77, |
| EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K = 81, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K = 82, |
| EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 83, |
| EVENT_ap2md_usb_rx_not_empty_NON_F32K = 84, |
| EVENT_ap2md_usb_rx_gpd_done_NON_F32K = 85, |
| EVENT_ap2md_usb_dma_active_NON_F32K = 86, |
| EVENT_ap2md_usb_ip_wakeup_NON_F32K = 87, |
| EVENT_ap2md_usb_mcu_irq_b_NON_F32K = 88, |
| EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 89, |
| EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K = 90, |
| EVENT_ap2md_ssusb_dma_active_NON_F32K = 91, |
| EVENT_ap2md_ssusb_ip_wakeup_NON_F32K = 92, |
| EVENT_ap2md_ssusb_dev_int_b_NON_F32K = 93, |
| EVENT_ap2md_ccif0_md_event_b_NON_F32K = 94, |
| EVENT_ap2md_ccif1_md_event_b_NON_F32K = 95, |
| EVENT_ap2md_cldma_ip_busy_NON_F32K = 96, |
| EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 97, |
| EVENT_conn2md_pdma_irq_b_NON_F32K = 98, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 99, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 100, |
| EVENT_ipsec_so_int_lv_NON_F32K = 101, |
| EVENT_conn_bt_cvsd_int_b_NON_F32K = 102, |
| EVENT_conn_bt_isoch_irq_b_NON_F32K = 103, |
| EVENT_rgu2md_irq_b_NON_F32K = 104, |
| EVENT_ap2md_ccif2_md_event_b_NON_F32K = 105, |
| EVENT_mhccif_sap2md_event_b_NON_F32K = 106, |
| EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 107, |
| EVENT_ap2md_apmcu_active_irq_NON_F32K = 108, |
| EVENT_eint_event0_NON_F32K = 109, |
| EVENT_eint_event1_NON_F32K = 110, |
| EVENT_eint_event2_NON_F32K = 111, |
| EVENT_eint_event3_NON_F32K = 112, |
| EVENT_eint_event4_NON_F32K = 113, |
| EVENT_eint_event5_NON_F32K = 114, |
| EVENT_eint_event6_NON_F32K = 115, |
| EVENT_eint_event7_NON_F32K = 116, |
| EVENT_eint_event8_NON_F32K = 117, |
| EVENT_eint_event9_NON_F32K = 118, |
| EVENT_eint_event10_NON_F32K = 119, |
| EVENT_eint_event11_NON_F32K = 120, |
| EVENT_ap2md_cldma0_md_ip_busy_lv_md_NON_F32K = 121, |
| EVENT_ap2md_cldma1_md_ip_busy_lv_md_NON_F32K = 122, |
| EVENT_ap2md_cldma2_md_ip_busy_lv_md_NON_F32K = 123, |
| EVENT_ap2md_cldma3_md_ip_busy_lv_md_NON_F32K = 124, |
| EVENT_pcie_interrupt_out_NON_F32K = 125, |
| } sm_event_e; |
| #elif defined(MT6885) |
| typedef enum |
| { |
| EVENT_l1sm_timer_trig_F32K = 0, |
| EVENT_mdsm_timer_trig_F32K = 1, |
| EVENT_dem_trig_md_int_le_F32K = 2, |
| EVENT_fe_md_share_d12mint1_b_F32K = 3, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4, |
| EVENT_mcu_bus_decerr_irq_F32K = 5, |
| EVENT_usip_ia_ostimer_wakeup_b_F32K = 6, |
| EVENT_cs_nr_irq_F32K, |
| EVENT_cs_err_irq_F32K, |
| EVENT_ulsp_log_md_rt_int_F32K = 9, |
| EVENT_ulsp_log_md_od_int_F32K = 10, |
| EVENT_ulsp_log_dsp4g_rt_int_F32K = 11, |
| EVENT_ulsp_log_dsp4g_od_int_F32K = 12, |
| EVENT_ulsp_log_dsp5g_rt_int_F32K = 13, |
| EVENT_ulsp_log_dsp5g_od_int_F32K = 14, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16, |
| EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19, |
| EVENT_mml1_dspcsif_top_err_cirq_F32K = 20, |
| EVENT_ap2md_usb_rx_not_empty_F32K, |
| EVENT_ap2md_usb_rx_gpd_done_F32K = 22, |
| EVENT_ap2md_usb_dma_active_F32K, |
| EVENT_ap2md_usb_ip_wakeup_F32K = 24, |
| EVENT_ap2md_usb_mcu_irq_b_F32K =25, |
| EVENT_ap2md_ssusb_rx_not_empty_F32K, |
| EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27, |
| EVENT_ap2md_ssusb_dma_active_F32K, |
| EVENT_ap2md_ssusb_ip_wakeup_F32K = 29, |
| EVENT_ap2md_ssusb_dev_int_b_F32K = 30, |
| EVENT_ap2md_ccif0_md_event_b_F32K = 31, |
| EVENT_ap2md_ccif1_md_event_b_F32K = 32, |
| EVENT_ap2md_cldma_ip_busy_F32K = 33, |
| EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34, |
| EVENT_conn2md_pdma_irq_b_F32K = 35, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37, |
| EVENT_ipsec_so_int_lv_F32K = 38, |
| EVENT_conn_bt_cvsd_int_b_F32K = 39, |
| EVENT_conn_bt_isoch_irq_b_F32K = 40, |
| EVENT_eint_int_lv_F32K = 41, |
| EVENT_eint_event0_F32K = 42, |
| EVENT_eint_event1_F32K = 43, |
| EVENT_eint_event2_F32K = 44, |
| EVENT_eint_event3_F32K = 45, |
| EVENT_rgu2md_irq_b_F32K = 46, |
| EVENT_ap2md_ccif2_md_event_b_F32K = 47, |
| |
| EVENT_l1sm_timer_trig_NON_F32K = 64, |
| EVENT_mdsm_timer_trig_NON_F32K = 65, |
| EVENT_dem_trig_md_int_le_NON_F32K, |
| EVENT_fe_md_share_d12mint1_b_NON_F32K = 67, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68, |
| EVENT_mcu_bus_decerr_irq_NON_F32K = 69, |
| EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70, |
| EVENT_cs_nr_irq_NON_F32K, |
| EVENT_cs_err_irq_NON_F32K, |
| EVENT_ulsp_log_md_rt_int_NON_F32K = 73, |
| EVENT_ulsp_log_md_od_int_NON_F32K = 74, |
| EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75, |
| EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76, |
| EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77, |
| EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80, |
| EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K, |
| EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84, |
| EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85, |
| EVENT_ap2md_usb_rx_gpd_done_NON_F32K, |
| EVENT_ap2md_usb_dma_active_NON_F32K = 87, |
| EVENT_ap2md_usb_ip_wakeup_NON_F32K, |
| EVENT_ap2md_usb_mcu_irq_b_NON_F32K, |
| EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90, |
| EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K, |
| EVENT_ap2md_ssusb_dma_active_NON_F32K = 92, |
| EVENT_ap2md_ssusb_ip_wakeup_NON_F32K, |
| EVENT_ap2md_ssusb_dev_int_b_NON_F32K, |
| EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95, |
| EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96, |
| EVENT_ap2md_cldma_ip_busy_NON_F32K = 97, |
| EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98, |
| EVENT_conn2md_pdma_irq_b_NON_F32K = 99, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101, |
| EVENT_ipsec_so_int_lv_NON_F32K = 102, |
| EVENT_conn_bt_cvsd_int_b_NON_F32K = 103, |
| EVENT_conn_bt_isoch_irq_b_NON_F32K = 104, |
| EVENT_eint_int_lv_NON_F32K = 105, |
| EVENT_eint_event0_NON_F32K = 106, |
| EVENT_eint_event1_NON_F32K = 107, |
| EVENT_eint_event2_NON_F32K = 108, |
| EVENT_eint_event3_NON_F32K = 109, |
| EVENT_rgu2md_irq_b_NON_F32K = 110, |
| EVENT_ap2md_ccif2_md_event_b_NON_F32K = 111, |
| } sm_event_e; |
| #else |
| typedef enum |
| { |
| EVENT_l1sm_timer_trig_F32K = 0, |
| EVENT_mdsm_timer_trig_F32K = 1, |
| EVENT_dem_trig_md_int_le_F32K = 2, |
| EVENT_fe_md_share_d12mint1_b_F32K = 3, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_F32K = 4, |
| EVENT_mcu_bus_decerr_irq_F32K = 5, |
| EVENT_usip_ia_ostimer_wakeup_b_F32K = 6, |
| EVENT_cs_nr_irq_F32K, |
| EVENT_cs_err_irq_F32K, |
| EVENT_ulsp_log_md_rt_int_F32K = 9, |
| EVENT_ulsp_log_md_od_int_F32K = 10, |
| EVENT_ulsp_log_dsp4g_rt_int_F32K = 11, |
| EVENT_ulsp_log_dsp4g_od_int_F32K = 12, |
| EVENT_ulsp_log_dsp5g_rt_int_F32K = 13, |
| EVENT_ulsp_log_dsp5g_od_int_F32K = 14, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_F32K = 15, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_F32K = 16, |
| EVENT_vcore_mml1_dsppmu_top_emi_irq_F32K = 17, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_F32K = 18, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_F32K = 19, |
| EVENT_mml1_dspcsif_top_err_cirq_F32K = 20, |
| EVENT_ap2md_usb_rx_not_empty_F32K, |
| EVENT_ap2md_usb_rx_gpd_done_F32K = 22, |
| EVENT_ap2md_usb_dma_active_F32K, |
| EVENT_ap2md_usb_ip_wakeup_F32K = 24, |
| EVENT_ap2md_usb_mcu_irq_b_F32K =25, |
| EVENT_ap2md_ssusb_rx_not_empty_F32K, |
| EVENT_ap2md_ssusb_rx_gpd_done_F32K = 27, |
| EVENT_ap2md_ssusb_dma_active_F32K, |
| EVENT_ap2md_ssusb_ip_wakeup_F32K = 29, |
| EVENT_ap2md_ssusb_dev_int_b_F32K = 30, |
| EVENT_ap2md_ccif0_md_event_b_F32K = 31, |
| EVENT_ap2md_ccif1_md_event_b_F32K = 32, |
| EVENT_ap2md_cldma_ip_busy_F32K = 33, |
| EVENT_ap2md_dpmaif_mdtopsm_int_F32K = 34, |
| EVENT_conn2md_pdma_irq_b_F32K = 35, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_F32K = 36, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_F32K = 37, |
| EVENT_ipsec_so_int_lv_F32K = 38, |
| EVENT_conn_bt_cvsd_int_b_F32K = 39, |
| EVENT_conn_bt_isoch_irq_b_F32K = 40, |
| EVENT_eint_int_lv_F32K = 41, |
| EVENT_eint_event0_F32K = 42, |
| EVENT_eint_event1_F32K = 43, |
| EVENT_eint_event2_F32K = 44, |
| EVENT_eint_event3_F32K = 45, |
| EVENT_rgu2md_irq_b_F32K = 46, |
| EVENT_ap2md_ccif2_md_event_b_F32K = 47, |
| EVENT_ap2md_apmcu_suspend_irq_F32K = 48, |
| EVENT_ap2md_apmcu_active_irq_F32K = 49, |
| |
| EVENT_l1sm_timer_trig_NON_F32K = 64, |
| EVENT_mdsm_timer_trig_NON_F32K = 65, |
| EVENT_dem_trig_md_int_le_NON_F32K, |
| EVENT_fe_md_share_d12mint1_b_NON_F32K = 67, |
| EVENT_fe_md_cssys_ltel1_cs_irq_b_NON_F32K = 68, |
| EVENT_mcu_bus_decerr_irq_NON_F32K = 69, |
| EVENT_usip_ia_ostimer_wakeup_b_NON_F32K = 70, |
| EVENT_cs_nr_irq_NON_F32K, |
| EVENT_cs_err_irq_NON_F32K, |
| EVENT_ulsp_log_md_rt_int_NON_F32K = 73, |
| EVENT_ulsp_log_md_od_int_NON_F32K = 74, |
| EVENT_ulsp_log_dsp4g_rt_int_NON_F32K = 75, |
| EVENT_ulsp_log_dsp4g_od_int_NON_F32K = 76, |
| EVENT_ulsp_log_dsp5g_rt_int_NON_F32K = 77, |
| EVENT_ulsp_log_dsp5g_od_int_NON_F32K = 78, |
| EVENT_mcore0_mml1_dsppmu_top_emi_irq_NON_F32K = 79, |
| EVENT_mcore1_mml1_dsppmu_top_emi_irq_NON_F32K = 80, |
| EVENT_vcore_mml1_dsppmu_top_emi_irq_NON_F32K = 81, |
| EVENT_mml1_dspcsif_top_s2c0_cirq_NON_F32K, |
| EVENT_mml1_dspcsif_top_s2c1_cirq_NON_F32K, |
| EVENT_mml1_dspcsif_top_err_cirq_NON_F32K = 84, |
| EVENT_ap2md_usb_rx_not_empty_NON_F32K = 85, |
| EVENT_ap2md_usb_rx_gpd_done_NON_F32K, |
| EVENT_ap2md_usb_dma_active_NON_F32K = 87, |
| EVENT_ap2md_usb_ip_wakeup_NON_F32K, |
| EVENT_ap2md_usb_mcu_irq_b_NON_F32K, |
| EVENT_ap2md_ssusb_rx_not_empty_NON_F32K = 90, |
| EVENT_ap2md_ssusb_rx_gpd_done_NON_F32K, |
| EVENT_ap2md_ssusb_dma_active_NON_F32K = 92, |
| EVENT_ap2md_ssusb_ip_wakeup_NON_F32K, |
| EVENT_ap2md_ssusb_dev_int_b_NON_F32K, |
| EVENT_ap2md_ccif0_md_event_b_NON_F32K = 95, |
| EVENT_ap2md_ccif1_md_event_b_NON_F32K = 96, |
| EVENT_ap2md_cldma_ip_busy_NON_F32K = 97, |
| EVENT_ap2md_dpmaif_mdtopsm_int_NON_F32K = 98, |
| EVENT_conn2md_pdma_irq_b_NON_F32K = 99, |
| EVENT_ap2md_conn_bgf_ccif_md_event_b_NON_F32K = 100, |
| EVENT_ap2md_conn_wf_ccif_md_event_b_NON_F32K = 101, |
| EVENT_ipsec_so_int_lv_NON_F32K = 102, |
| EVENT_conn_bt_cvsd_int_b_NON_F32K = 103, |
| EVENT_conn_bt_isoch_irq_b_NON_F32K = 104, |
| EVENT_eint_int_lv_NON_F32K = 105, |
| EVENT_eint_event0_NON_F32K = 106, |
| EVENT_eint_event1_NON_F32K = 107, |
| EVENT_eint_event2_NON_F32K = 108, |
| EVENT_eint_event3_NON_F32K = 109, |
| EVENT_ap2md_apmcu_suspend_irq_NON_F32K = 110, |
| EVENT_ap2md_apmcu_active_irq_NON_F32K = 111, |
| } sm_event_e; |
| #endif |
| #endif |
| |
| /***************************************************************************** |
| * Functions provided by OSTD |
| *****************************************************************************/ |
| |
| /* For ARM Side OS Timer Upper Layer */ |
| extern void OSTD_Init( void ); |
| extern void OSTD_EnOST( kal_bool enable ); |
| extern void OSTD_SetFrmDur( kal_uint16 frm_dur ); |
| extern void OSTD_GetCurrFrm( OSTD_FRM_INFO_T *pFrm_Info ); |
| extern OSTD_RESULT_E OSTD_SetAfn( kal_uint32 afn ); |
| extern OSTD_RESULT_E OSTD_SetUfn( kal_uint32 ufn ); |
| extern OSTD_RESULT_E OSTD_SetAfnUfn( kal_uint32 afn,kal_uint32 ufn ); |
| |
| |
| /* For ARM Side OS Timer Sleep Mode Manager */ |
| extern kal_checksleep_e OSTD_CheckSleep( void ); |
| extern void OSTD_CSC_handler( void ); |
| extern kal_uint32 OSTD_CheckIsSleepLock(void); |
| |
| /* For AT CMD of AT+SLEEPCOUNT */ |
| extern kal_bool OSTD_SleepCountGet( kal_uint32 * cnt, kal_uint32 * time, kal_uint32 * acc_time ); |
| extern kal_bool OSTD_SleepCountSet( kal_uint32 op ); |
| extern kal_bool OSTD_GetModemSleepTime( kal_uint32 *acc_time ); |
| |
| /* For Modem Infinite Sleep */ |
| extern kal_bool OSTD_Radio_On_Query(void); |
| extern kal_bool OSTD_Infinite_Sleep_Query(void); |
| extern kal_chkslp_inf_e OSTD_chkslp_is_all_timers_infinite_sleep(void); |
| extern OSTD_RESULT_E OSTD_MD_Infinite_Sleep(void); |
| extern OSTD_RESULT_E OSTD_Infinite_Sleep_TimerInform(OSTD_TIMER_TYPE_E timer, kal_bool sta); |
| extern void OSTD_Radio_ON(void); |
| extern void OSTD_Radio_OFF(void); |
| extern void OSTD_Radio_OFF_SleepCheck(void); |
| extern void OSTD_UnmaskIRQ( void ); |
| |
| /* For Power Modelling */ |
| extern void OSTD_Idle_Rate_Logging(kal_uint32); |
| |
| /* For Mumtas*/ |
| #ifndef L1_SIM |
| extern ostd_ap_core_status_enum OSTD_return_AP_status(void); |
| extern void is_pending_data(char* module_name, kal_bool flag); |
| #endif |
| #endif |
| |
| #endif /*__CENTRALIZED_SLEEP_MANAGER__*/ |
| |