| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2020 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
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| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
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| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
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| * |
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| * |
| *****************************************************************************/ |
| |
| #ifndef __SYNC_DATA_H__ |
| #define __SYNC_DATA_H__ |
| |
| #include "reg_base.h" |
| #include "mips_ia_utils_public.h" |
| |
| // DSB: Data_Sync_Barrier() |
| #if defined(__MIPS_I7200__) && defined(__MTK_TARGET__) |
| # define Data_Sync_Barrier() miu_syncn(7) |
| # define MO_Sync() miu_syncn(6) |
| # define MM_Sync() miu_syncn(3) |
| # define Data_Coherent_Sync() miu_syncn(0x10) |
| #elif defined(__MIPS_IA__) && defined(__MTK_TARGET__) |
| # define Data_Sync_Barrier() do { \ |
| register kal_uint32 __tmp__; \ |
| __asm__ volatile ( \ |
| "sync 0x3\n" \ |
| "lw %0, 0(%1)\n" \ |
| "sw %0, 0(%1)\n" \ |
| :"=&d"(__tmp__) \ |
| :"d"(BASE_ADDR_MO_SYNC_MAGIC) \ |
| : "memory" \ |
| );\ |
| } while (0) |
| # define MO_Sync() do { \ |
| register kal_uint32 __tmp__; \ |
| __asm__ volatile ( \ |
| "sw %0, 0(%1)\n" \ |
| "lw %0, 0(%1)\n" \ |
| "sw %0, 0(%1)\n" \ |
| :"=&d"(__tmp__) \ |
| :"d"(BASE_ADDR_MO_SYNC_MAGIC) \ |
| : "memory" \ |
| );\ |
| } while (0) |
| # define MM_Sync() miu_syncn(3) |
| # define Data_Coherent_Sync() do {} while(0) |
| #else /* __MIPS_IA__ && __MTK_TARGET__ */ |
| #define Data_Sync_Barrier() do {} while(0) |
| #define MO_Sync() do {} while(0) |
| #define MM_Sync() do {} while(0) |
| #define Data_Coherent_Sync() do {} while(0) |
| #endif /* __MIPS_IA__ && __MTK_TARGET__ */ |
| |
| // DMB: Data_Mem_Barrier() |
| #define Data_Mem_Barrier() do {} while(0) |
| |
| // ISB: Inst_Sync_Barrier() |
| #define Inst_Sync_Barrier() do {} while(0) |
| |
| #endif /* __SYNC_DATA_H__ */ |