| #ifndef _IDC_L5_ENUM_H |
| #define _IDC_L5_ENUM_H |
| |
| #if defined(CHIP10992) || defined(__NANO_UT__) |
| |
| typedef enum |
| { |
| |
| IDC_LAA_RESTRICTED_POSSIBLE = 0, |
| IDC_LAA_RESTRICTED_IMPOSSIBLE = 1, |
| IDC_LAA_RESTRICTED_INVALID = 2 |
| }idc_laa_restricted_enum; |
| |
| typedef enum |
| { |
| IDC_DYNAMIC_SET_MODE_DISABLE = 0, //disable unsolicited ntf |
| IDC_DYNAMIC_SET_MODE_ENABLE = 1, //enable unsolicited ntf |
| IDC_DYNAMIC_SET_MODE_CONFIG = 2, //config mode via MBIM (Intel) |
| IDC_DYNAMIC_SET_MODE_CONFIG_BY_MIPC = 3, //config mode via MIPC (Quanta) |
| IDC_DYNAMIC_SET_MODE_INVALID = 0x7FFFFFFF |
| }idc_dynamic_set_mode_enum; |
| |
| typedef enum |
| { |
| IDC_FILTER_TYPE_RX = 0, |
| IDC_FILTER_TYPE_TX = 1, |
| IDC_FILTER_TYPE_NUM = 2 |
| }idc_filter_type_enum; |
| |
| typedef enum |
| { |
| IDC_CNF_STATUS_SUCCESS = 0, |
| IDC_CNF_STATUS_FAILURE = 1, |
| IDC_CNF_STATUS_INVALID = 2 |
| } idc_cnf_status_enum; |
| |
| typedef enum |
| { |
| IDC_MBIM_CFG_TYPE_DEFAULT = 0, |
| IDC_MBIM_CFG_TYPE_SET = 1, |
| IDC_MBIM_CFG_TYPE_QUERY = 2, |
| IDC_MBIM_CFG_TYPE_NTF = 3, |
| IDC_MBIM_CFG_TYPE_NUM = 4 |
| } l5_idc_mbim_cfg_type_enum; |
| |
| #endif |
| #endif |