mcu/driver/devdrv/btdma/src/btdma.c

#include <stdio.h>
#include "drv_comm.h"
#include "btdma_public.h"
#include "btdma_private.h"
//#include "spinlock_hw_public.h"
#include "intrCtrl.h"


#define LSB_DIR_ONE(input,output)\
	output = __builtin_ctz(input)

#define BTDMA_REG32(addr) (*((volatile btdma_uint32 *)(addr)))
#define BTDMA_ASSERT()



#undef BTDMA_CALLBACK_REGISTER
#define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) extern void CALLBACK(void);
#include "btdma_callback_reg.h"
#undef BTDMA_CALLBACK_REGISTER


#define cc_spinlock_hw_take_lock(resource)
#define cc_spinlock_hw_give_lock(resource)
typedef void (*btdma_callback_type)(void);



#if 0
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#if defined(__BTDMA_DRIVER_TEST__)
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#endif
#endif


btdma_callback_type btdma_callback[] = {
#undef BTDMA_CALLBACK_REGISTER
#define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) CALLBACK,
#include "btdma_callback_reg.h"
#undef BTDMA_CALLBACK_REGISTER
  0
};


void BTDMA_Interrupt_Handler(kal_uint32 irq_id);
void BTDMA_Exception_Handler(kal_uint32 irq_id){
EXT_ASSERT(0, 0, 0, 0);
}


static inline void BTDMA_MPU_AXI_Set(btdma_uint32 channel, 
                                     btdma_uint32 start_address, 
		                     btdma_uint32 end_address)
{
  DRV_WriteReg32(BTDMA_MPU_REGION_AXI_START_ADDR + channel * 4 ,start_address);
  DRV_WriteReg32(BTDMA_MPU_REGION_AXI_END_ADDR + channel * 4 ,end_address);
  DRV_WriteReg32(BTDMA_MPU_ENABLE_ADDR ,(DRV_Reg32(BTDMA_MPU_ENABLE_ADDR)) |(1 << channel));

}


static inline void BTDMA_MPU_DBUS_Set(btdma_uint32 channel,
                                      btdma_uint32 start_address,
			              btdma_uint32 end_address)
{
  DRV_WriteReg32(BTDMA_MPU_REGION_DBUS_START_ADDR + channel * 4 ,start_address);
  DRV_WriteReg32(BTDMA_MPU_REGION_DBUS_END_ADDR + channel * 4 ,end_address);

#if  !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833)
  DRV_WriteReg32(BTDMA_MPU_TYPE_ADDR ,(DRV_Reg32(BTDMA_MPU_TYPE_ADDR)) |(1 << (channel+BTDMA_MPU_AXI_CHANNEL_NUM))); 
#endif

  DRV_WriteReg32(BTDMA_MPU_ENABLE_ADDR ,(DRV_Reg32(BTDMA_MPU_ENABLE_ADDR)) |(1 << (channel+BTDMA_MPU_AXI_CHANNEL_NUM)));


}

void BTDMA_MPU_EMI_Region_Set(btdma_uint32 start_address,btdma_uint32 end_address)
{
 BTDMA_MPU_AXI_Set(0,start_address,end_address);
}


void BTDMA_interrupt_register()
{
	//IRQ_Register_LISR(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE, BTDMA_Interrupt_Handler, "btdma");
	//IRQSensitivity(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE, LEVEL_SENSITIVE);
        IRQUnmask(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE);
}

void BTDMA_exception_register()
{
	//IRQ_Register_LISR(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE, BTDMA_Exception_Handler, "btdma_exception");
	//IRQSensitivity(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE, LEVEL_SENSITIVE);
	IRQUnmask(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE);
}

void BTDMA_Init()
{

   BTDMA_interrupt_register(); 
   BTDMA_exception_register();

#if defined(__MD97P__)
   BTDMA_MPU_AXI_Set(1,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM+0X600000);
   BTDMA_MPU_DBUS_Set(0,BASE_MADDR_VCORE_THREAD0_ICM,BASE_ADDR_MODEML1_AO_VCOREHRAM_PAR_AO_SRAM);
   BTDMA_MPU_DBUS_Set(1,BASE_MADDR_MCORE_MSYS_DSPCBSCHEDULER,BASE_MADDR_VCORE_THREAD0_ICM); 
#else
   BTDMA_MPU_AXI_Set(1,BASE_MADDR_HRAM_MML1_HRAM_BRICK,BASE_MADDR_HRAM_MML1_HRAM_BRICK+0X600000);
   BTDMA_MPU_DBUS_Set(0,BASE_MADDR_VCORE_THREAD0_LOCAL_ICM,BASE_MADDR_HRAM_MML1_HRAM_BRICK);
   BTDMA_MPU_DBUS_Set(1,BASE_MADDR_MCORE0_CBSCHEDULER,BASE_MADDR_VCORE_TH0_L1MC__CR);
#endif
}


#if 0
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void SS_BTDMA_Trigger(btdma_description* desc,
		              btdma_priority_chain priority,
		              btdma_callback_index callback_key)  
{
    desc[0].callback_key = callback_key; 
    DRV_WriteReg32(BTDMA_DESC_CTRL_0_PRI0_START_ADDR  + priority * 4, (btdma_uint32)desc);
    DRV_WriteReg32(BTDMA_DESC_CTRL_0_PRI0_TRIG_ADDR  + priority * 4, 0x1);
}


void BTDMA_Polling_Priority_idle(btdma_uint32 priority)
{
	kal_uint32 volatile  status = DRV_Reg32(BTDMA_BASE_ADDR + BTDMA_DESC_STS_4_OFFSET+ priority * 4);
        status = status >> BTDMA_DESC_STS_4_CMD_STS_POS;

        while(status !=0){
		status = (DRV_Reg32(BTDMA_BASE_ADDR + BTDMA_DESC_STS_4_OFFSET+ priority * 4))>> BTDMA_DESC_STS_4_CMD_STS_POS;
        }
}

#if 0
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void BTDMA_Interrupt_Handler(kal_uint32 irq_id)
{
    btdma_uint32 signal_status = BTDMA_REG32(BTDMA_INTERRUPT_STS_ADDR);
    btdma_uint32 trigger_priority = 0;
    //LSB_DIR_ONE(signal_status,trigger_priority);

	trigger_priority = __builtin_ctz(signal_status);
    

    while(trigger_priority < BTDMA_PRIO_CHAIN_NUM && signal_status != 0){

      btdma_description* desc = (btdma_description*)DRV_Reg32(DRV_Reg32(BTDMA_DESC_CTRL_0_PRI0_START_ADDR  + trigger_priority * 4));
      btdma_uint32 callback_key = (btdma_uint32)(*desc).callback_key;

      DRV_WriteReg32(BTDMA_INTERRUPT_STS_ADDR,1 <<trigger_priority);
      

      //call user callback
      (*btdma_callback[callback_key])();

      signal_status = BTDMA_REG32(BTDMA_INTERRUPT_STS_ADDR);

      //LSB_DIR_ONE(signal_status,trigger_priority);
		trigger_priority = __builtin_ctz(signal_status);

    }
}


#if 0
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void BTDMA_SW_Enable_Ungate_Signal(btdma_core core)
{
  btdma_uint32 temp;

    temp = BTDMA_REG32(BTDMA_SIGNAL_CTRL0_ADDR);
    DRV_WriteReg32(BTDMA_SIGNAL_CTRL0_ADDR,temp | (1 << core));
    MO_Sync();

}

void BTDMA_SW_Disable_Ungate_Signal(btdma_core core)
{
  btdma_uint32 temp;

    temp = BTDMA_REG32(BTDMA_SIGNAL_CTRL0_ADDR);
    DRV_WriteReg32(BTDMA_SIGNAL_CTRL0_ADDR,temp & ~(1 << core)); 
     MO_Sync();
}

void BTDMA_Debug_Dump()
{

}