mcu/driver/devdrv/cirq/md97/src/isrentry.c

/*****************************************************************************
*  Copyright Statement:
*  --------------------
*  This software is protected by Copyright and the information contained
*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2005
*
*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
*
*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
*
*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
*
*****************************************************************************/

/*****************************************************************************
 *
 * Filename:
 * ---------
 *   isrentry.c
 *
 * Project:
 * --------
 *   Maui_Software
 *
 * Description:
 * ------------
 *   This Module defines the IRQ service routines for all IRQ sources
 *
 * Author:
 * -------
 * -------
 *
 *============================================================================
 *             HISTORY
 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
 *============================================================================
 ****************************************************************************/
/*******************************************************************************
 * Include header files.
 *******************************************************************************/
#ifdef __MTK_TARGET__
#include <mips/mt.h>
#endif
#include "reg_base.h"
#include "isrentry.h"
#include "intrCtrl.h"

#if defined __MIPS_I7200__
#include "md97/idle_service.h"
#include "drv_rstctl.h"
#endif

#include "kal_hrt_api.h"
#include "sync_data.h"
#include "kal_general_types.h"
#include "kal_public_api.h"
#include "kal_public_defs.h"
#include "us_timer.h"
#include "drv_mdcirq.h"
#include "drv_mdcirq_reg.h"
#include "kal_iram_section_defs.h"
#include "drv_vpe_irq.h"
#include "kal_cpuinfo.h"
#include "mips_ia_utils.h"
#include "drv_vpe_irq.h"
#include "ex_public.h"
#include "SST_sla.h"
#include "swtr.h"
#include "kal_internal_api.h"
#include "mddbg_public.h"
#include "kal_wp_hook.h"

#if defined(__ESL_DBG_UTIL__)
#include "esl_debug.h"
#else  /* __ESL_DBG_UTIL__ */
#define esl_printf(donothing...) do {;}while(0)
#endif /* __ESL_DBG_UTIL__ */

/*************************************************************************
 * Define function prototypes and data structures.
 *************************************************************************/

extern void kal_hrt_mt_save(kal_uint32 irqvector, kal_mt_stack_ptr *stack_ptr);
extern void kal_hrt_mt_restore(kal_uint32 irqvector, kal_mt_stack_ptr *stack_ptr);

#if defined(__DUMMY_L1_ON_TARGET_4G5G__)
extern void xl1r_vpe_idle_setup_False(void);
#endif

/*************************************************************************
 * Define imported global data.
 *************************************************************************/
extern kal_uint16 HWIRQCode2SWIRQCode[];
extern kal_uint16 SWIRQCode2HWIRQCode[];

#if defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
extern kal_uint32 ECT_VPE_Trigger_Status[];
#endif

/*************************************************************************
 * Define global data.
 *************************************************************************/
irqlisr_entry lisr_dispatch_tbl[NUM_IRQ_SOURCES];

__MCURW_HWRW_C_ALIGNED_L2CACHE_LOCK_ZI(4) void *processing_lisr[MDCIRQ_TOTAL_VPE_NUM];
#if defined(__MD97_IS_2CORES__)
__MCURW_HWRW_C_ALIGNED_L2CACHE_LOCK_RW(4) kal_uint32 processing_irqx[MDCIRQ_TOTAL_VPE_NUM] = {IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT};
#else
__MCURW_HWRW_C_ALIGNED_L2CACHE_LOCK_RW(4) kal_uint32 processing_irqx[MDCIRQ_TOTAL_VPE_NUM] = {IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT};
#endif

#if defined(__MDCIRQ_MPB_PROFILE__)
__MCURW_HWRO_C_ALIGNED_ZI_WB(32) kal_uint32 processing_hrt_irq_count[8];
kal_uint32 max_concur_hrt_irq_count = 0; // Include both Running HRT ISRs & Preempted HRT ISRs
kal_uint32 max_concur_processing_hrt_irqx[MDCIRQ_TOTAL_VPE_NUM] = {IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT, IRQ_NOT_LISR_CONTEXT};
kal_uint32 max_concur_hrt_irq_frc = 0;
#endif

__MCURW_HWRW_C_ALIGNED_L2CACHE_LOCK_ZI(4) kal_uint32 processing_irqCnt[MDCIRQ_TOTAL_VPE_NUM];
__MCURW_HWRW_C_ALIGNED_L2CACHE_LOCK_ZI(4) kal_uint32 max_processing_irqCnt[MDCIRQ_TOTAL_VPE_NUM];

/* spurious interrupt log */
#define SPURIOUS_IRQ_LOG_SIZE 20
kal_uint32 spurious_count[MDCIRQ_TOTAL_VPE_NUM] = {0};
kal_uint32 spurious_id[MDCIRQ_TOTAL_VPE_NUM][SPURIOUS_IRQ_LOG_SIZE];

/*************************************************************************
 * Macro Definitions for "CIRQ Dispatch Misbehaviour" SW Workaround      *
 *************************************************************************/
#define MDCIRQ_DUMMY_DI() \
do{                       \
    __asm__ __volatile__( \
        "di\n\t"          \
        "ehb\n\t"         \
    );                    \
} while(0)

#define MDCIRQ_DUMMY_EI() \
do{                       \
    __asm__ __volatile__( \
        "ei\n\t"          \
        "ehb\n\t"         \
    );                    \
} while(0)


/* Delay cirq_cycle T * 6(Shaolin to CIRQ clock ratio) * 2(dual issue) */
/* 6T per round => 5 nop + 1 addiu from for loop */
#define MDCIRQ_DELAY_LOOP(cirq_cycle)                                               \
do{                                                                                 \
    register kal_uint32 _delay_loop;                                                \
    for(_delay_loop = 0; _delay_loop < cirq_cycle * 2; _delay_loop++) {             \
        __asm__ __volatile__(                                                       \
            "nop\n\t"                                                               \
            "nop\n\t"                                                               \
            "nop\n\t"                                                               \
            "nop\n\t"                                                               \
            "nop\n\t"                                                               \
        );                                                                          \
    }                                                                               \
}while(0)

/*************************************************************************
 * Macro Definitions for "CIRQ Dispatch Misbehaviour" SW Workaround End  *
 *************************************************************************/

/*************************************************************************
* FUNCTION
*  MDCIRQ_IRQ_Register_LISR
*
* DESCRIPTION
*   This function implement method to register IRQ's LISR.
*
* CALLS
*
* CALL BY
*
* PARAMETERS
*  HWIRQID   -  vector number to register
*  reg_lisr    -  register LISR's handler
*  description -  LISR's description pointer to be saved.
*     Remember, the routine won't duplicate the description,
*     therefore, caller shouldn't free the description.
*
* RETURNS
*
*************************************************************************/
void MDCIRQ_IRQ_Register_LISR(kal_uint16 HWIRQCode, void (*reg_lisr)(kal_uint32), char* description)
{
    kal_uint32 savedMask, SWIRQCode;

    savedMask = kal_hrt_SaveAndSetIRQMask();
    SWIRQCode = (kal_uint32)HWIRQCode2SWIRQCode[HWIRQCode];
    lisr_dispatch_tbl[HWIRQCode].vector = SWIRQCode;
    lisr_dispatch_tbl[HWIRQCode].lisr_handler = reg_lisr;
    lisr_dispatch_tbl[HWIRQCode].description = description;
    kal_hrt_RestoreIRQMask(savedMask);
}

/*************************************************************************
* FUNCTION
*  MDCIRQ_IRQ_LISR_Init
*
* DESCRIPTION
*   This function implement IRQ's LISR (Low-level Interrupt Service Routine)
*  Table initialization.
*
* CALLS
*
* CALL BY
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void MDCIRQ_IRQ_LISR_Init()
{
    kal_uint32 i;
    for (i = NUM_IRQ_SOURCES; i != 0; i--)
    {
        MDCIRQ_IRQ_Register_LISR(i - 1, MDCIRQ_IRQ_Default_LISR, "NULL handler");
    }
}

/*************************************************************************
* FUNCTION
*  MDCIRQ_IRQ_Retrieve_LISR
*
* DESCRIPTION
*   This function implement to retrieve register LISR handler
*
* CALLS
*
* CALL BY
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void* MDCIRQ_IRQ_Retrieve_LISR(kal_uint16 HWIRQCode)
{
    return(void*)(lisr_dispatch_tbl[HWIRQCode].lisr_handler);
}

/*************************************************************************
* FUNCTION
*  IRQ_Default_LISR
*
* DESCRIPTION
*   This function implement default IRQ' LISR
*
* CALLS
*
* CALL BY
*  IRQ_LISR_Init()
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
void MDCIRQ_IRQ_Default_LISR(kal_uint32 irq_id)
{
    kal_fatal_error_handler(KAL_ERROR_NON_REGISTERED_LISR, irq_id);
}

void INT_Timer_Interrupt(void)
{
    kal_timer_interrupt();
}

void isrC_Main(kal_uint32 vector)
{

    kal_uint32 vpe_num;
    kal_uint32 irqx_swcode, irqx_swcode_non_spurious;
    kal_uint32 irqx_hwcode, irqx_hwcode_non_spurious;
    void       *processing_lisr_backup;
    kal_uint32 processing_irqx_backup;
    kal_uint32 ori_vpe_state;
    kal_mt_stack_ptr mt_stack_ptr_backup = {{NULL}};

    ASSERT_EXL_SAFE(vector == VPE_IRQID_MDCIRQ);

    vpe_num = kal_get_current_vpe_id();
    processing_lisr_backup = processing_lisr[vpe_num];
    processing_irqx_backup = processing_irqx[vpe_num];

#if defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
    do {
#endif

#if defined(__MDCIRQ_GCR_SIGNAL_DISABLE__)
    irqx_swcode = DRV_Reg32(MDCIRQ_VPE_IRQ_ID_BASE + (vpe_num<<2));
#else
    irqx_swcode = DRV_Reg32(MDCIRQ_GCR_VPE_IRQ_ID_BASE + (vpe_num<<2));
#endif

    irqx_swcode_non_spurious = irqx_swcode & 0x1ff;

    /* Set&backup VPE IRQ state */
    ori_vpe_state = drv_mdcirq_SaveAndSet_VPE_state(vpe_num, irqx_swcode_non_spurious);

#if defined __MIPS_I7200__
    /* Reset TC's priority according IRQ's Priority */
    register miu_reg32_t tc_priority;
    if (irqx_swcode < IRQ_HRT_PRIORITY_THRESHOLD) {
        // HRT IRQs
        tc_priority = HRT_CONTEXT_GRP;
#if defined(__MDCIRQ_MPB_PROFILE__)
        kal_atomic_inc(&processing_hrt_irq_count[0]);
#endif
    } else {
    	// Non-HRT IRQs and Spurious IRQs
        tc_priority = kal_get_current_domain();
    }
    miu_mtc0(MIU_C0_TCSCHEDULE, tc_priority << MIU_C0_TCSCHEDULE_PRIO_BITFIELD_BEG);
    
#else /* MT6297_IA */
    /* Not set when spurious interrput, so take original read ID result as parameter */
    if( !kal_if_hrt_domain(vpe_num) )
    {
        LISR_RAISE_TC_PRIO(irqx_swcode);
    }
#endif

#if defined(__DUMMY_L1_ON_TARGET_4G5G__)
    /* Record current VPE is not in Idletask for KS IODT FPGA */
    xl1r_vpe_idle_setup_False();
#endif

    irqx_hwcode_non_spurious = (kal_uint32)SWIRQCode2HWIRQCode[irqx_swcode_non_spurious];
    irqx_hwcode = irqx_hwcode_non_spurious | (irqx_swcode&0x200);

    /* Use HW code to do IRQ logging */
    esl_printf(ESL_SIM_TIME_FLAG|ESL_WALL_TIME_FLAG, "[ISR-%d S]\n", irqx_hwcode);
	
    /* These global variable will be used by others. The meaning should keep the same as 93*/
    processing_irqx[vpe_num] = irqx_hwcode_non_spurious;
    processing_lisr[vpe_num] = (void*)lisr_dispatch_tbl[irqx_hwcode_non_spurious].lisr_handler;
    processing_irqCnt[vpe_num]++;
    if(processing_irqCnt[vpe_num]>max_processing_irqCnt[vpe_num])
    {
        max_processing_irqCnt[vpe_num] = processing_irqCnt[vpe_num];
    }
	
    SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)irqx_hwcode), vpe_num);

    /************************************************************************************
    * SW workaround for "CIRQ Dispatch Misbehaviour"                                    *
    * When low priority IRQ is enterting IRQ handler flow (readID ~ set vpe state), and *
    * high priority IRQ is choosing best vpe according to vpe state, the high priority  *
    * IRQ will dispatch to the same VPE and preempt low priority IRQ since vpe state    *
    * of the low priority IRQ has not yet been updated to CIRQ. This may cause two      *
    * critical LISRS to run on the same VPE while other VPEs are in IDLE. Therefore, we *
    * trigger a dummy DI/EI below to force high priority IRQ to be resent to other VPEs.*
    *************************************************************************************/

#if defined(__MDCIRQ_GCR_SIGNAL_DISABLE__)
    /* Dummy read APB_VPE_IRQ_STATE to guarantee value has been written to CIRQ */
    ASSERT_EXL_SAFE(MDCIRQ_READ_REG_INDEX(MDCIRQ_VPE_IRQ_STATE_BASE, vpe_num) == irqx_swcode_non_spurious);
#else
    /* Dummy read GCR_VPE_IRQ_STATE to guarantee value has been written to GCR,
       then wait for 3T CIRQ clock so that the GCR value is synced to CIRQ */
    ASSERT_EXL_SAFE(MDCIRQ_READ_REG_INDEX(MDCIRQ_GCR_VPE_IRQ_STATE_BASE, vpe_num) == irqx_swcode_non_spurious);
    MDCIRQ_DELAY_LOOP(3);
#endif

    /* Dummy DI/EI to force pending IRQs to be resent */
    MDCIRQ_DUMMY_DI();
    MDCIRQ_DELAY_LOOP(3);
    MDCIRQ_DUMMY_EI();

    /************************************************************************************
    * SW workaround for "CIRQ Dispatch Misbehaviour" End                                *
    *************************************************************************************/

    /* Non-Spurious IRQ */
    if(!(irqx_hwcode&0x200))
    {
        kal_hrt_mt_save(irqx_hwcode_non_spurious, &mt_stack_ptr_backup);
#if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
        /* Mask OSIPI in the first IRQ LISR (because OSIPI is the lowest priority) */
        if( processing_irqCnt[vpe_num] == 1 )
        {
            VPE_IRQ_MASK(VPE_IRQID_OSIPI);
        }
#endif
#if defined __MIPS_I7200__
        if((kal_get_current_domain() == KAL_DOMAIN_CHRT) && (processing_irqCnt[vpe_num] == 1))
        {
            // enable and kick WDT
            drv_rstctl_set_check_bit((vpeid_e)vpe_num);
            drv_rstctl_set_kick_bit((vpeid_e)vpe_num);
        }
#endif
#if !defined(DISABLE_MDDBG_FUNCTION)
	wp_hook_dispatchLISR_start(vpe_num,irqx_hwcode_non_spurious);
#endif
        Clear_EXL();

        lisr_dispatch_tbl[irqx_hwcode_non_spurious].lisr_handler(irqx_hwcode_non_spurious);

        if(Ibit_Status()!=1)  //Ibit cannot be disabled after LISR!
        {
            kal_fatal_error_handler(KAL_ERROR_INTERRUPT_DISABLED_AFTER_LISR_FAILED, (kal_uint32)processing_lisr[vpe_num]);
        }

        Set_EXL();
#if !defined(DISABLE_MDDBG_FUNCTION)
	wp_hook_dispatchLISR_end(vpe_num,irqx_hwcode_non_spurious);
#endif

#if defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
        /* CIRQ timing limitation: "After clearing IRQ source, need to wait for
           105T CPU clock before doing priority ACK."
           => SWLA need to be placed before priority ACK */
        kal_hrt_mt_restore(irqx_hwcode_non_spurious, &mt_stack_ptr_backup);
        SLA_LoggingLISR(0xaaaaaaaa, vpe_num);
        drv_mdcirq_Restore_VPE_state(vpe_num, ori_vpe_state);

        /* In B2B flow, do priority ACK earlier so that next IRQ can be
           triggered to CPU earlier. */
        if( processing_irqx_backup == IRQ_NOT_LISR_CONTEXT)
            MDCIRQ_SYS_endIsr(vpe_num, processing_irqx_backup);
        else
            MDCIRQ_SYS_endIsr(vpe_num, (kal_uint32)HWIRQCode2SWIRQCode[processing_irqx_backup]);
#endif

#if defined(__MDCIRQ_OSIPI_SPECIAL_FLOW__)
        /* Unmask OSIPI after the first IRQ LISR */
        if( processing_irqCnt[vpe_num] == 1 )
        {
            VPE_IRQ_UNMASK(VPE_IRQID_OSIPI);
        }
#endif

#if defined __MIPS_I7200__
        if((kal_get_current_domain() == KAL_DOMAIN_CHRT) && (processing_irqCnt[vpe_num] == 1))
        {
            // disable WDT
            drv_rstctl_clr_check_bit((vpeid_e)vpe_num);
            // set wait variable
            Idle_Service_Prepare_WAIT();
        }
#endif

#if !defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
        kal_hrt_mt_restore(irqx_hwcode_non_spurious, &mt_stack_ptr_backup);
#endif
    }
    else  // spurious IRQ
    {
        spurious_id[vpe_num][spurious_count[vpe_num]%SPURIOUS_IRQ_LOG_SIZE] = irqx_hwcode;
        spurious_count[vpe_num]++;

#if defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
        SLA_LoggingLISR(0xaaaaaaaa, vpe_num);
        drv_mdcirq_Restore_VPE_state(vpe_num, ori_vpe_state);
#endif
    }

#if defined(__MDCIRQ_MPB_PROFILE__)
    if (processing_hrt_irq_count[0] >= max_concur_hrt_irq_count) {
        max_concur_hrt_irq_count = processing_hrt_irq_count[0];
        max_concur_hrt_irq_frc = ust_get_current_time();
        memcpy(max_concur_processing_hrt_irqx, processing_irqx, sizeof(processing_irqx));
    }
    if (irqx_swcode < IRQ_HRT_PRIORITY_THRESHOLD) {
        kal_atomic_dec(&processing_hrt_irq_count[0]);
    } 
#endif

    processing_irqx[vpe_num] = processing_irqx_backup;
    processing_lisr[vpe_num] = processing_lisr_backup;
    processing_irqCnt[vpe_num]--;

    /* Use HW code to do IRQ logging */
    esl_printf(ESL_SIM_TIME_FLAG|ESL_WALL_TIME_FLAG, "[ISR-%d E]\n", irqx_hwcode);

#if defined(__MDCIRQ_B2B_IRQ_SPEEDUP_FLOW__)
    /* CTI interrupt is level-trigger and the source would not be cleared.
       Therefore, ignore the pending IRQ, let it back to OS and enter exception. */
    if (ECT_VPE_Trigger_Status[vpe_num] != 0) {
        break;
    }

    /* Check if next IRQ is pending */
    /* IRQ_B <-> SI_INT[4] => IP6 => C0_CAUSE[14] */
    if (((miu_mfc0(MIU_C0_CAUSE) >> (8 + VPE_IRQID_MDCIRQ)) & 0x1) == 1) {
        /* Delay 1T CIRQ clock to ensure IRQ ID has been synced to GCR */
        MDCIRQ_DELAY_LOOP(1);

        /* CIRQ timing limitation: "SW should not DI or set min priority within
           50T CPU clock before read ID."
           => Should not DI or set SPL within 50T before this point */
    } else {
        /* No pending IRQ => exit ISR handler loop */
        break;
    }

    } while (1);
#else
    SLA_LoggingLISR(0xaaaaaaaa, vpe_num);
    drv_mdcirq_Restore_VPE_state(vpe_num, ori_vpe_state);

    /* Non-Spurious IRQ */
    if(!(irqx_hwcode&0x200))
    {
        /* IRQ idx in SW code view */
        if( processing_irqx_backup == IRQ_NOT_LISR_CONTEXT)
            MDCIRQ_SYS_endIsr(vpe_num, processing_irqx_backup);
        else
            MDCIRQ_SYS_endIsr(vpe_num, (kal_uint32)HWIRQCode2SWIRQCode[processing_irqx_backup]);
    }
#endif
}


#if 0
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif