| #ifndef __DRV_CUIF_H__ |
| #define __DRV_CUIF_H__ |
| |
| |
| #include "cuif_l1core_public.h" |
| |
| #include "intrCtrl.h" |
| #include "kal_public_api.h" |
| #include "kal_general_types.h" |
| |
| #include "sync_data.h" |
| #include "drv_comm.h" |
| #include "reg_base.h" |
| |
| #define __CUIF_DEBUG__ |
| |
| /******************************************************************************* |
| * CUIF Memory Definition |
| *******************************************************************************/ |
| |
| /* Control Register Offset */ |
| #define CUIF_INTERRUPT_STATUS_OFFSET (0x00) |
| #define CUIF_INTERRUPT_SET_OFFSET (0x04) |
| #define CUIF_INTERRUPT_CLEAR_OFFSET (0x08) |
| #define CUIF_INTERRUPT_EN_OFFSET (0x0C) |
| #define CUIF_INTERRUPT_EN_SET_OFFSET (0x10) |
| #define CUIF_INTERRUPT_EN_CLR_OFFSET (0x14) |
| |
| #define CUIF_INTERRUPT_STA_EN_OFFSET (CUIF_INTERRUPT_EN_OFFSET - CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_INTERRUPT_NEXT_INT_OFFSET (0x18) |
| |
| |
| /* C2U Core Offset*/ |
| #define CUIF_C2U_INNER (0x00 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_C2U_OUTER (0x18 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #if defined(__MD97__) || defined(__MD98__) |
| |
| #if defined(__SSDVT_CUIF_TEST__) |
| |
| #define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #else |
| |
| #define CUIF_C2U_SPEECH (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_C2U_FEC (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #endif |
| |
| #else |
| |
| #define CUIF_C2U_FEC (0x30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_C2U_SPEECH (0x48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #endif |
| |
| /* C2U INNER */ |
| #define CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_C2U_INNER_INTERRUPT_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_C2U_INNER_INTERRUPT_EN_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_INNER + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| |
| /* C2U OUTER */ |
| #define CUIF_C2U_OUTER_INTERRUPT_STATUS_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_C2U_OUTER_INTERRUPT_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_C2U_OUTER_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_C2U_OUTER_INTERRUPT_EN_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_C2U_OUTER_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_C2U_OUTER_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_OUTER + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* C2U FEC */ |
| #define CUIF_C2U_FEC_INTERRUPT_STATUS_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_C2U_FEC_INTERRUPT_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_C2U_FEC_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_C2U_FEC_INTERRUPT_EN_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_C2U_FEC_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_C2U_FEC_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_FEC + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* C2U SPEECH */ |
| #define CUIF_C2U_SPEECH_INTERRUPT_STATUS_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_C2U_SPEECH_INTERRUPT_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_C2U_SPEECH_INTERRUPT_CLEAR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_C2U_SPEECH_INTERRUPT_EN_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_C2U_SPEECH_INTERRUPT_EN_SET_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_C2U_SPEECH_INTERRUPT_EN_CLR_OFFSET (CUIF_C2U_SPEECH + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C Core Offset*/ |
| |
| #if defined(__MD93__) |
| |
| /* U2C Core Offset*/ |
| /* to iA core0 VPE0 */ |
| #define CUIF_U2C_N0 (0x60 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| /* to iA core0 VPE1 */ |
| #define CUIF_U2C_N1 (0x78 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N2 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N3 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| /* to iA core1 VPE1 */ |
| #define CUIF_U2C_N4 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #define CUIF_U2C_WAKEUP (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #elif defined(__MD95__) |
| |
| /* to iA core0 VPE0 */ |
| #define CUIF_U2C_N0 (0x90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| /* to iA core0 VPE1 */ |
| #define CUIF_U2C_N1 (0xa8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N2 (0xc0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N3 (0xd8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| /* to iA core1 VPE0/1 */ |
| #define CUIF_U2C_N4 (0xf0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N5 (0x108 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N6 (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #define CUIF_U2C_WAKEUP (0x138 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #elif defined(__MD97__) || defined(__MD97P__) |
| |
| #define CUIF_U2C_N0 (0xA00 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N1 (0xA18 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N2 (0xA30 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N3 (0xA48 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N4 (0xA60 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N5 (0xA78 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N6 (0xA90 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N7 (0xAA8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N8 (0xAC0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N9 (0xAD8 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N10 (0xAF0 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N11 (0xB08 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N12 (0xB20 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| #define CUIF_U2C_N13 (0xB38 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #define CUIF_U2C_WAKEUP (0x120 + BASE_MADDR_USIP_CROSS_CORE_CTRL) |
| |
| #else |
| #error "not support this arch!!!!" |
| #endif |
| |
| /* U2C N0 */ |
| #define CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N0_INTERRUPT_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N0_INTERRUPT_EN_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N0 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N1 */ |
| #define CUIF_U2C_N1_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N1_INTERRUPT_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N1_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N1_INTERRUPT_EN_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N1_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N1_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N1 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N2 */ |
| #define CUIF_U2C_N2_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N2_INTERRUPT_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N2_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N2_INTERRUPT_EN_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N2_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N2_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N2 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N3 */ |
| #define CUIF_U2C_N3_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N3_INTERRUPT_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N3_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N3_INTERRUPT_EN_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N3_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N3_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N3 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N4 */ |
| #define CUIF_U2C_N4_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N4_INTERRUPT_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N4_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N4_INTERRUPT_EN_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N4_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N4_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N4 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| #if defined(__MD95__) |
| |
| /* U2C N5 */ |
| #define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N6 */ |
| #define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| #elif defined(__MD97__) || defined(__MD97P__) |
| |
| /* U2C N5 */ |
| #define CUIF_U2C_N5_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N5_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N5 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N6 */ |
| #define CUIF_U2C_N6_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N6_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N6 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N7 */ |
| #define CUIF_U2C_N7_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N7_INTERRUPT_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N7_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N7_INTERRUPT_EN_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N7_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N7_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N7 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N8 */ |
| #define CUIF_U2C_N8_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N8_INTERRUPT_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N8_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N8_INTERRUPT_EN_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N8_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N8_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N8 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N9 */ |
| #define CUIF_U2C_N9_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N9_INTERRUPT_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N9_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N9_INTERRUPT_EN_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N9_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N9_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N9 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N10 */ |
| #define CUIF_U2C_N10_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N10_INTERRUPT_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N10_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N10_INTERRUPT_EN_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N10_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N10_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N10 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N11 */ |
| #define CUIF_U2C_N11_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N11_INTERRUPT_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N11_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N11_INTERRUPT_EN_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N11_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N11_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N11 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N12 */ |
| #define CUIF_U2C_N12_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N12_INTERRUPT_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N12_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N12_INTERRUPT_EN_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N12_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N12_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N12 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C N13 */ |
| #define CUIF_U2C_N13_INTERRUPT_STATUS_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_N13_INTERRUPT_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_N13_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_N13_INTERRUPT_EN_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_N13_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_N13_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_N13 + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| /* U2C WAKEUP */ |
| #define CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_STATUS_OFFSET) |
| #define CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_SET_OFFSET) |
| #define CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_CLEAR_OFFSET) |
| #define CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_OFFSET) |
| #define CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_SET_OFFSET) |
| #define CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET (CUIF_U2C_WAKEUP + CUIF_INTERRUPT_EN_CLR_OFFSET) |
| |
| #endif |
| /******************************************************************************* |
| * Macros |
| *******************************************************************************/ |
| |
| /* C2U */ |
| #define CUIF_C2U_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_STATUS_OFFSET)) |
| #define CUIF_C2U_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_SET_OFFSET)) |
| #define CUIF_C2U_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_CLEAR_OFFSET)) |
| #define CUIF_C2U_EN_STATUS_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_OFFSET)) |
| #define CUIF_C2U_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_SET_OFFSET)) |
| #define CUIF_C2U_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_C2U_INNER_INTERRUPT_EN_CLR_OFFSET)) |
| |
| |
| /* U2C */ |
| #define CUIF_U2C_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_STATUS_OFFSET)) |
| #define CUIF_U2C_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_SET_OFFSET)) |
| #define CUIF_U2C_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_CLEAR_OFFSET)) |
| #define CUIF_U2C_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_OFFSET)) |
| #define CUIF_U2C_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_SET_OFFSET)) |
| #define CUIF_U2C_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_N0_INTERRUPT_EN_CLR_OFFSET)) |
| |
| |
| #if defined(__MD97__) || defined(__MD97P__) |
| /* U2C WAKEUP*/ |
| #define CUIF_U2C_WAKEUP_STATUS_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_STATUS_OFFSET)) |
| #define CUIF_U2C_WAKEUP_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_SET_OFFSET)) |
| #define CUIF_U2C_WAKEUP_CLEAR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_CLEAR_OFFSET)) |
| #define CUIF_U2C_WAKEUP_EN_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_OFFSET)) |
| #define CUIF_U2C_WAKEUP_EN_SET_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_SET_OFFSET)) |
| #define CUIF_U2C_WAKEUP_EN_CLR_BASE ((volatile cuif_uint32*)(CUIF_U2C_WAKEUP_INTERRUPT_EN_CLR_OFFSET)) |
| #endif |
| |
| #define CUIF_TRUE KAL_TRUE |
| #define CUIF_FALSE KAL_FALSE |
| |
| |
| /* Read/Write macros */ |
| #define CUIF_REG_READ(addr) *(volatile cuif_uint32*)(addr) |
| #define CUIF_REG_WRITE(addr, value) do{DRV_WriteReg32(addr, value); MO_Sync();}while(0); |
| |
| |
| #define CUIF_NULL NULL |
| #define CUIF_ASSERT(expr, c1, c2, c3) EXT_ASSERT(expr, c1, c2, c3) |
| #define CUIF_GET_RETURN_ADDRESS(a) GET_RETURN_ADDRESS(a) |
| |
| #define CUIF_CLZ(z) __builtin_clz((z)) |
| #define CUIF_GET_LSB(b) (31 - CUIF_CLZ((b) & -(b))) |
| |
| #if defined(__MD93__) || defined(__MD95__) |
| |
| #define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_0_CODE |
| #define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_0_CODE |
| #define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_0_CODE |
| #define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_0_CODE |
| #define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP0_1_CODE |
| |
| #if defined(__MD95__) |
| #define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP1_1_CODE |
| #define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP2_1_CODE |
| #endif |
| |
| #elif defined(__MD97__) || defined(__MD97P__) |
| |
| #define IRQID_CUIF_U2C_IRQ_N0 IRQ_USIP0_CODE |
| #define IRQID_CUIF_U2C_IRQ_N1 IRQ_USIP1_CODE |
| #define IRQID_CUIF_U2C_IRQ_N2 IRQ_USIP2_CODE |
| #define IRQID_CUIF_U2C_IRQ_N3 IRQ_USIP3_CODE |
| #define IRQID_CUIF_U2C_IRQ_N4 IRQ_USIP4_CODE |
| #define IRQID_CUIF_U2C_IRQ_N5 IRQ_USIP5_CODE |
| #define IRQID_CUIF_U2C_IRQ_N6 IRQ_USIP6_CODE |
| #define IRQID_CUIF_U2C_IRQ_N7 IRQ_USIP7_CODE |
| #define IRQID_CUIF_U2C_IRQ_N8 IRQ_USIP8_CODE |
| #define IRQID_CUIF_U2C_IRQ_N9 IRQ_USIP9_CODE |
| #define IRQID_CUIF_U2C_IRQ_N10 IRQ_USIP10_CODE |
| #define IRQID_CUIF_U2C_IRQ_N11 IRQ_USIP11_CODE |
| #define IRQID_CUIF_U2C_IRQ_N12 IRQ_USIP12_CODE |
| #define IRQID_CUIF_U2C_IRQ_N13 IRQ_USIP13_CODE |
| |
| #endif |
| |
| |
| #if defined(__MD93__) |
| #define CUIF_VPE_NUM (4) |
| #elif defined(__MD95__) |
| #define CUIF_VPE_NUM (6) |
| #elif defined(__MD97__) || defined(__MD97P__) |
| #define CUIF_VPE_NUM (12) |
| #endif |
| /* because reg is type of int, reg + 1 = addr + 4 */ |
| #define REG_OFFSET(mID) (mID * 6) |
| |
| #define ARRAY_OFFSET(mID) (mID) |
| |
| |
| /* cuif handler*/ |
| #if !defined(__CUIF_DEBUG__) |
| #define CUIF_HANDLER(nID) \ |
| cuif_InterruptHandlerInternal( \ |
| CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \ |
| CUIF_U2C_EN_BASE + REG_OFFSET(nID), \ |
| CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \ |
| cuif_isr_handler[ARRAY_OFFSET(nID)], \ |
| cuif_isr_eoi[ARRAY_OFFSET(nID)]) |
| #else /* __CUIF_DEBUG__ */ |
| #define CUIF_HANDLER(nID) \ |
| cuif_InterruptHandlerInternal( \ |
| CUIF_U2C_STATUS_BASE + REG_OFFSET(nID), \ |
| CUIF_U2C_EN_BASE + REG_OFFSET(nID), \ |
| CUIF_U2C_CLEAR_BASE + REG_OFFSET(nID), \ |
| cuif_isr_handler[ARRAY_OFFSET(nID)], \ |
| cuif_isr_eoi[ARRAY_OFFSET(nID)], \ |
| nID) |
| #endif /* __CUIF_DEBUG__ */ |
| |
| |
| |
| /* cuif overflow debug info */ |
| typedef struct{ |
| cuif_uint32 receiver; /**< The mcu receiver: 0~4 means n0~n4 */ |
| cuif_uint32 interrupt_bit; /**< The overflow bit */ |
| cuif_uint32 status_addr; /**< The addr of the status register */ |
| cuif_uint32 current_status;/**< The current value of the status register */ |
| cuif_uint32 caller; /**< The caller address */ |
| cuif_uint32 time; |
| }CUIF_OverFlowRecord; |
| |
| /** |
| * CUIF Init function |
| */ |
| extern void CUIF_Init(); |
| |
| |
| /******************************************************************************* |
| * Debug feature |
| *******************************************************************************/ |
| #if defined(__CUIF_DEBUG__) |
| |
| #if __CUIF_MD32S_CORE__ |
| /* MD32 side */ |
| #define CUIF_DEBUG_API_RECORD_SIZE 8 |
| #define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 8 |
| |
| #else /* __CUIF_MD32S_CORE__ */ |
| |
| #define CUIF_DEBUG_API_RECORD_SIZE 16 |
| #define CUIF_DEBUG_ISR_HANDLE_CODE_SIZE 16 |
| |
| #endif /* __CUIF_MD32S_CORE__ */ |
| |
| typedef struct{ |
| cuif_uint32 time; |
| cuif_uint32 code; |
| }CUIF_DebugISRRecord; |
| |
| /** The Ring Buffer */ |
| typedef struct{ |
| CUIF_DebugISRRecord records[CUIF_DEBUG_ISR_HANDLE_CODE_SIZE]; |
| cuif_uint32 top_index; |
| }CUIF_DebugISRCodeList; |
| |
| typedef struct{ |
| cuif_uint32 time; |
| cuif_uint32 status; |
| cuif_uint32 set_addr; /**< The control register address */ |
| cuif_uint32 set_value; /**< The writing value for the control regsiters */ |
| cuif_uint32 caller; /**< The caller address */ |
| }CUIF_DebugRecord; |
| |
| /** The Ring Buffer */ |
| typedef struct{ |
| CUIF_DebugRecord records[CUIF_DEBUG_API_RECORD_SIZE]; |
| kal_atomic_uint32 top_index; |
| }CUIF_DebugRecordList; |
| |
| void cuif_DebugAddRecord(cuif_uint32 status, |
| volatile cuif_uint32* set_addr, |
| cuif_uint32 set_value, |
| cuif_uint32 caller); |
| |
| void cuif_DebugAddISRHandleCode(cuif_uint32 code, CUIF_MCU_INT nID); |
| |
| #endif /* __CUIF_DEBUG__ */ |
| |
| |
| |
| #if defined(__CUIF_DRV_TEST__) |
| |
| |
| //#include "dsp_header_define_cuif_inner_brp.h" |
| #define CUIF_INNER_BRP_BASE ((kal_uint32)(0xA0840000)) // Bank A: L1 normal access. |
| #define CUIF_SYNC_ADDR_USIP0 ((CUIF_INNER_BRP_BASE) + 0x2000) |
| |
| #if defined(__MD97__) || defined(__MD97P__) |
| //#include "dsp_header_define_cuif_speech.h" |
| #define CUIF_SPEECH_BASE ((kal_uint32)(0xA0944700)) |
| #define CUIF_SYNC_ADDR_USIP1 ((CUIF_SPEECH_BASE) + 0x2000) |
| #else |
| #include "dsp_header_define_cuif_fec_wbrp.h" |
| #define CUIF_SYNC_ADDR_USIP1 ((CUIF_FEC_WBRP_BASE) + 0x2000) |
| #endif |
| |
| #define INT INVALID_INT |
| #define UINT INVALID_UINT |
| #define INT32 INVALID_INT32 |
| #define UINT32 INVALID_UINT32 |
| |
| #define CUIF_DRV_TEST_ASSERT_EQ(a, b) \ |
| do{ \ |
| if((a) != (b)){ \ |
| dbg_print("Error: %s: %d - %d != %d\n", __FILE__, __LINE__, (a), (b)); \ |
| while(1); \ |
| } \ |
| }while(0) |
| |
| extern cuif_uint32 cuif_c2u_int_source_num[CUIF_ENUM_ALL_USIP_INT_NUM]; |
| extern cuif_uint32 cuif_u2c_int_source_num[CUIF_ENUM_ALL_MCU_INT_NUM - 1]; |
| |
| extern void CUIF_DriverTestISR_N0(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N1(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N2(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N3(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N4(CUIF_Mask_t* mask); |
| #if defined(__MD97__) || defined(__MD97P__) |
| extern void CUIF_DriverTestISR_N5(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N6(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N7(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N8(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N9(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N10(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N11(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N12(CUIF_Mask_t* mask); |
| extern void CUIF_DriverTestISR_N13(CUIF_Mask_t* mask); |
| #endif |
| |
| #endif /* __CUIF_DRV_TEST__ */ |
| |
| |
| #endif /* __DRV_CUIF_H__ */ |