| /******************************************************************************* |
| * Modification Notice: |
| * -------------------------- |
| * This software is modified by MediaTek Inc. and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *******************************************************************************/ |
| |
| |
| /***************************************************************************** |
| * |
| * Filename: |
| * --------- |
| * mml1_d_gdma.h |
| * |
| * Project: |
| * -------- |
| * MT6297 Project |
| * |
| * Description: |
| * ------------ |
| * MML1 D_GDMA Common API |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
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| *------------------------------------------------------------------------------ |
| * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| |
| /*===============================================================================*/ |
| |
| #ifndef _MML1_D_GDMA_H_ |
| #define _MML1_D_GDMA_H_ |
| |
| #include "kal_general_types.h" |
| #include "mml1_d_gdma_reg.h" |
| |
| /* chip option */ |
| #define _MM_D_GDMA_CHIP_ID_APOLLO 0x00000001 |
| #define _MM_D_GDMA_CHIP_ID_PETRUS 0x00000002 |
| #define _MM_D_GDMA_CHIP_ID_MERCURY 0x00000004 |
| #define _MM_D_GDMA_CHIP_ID_MARGAUX 0x00000008 |
| #define _MM_D_GDMA_CHIP_ID_MOUTON 0x00000010 |
| #define _MM_D_GDMA_CHIP_ID_COLGIN 0x00000020 |
| #define _MM_D_GDMA_CHIP_ID_PALMER 0x00000040 |
| #define _MM_D_GDMA_CHIP_ID_PETRUS_P 0x00000080 |
| #define _MM_D_GDMA_CHIP_ID_MONTROSE 0x00000100 |
| |
| |
| |
| #ifndef _MM_D_GDMA_CHIP_ID |
| /* ------------------------------------------------------------------- */ |
| /* Gen97 */ |
| /* ------------------------------------------------------------------- */ |
| #if defined(MT6297) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_APOLLO |
| #elif defined(MT6893) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_PETRUS_P |
| #elif defined(MT6885) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_PETRUS |
| #elif defined(__MD97P__) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_MERCURY |
| #elif defined(MT6873) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_MARGAUX |
| #elif defined(MT6853) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_MOUTON |
| #elif defined(CHIP10992) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_COLGIN |
| #elif defined(MT6833) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_PALMER |
| #elif defined(MT6877) |
| #define _MM_D_GDMA_CHIP_ID _MM_D_GDMA_CHIP_ID_MONTROSE |
| #else |
| #error "please check chip version" |
| #endif |
| #endif //#ifndef _MM_D_GDMA_CHIP_ID |
| |
| #define _MM_D_GDMA_CHIP_MT6885_AND_LATTER_VERSION ( _MM_D_GDMA_CHIP_ID_PETRUS | _MM_D_GDMA_CHIP_ID_MERCURY | _MM_D_GDMA_CHIP_ID_MARGAUX | _MM_D_GDMA_CHIP_ID_MOUTON | _MM_D_GDMA_CHIP_ID_COLGIN | _MM_D_GDMA_CHIP_ID_PALMER | _MM_D_GDMA_CHIP_ID_PETRUS_P|_MM_D_GDMA_CHIP_ID_MONTROSE) |
| #define IS_MM_D_GDMA_CHIP_MT6885_AND_LATTER_VERSION ( _MM_D_GDMA_CHIP_ID & _MM_D_GDMA_CHIP_MT6885_AND_LATTER_VERSION ) |
| |
| //define |
| #define MML1_D_GDMA_CH_MASK(ch_id) (1<<((ch_id)%32)) |
| |
| //enum |
| #if defined(MT6297) |
| typedef enum |
| { |
| MML1_D_GDMA_RXDFE_0_H_0 = 0 , |
| MML1_D_GDMA_RXDFE_0_H_1 = 1 , |
| MML1_D_GDMA_RXDFE_0_H_2 = 2 , |
| MML1_D_GDMA_RXDFE_0_H_3 = 3 , |
| MML1_D_GDMA_RXAGC_0_H_4 = 4 , |
| MML1_D_GDMA_RXAGC_0_H_5 = 5 , |
| MML1_D_GDMA_RXAGC_0_H_6 = 6 , |
| MML1_D_GDMA_RXAGC_0_H_7 = 7 , |
| MML1_D_GDMA_RXAGC_0_H_8 = 8 , |
| MML1_D_GDMA_RXAGC_0_L_0 = 9 , |
| MML1_D_GDMA_RXAGC_0_L_1 = 10 , |
| MML1_D_GDMA_RXAGC_0_L_2 = 11 , |
| MML1_D_GDMA_RXAGC_0_L_3 = 12 , |
| MML1_D_GDMA_RXAGC_0_L_4 = 13 , |
| MML1_D_GDMA_RXAGC_0_L_5 = 14 , |
| MML1_D_GDMA_RXAGC_0_L_6 = 15 , |
| MML1_D_GDMA_RXAGC_0_L_7 = 16 , |
| MML1_D_GDMA_RXAGC_0_L_8 = 17 , |
| MML1_D_GDMA_RXAGC_0_L_9 = 18 , |
| MML1_D_GDMA_RXAGC_0_L_10 = 19 , |
| MML1_D_GDMA_RXAGC_0_L_11 = 20 , |
| MML1_D_GDMA_RXAGC_0_L_12 = 21 , |
| MML1_D_GDMA_RXAGC_0_L_13 = 22 , |
| MML1_D_GDMA_RXAGC_0_L_14 = 23 , |
| MML1_D_GDMA_RXAGC_0_L_15 = 24 , |
| MML1_D_GDMA_RXAGC_0_L_16 = 25 , |
| MML1_D_GDMA_RXAGC_0_L_17 = 26 , |
| MML1_D_GDMA_RXAGC_0_L_18 = 27 , |
| MML1_D_GDMA_RXAGC_0_L_19 = 28 , |
| MML1_D_GDMA_RXAGC_0_L_20 = 29 , |
| MML1_D_GDMA_RXAGC_0_L_21 = 30 , |
| MML1_D_GDMA_RXAGC_0_L_22 = 31 , |
| MML1_D_GDMA_RXAGC_0_L_23 = 32 , |
| MML1_D_GDMA_RXAGC_0_L_24 = 33 , |
| MML1_D_GDMA_RXAGC_0_L_25 = 34 , |
| MML1_D_GDMA_RXAGC_0_L_26 = 35 , |
| MML1_D_GDMA_RXAGC_0_L_27 = 36 , |
| MML1_D_GDMA_RXAGC_0_L_28 = 37 , |
| MML1_D_GDMA_RXAGC_0_L_29 = 38 , |
| MML1_D_GDMA_RXAGC_0_L_30 = 39 , |
| MML1_D_GDMA_RXAGC_0_L_31 = 40 , |
| MML1_D_GDMA_L1RFD_0_L_32 = 41 , |
| MML1_D_GDMA_L1RFD_0_L_33 = 42 , |
| MML1_D_GDMA_L1RFD_0_L_34 = 43 , |
| MML1_D_GDMA_L1RFD_0_L_35 = 44 , |
| MML1_D_GDMA_L1RFD_0_L_36 = 45 , |
| MML1_D_GDMA_L1RFD_0_L_37 = 46 , |
| MML1_D_GDMA_L1RFD_0_L_38 = 47 , |
| MML1_D_GDMA_L1RFD_0_L_39 = 48 , |
| MML1_D_GDMA_RXAGC_0_L_40 = 49 , |
| MML1_D_GDMA_RXAGC_0_L_41 = 50 , |
| MML1_D_GDMA_RXAGC_0_L_42 = 51 , |
| MML1_D_GDMA_RXAGC_0_L_43 = 52 , |
| MML1_D_GDMA_RXAGC_0_L_44 = 53 , |
| MML1_D_GDMA_RXAGC_0_L_45 = 54 , |
| MML1_D_GDMA_RXAGC_0_L_46 = 55 , |
| MML1_D_GDMA_RXAGC_0_L_47 = 56 , |
| MML1_D_GDMA_RXAGC_0_L_48 = 57 , |
| MML1_D_GDMA_RXAGC_0_L_49 = 58 , |
| MML1_D_GDMA_RXAGC_1_H_0 = 59 , |
| MML1_D_GDMA_RXAGC_1_H_1 = 60 , |
| MML1_D_GDMA_TXTPC_1_H_5 = 61 , |
| MML1_D_GDMA_RXAGC_1_L_0 = 62 , |
| MML1_D_GDMA_RXAGC_1_L_1 = 63 , |
| MML1_D_GDMA_RXAGC_1_L_2 = 64 , |
| MML1_D_GDMA_RXAGC_1_L_3 = 65 , |
| MML1_D_GDMA_RXAGC_1_L_4 = 66 , |
| MML1_D_GDMA_RXAGC_1_L_5 = 67 , |
| MML1_D_GDMA_RXAGC_1_L_6 = 68 , |
| MML1_D_GDMA_RXAGC_1_L_7 = 69 , |
| MML1_D_GDMA_RXAGC_1_L_8 = 70 , |
| MML1_D_GDMA_RXAGC_1_L_9 = 71 , |
| MML1_D_GDMA_RXAGC_1_L_10 = 72 , |
| MML1_D_GDMA_RXAGC_1_L_11 = 73 , |
| MML1_D_GDMA_RXAGC_1_L_12 = 74 , |
| MML1_D_GDMA_RXAGC_1_L_13 = 75 , |
| MML1_D_GDMA_RXAGC_1_L_14 = 76 , |
| MML1_D_GDMA_RXAGC_1_L_15 = 77 , |
| MML1_D_GDMA_RXAGC_1_L_16 = 78 , |
| MML1_D_GDMA_RXAGC_1_L_17 = 79 , |
| MML1_D_GDMA_RXAGC_1_L_18 = 80 , |
| MML1_D_GDMA_RXAGC_1_L_19 = 81 , |
| MML1_D_GDMA_RXAGC_1_L_20 = 82 , |
| MML1_D_GDMA_RXAGC_1_L_21 = 83 , |
| MML1_D_GDMA_RXAGC_1_L_22 = 84 , |
| MML1_D_GDMA_RXAGC_1_L_23 = 85 , |
| MML1_D_GDMA_RXAGC_1_L_24 = 86 , |
| MML1_D_GDMA_RXAGC_1_L_25 = 87 , |
| MML1_D_GDMA_RXAGC_1_L_26 = 88 , |
| MML1_D_GDMA_RXAGC_1_L_27 = 89 , |
| MML1_D_GDMA_RXAGC_1_L_28 = 90 , |
| MML1_D_GDMA_RXAGC_1_L_29 = 91 , |
| MML1_D_GDMA_RXAGC_1_L_30 = 92 , |
| MML1_D_GDMA_RXAGC_1_L_31 = 93 , |
| MML1_D_GDMA_RXAGC_1_L_32 = 94 , |
| MML1_D_GDMA_RXAGC_1_L_33 = 95 , |
| MML1_D_GDMA_RXAGC_1_L_34 = 96 , |
| MML1_D_GDMA_RXAGC_1_L_35 = 97 , |
| MML1_D_GDMA_RXAGC_1_L_36 = 98 , |
| MML1_D_GDMA_RXAGC_1_L_37 = 99, |
| MML1_D_GDMA_RXAGC_1_L_38 = 100, |
| MML1_D_GDMA_RXAGC_1_L_39 = 101, |
| MML1_D_GDMA_RXAGC_1_L_40 = 102, |
| MML1_D_GDMA_RXAGC_1_L_41 = 103, |
| MML1_D_GDMA_RXAGC_1_L_42 = 104, |
| MML1_D_GDMA_RXAGC_1_L_43 = 105, |
| MML1_D_GDMA_RXAGC_1_L_44 = 106, |
| MML1_D_GDMA_RXAGC_1_L_45 = 107, |
| MML1_D_GDMA_RXAGC_1_L_46 = 108, |
| MML1_D_GDMA_RXAGC_1_L_47 = 109, |
| MML1_D_GDMA_RXAGC_1_L_48 = 110, |
| MML1_D_GDMA_RXAGC_1_L_49 = 111, |
| MML1_D_GDMA_RXAGC_1_L_50 = 112, |
| MML1_D_GDMA_RXAGC_1_L_51 = 113, |
| MML1_D_GDMA_L1RFD_1_L_52 = 114, |
| MML1_D_GDMA_L1RFD_1_L_53 = 115, |
| MML1_D_GDMA_L1RFD_1_L_54 = 116, |
| MML1_D_GDMA_L1RFD_1_L_55 = 117, |
| MML1_D_GDMA_L1RFD_1_L_56 = 118, |
| MML1_D_GDMA_L1RFD_1_L_57 = 119, |
| MML1_D_GDMA_L1RFD_1_L_58 = 120, |
| MML1_D_GDMA_L1RFD_1_L_59 = 121, |
| MML1_D_GDMA_L1RFD_1_L_60 = 122, |
| MML1_D_GDMA_L1RFD_1_L_61 = 123, |
| MML1_D_GDMA_L1RFD_1_L_62 = 124, |
| MML1_D_GDMA_L1RFD_1_L_63 = 125, |
| MML1_D_GDMA_TXTPC_2_H_0 = 126, |
| MML1_D_GDMA_TXTPC_2_L_0 = 127, |
| MML1_D_GDMA_TXDFE_2_L_1 = 128, |
| MML1_D_GDMA_TXDFE_2_L_2 = 129, |
| MML1_D_GDMA_TXDFE_2_L_3 = 130, |
| MML1_D_GDMA_TXDFE_2_L_4 = 131, |
| MML1_D_GDMA_TXDFE_2_L_5 = 132, |
| MML1_D_GDMA_TXTPC_2_L_6 = 133, |
| MML1_D_GDMA_TXTPC_2_L_7 = 134, |
| MML1_D_GDMA_TXTPC_2_L_8 = 135, |
| MML1_D_GDMA_TXTPC_2_L_9 = 136, |
| MML1_D_GDMA_TXTPC_3_H_0 = 137, |
| MML1_D_GDMA_TXTPC_3_H_1 = 138, |
| MML1_D_GDMA_TXTPC_3_H_2 = 139, |
| MML1_D_GDMA_RXDFE_3_L_0 = 140, |
| MML1_D_GDMA_RXDFE_3_L_1 = 141, |
| MML1_D_GDMA_TXTPC_4_H_0 = 142, |
| MML1_D_GDMA_TXTPC_4_L_0 = 143, |
| MML1_D_GDMA_TXTPC_4_L_1 = 144, |
| MML1_D_GDMA_TXDFE_4_L_2 = 145, |
| MML1_D_GDMA_TXDFE_4_L_3 = 146, |
| MML1_D_GDMA_TXDFE_4_L_4 = 147, |
| MML1_D_GDMA_TXDFE_4_L_5 = 148, |
| MML1_D_GDMA_TXDFE_4_L_6 = 149, |
| MML1_D_GDMA_TXDFE_4_L_7 = 150, |
| MML1_D_GDMA_TXDFE_4_L_8 = 151, |
| MML1_D_GDMA_TXDFE_4_L_9 = 152, |
| MML1_D_GDMA_TXDFE_4_L_10 = 153, |
| MML1_D_GDMA_TXDFE_4_L_11 = 154, |
| MML1_D_GDMA_TXDFE_4_L_12 = 155, |
| MML1_D_GDMA_TXDFE_4_L_13 = 156, |
| MML1_D_GDMA_TXET_4_L_14 = 157, |
| MML1_D_GDMA_TXET_4_L_15 = 158, |
| MML1_D_GDMA_TXET_4_L_16 = 159, |
| MML1_D_GDMA_TXET_4_L_17 = 160, |
| MML1_D_GDMA_TXET_4_L_18 = 161, |
| MML1_D_GDMA_TXET_4_L_19 = 162, |
| MML1_D_GDMA_TXKGC_4_L_20 = 163, |
| MML1_D_GDMA_RXAGC_5_H_0 = 164, |
| MML1_D_GDMA_RXDFE_5_H_1 = 165, |
| MML1_D_GDMA_RXDFE_5_H_2 = 166, |
| MML1_D_GDMA_RXDFE_5_H_3 = 167, |
| MML1_D_GDMA_RXDFE_5_H_4 = 168, |
| MML1_D_GDMA_RXDFE_5_H_5 = 169, |
| MML1_D_GDMA_RXDFE_5_H_6 = 170, |
| MML1_D_GDMA_RXDFE_5_H_7 = 171, |
| MML1_D_GDMA_RXDFE_5_H_8 = 172, |
| MML1_D_GDMA_RXDFE_5_H_9 = 173, |
| MML1_D_GDMA_RXDFE_5_H_10 = 174, |
| MML1_D_GDMA_RXDFE_5_H_11 = 175, |
| MML1_D_GDMA_RXDFE_5_H_12 = 176, |
| MML1_D_GDMA_RXDFE_5_H_13 = 177, |
| MML1_D_GDMA_RXDFE_5_H_14 = 178, |
| MML1_D_GDMA_RXDFE_5_H_15 = 179, |
| MML1_D_GDMA_RXDFE_5_H_16 = 180, |
| MML1_D_GDMA_RXDFE_5_H_17 = 181, |
| MML1_D_GDMA_RXDFE_5_H_18 = 182, |
| MML1_D_GDMA_RXDFE_5_H_19 = 183, |
| MML1_D_GDMA_RXDFE_5_H_20 = 184, |
| MML1_D_GDMA_RXDFE_5_H_21 = 185, |
| MML1_D_GDMA_RXDFE_5_H_22 = 186, |
| MML1_D_GDMA_RXDFE_5_H_23 = 187, |
| MML1_D_GDMA_RXDFE_5_H_24 = 188, |
| MML1_D_GDMA_RXDFE_5_H_25 = 189, |
| MML1_D_GDMA_RXDFE_5_H_26 = 190, |
| MML1_D_GDMA_RXDFE_5_H_27 = 191, |
| MML1_D_GDMA_RXDFE_5_H_28 = 192, |
| MML1_D_GDMA_RXDFE_5_H_29 = 193, |
| MML1_D_GDMA_RXDFE_5_H_30 = 194, |
| MML1_D_GDMA_RXDFE_5_H_31 = 195, |
| MML1_D_GDMA_RXDFE_5_H_32 = 196, |
| MML1_D_GDMA_RXDFE_5_H_33 = 197, |
| MML1_D_GDMA_RXDFE_5_H_34 = 198, |
| MML1_D_GDMA_RXDFE_5_H_35 = 199, |
| MML1_D_GDMA_RXDFE_5_H_36 = 200, |
| MML1_D_GDMA_RXDFE_5_H_37 = 201, |
| MML1_D_GDMA_RXDFE_5_H_38 = 202, |
| MML1_D_GDMA_RXDFE_5_H_39 = 203, |
| MML1_D_GDMA_RXDFE_5_H_40 = 204, |
| MML1_D_GDMA_RXDFE_5_H_41 = 205, |
| MML1_D_GDMA_RXDFE_5_H_42 = 206, |
| MML1_D_GDMA_RXDFE_5_H_43 = 207, |
| MML1_D_GDMA_RXDFE_5_H_44 = 208, |
| MML1_D_GDMA_RXDFE_5_H_45 = 209, |
| MML1_D_GDMA_RXDFE_5_H_46 = 210, |
| MML1_D_GDMA_RXDFE_5_H_47 = 211, |
| MML1_D_GDMA_RXDFE_5_H_48 = 212, |
| MML1_D_GDMA_RXDFE_5_H_49 = 213, |
| MML1_D_GDMA_RXDFE_5_H_50 = 214, |
| MML1_D_GDMA_RXDFE_5_H_51 = 215, |
| MML1_D_GDMA_RXDFE_5_H_52 = 216, |
| MML1_D_GDMA_RXDFE_5_H_53 = 217, |
| MML1_D_GDMA_RXDFE_5_H_54 = 218, |
| MML1_D_GDMA_RXDFE_5_H_55 = 219, |
| MML1_D_GDMA_RXDFE_5_H_56 = 220, |
| MML1_D_GDMA_RXDFE_5_H_57 = 221, |
| MML1_D_GDMA_RXDFE_5_H_58 = 222, |
| MML1_D_GDMA_RXDFE_5_H_59 = 223, |
| MML1_D_GDMA_RXDFE_5_H_60 = 224, |
| MML1_D_GDMA_RXDFE_5_H_61 = 225, |
| MML1_D_GDMA_RXDFE_5_H_62 = 226, |
| MML1_D_GDMA_RXDFE_5_H_63 = 227, |
| MML1_D_GDMA_RXDFE_5_H_64 = 228, |
| MML1_D_GDMA_RXAGC_5_H_65 = 229, |
| MML1_D_GDMA_TXTPC_5_L_0 = 230, |
| MML1_D_GDMA_TXTPC_5_L_1 = 231, |
| MML1_D_GDMA_TXTPC_5_L_2 = 232, |
| MML1_D_GDMA_RXAGC_5_L_3 = 233, |
| MML1_D_GDMA_RXAGC_5_L_4 = 234, |
| MML1_D_GDMA_RXAGC_5_L_5 = 235, |
| MML1_D_GDMA_RXAGC_5_L_6 = 236, |
| MML1_D_GDMA_ID_SIZE = 237 |
| }MML1_D_GDMA_ID_E; |
| #elif IS_MM_D_GDMA_CHIP_MT6885_AND_LATTER_VERSION |
| typedef enum |
| { |
| MML1_D_GDMA_RXDFE_0_H_0 = 0 , |
| MML1_D_GDMA_RXDFE_0_H_1 = 1 , |
| MML1_D_GDMA_RXDFE_0_H_2 = 2 , |
| MML1_D_GDMA_RXDFE_0_H_3 = 3 , |
| MML1_D_GDMA_RXDFE_0_H_4 = 4 , |
| MML1_D_GDMA_RXDFE_0_H_5 = 5 , |
| MML1_D_GDMA_RXDFE_0_H_6 = 6 , |
| MML1_D_GDMA_RXDFE_0_H_7 = 7 , |
| MML1_D_GDMA_RXAGC_0_H_8 = 8 , |
| MML1_D_GDMA_RXAGC_0_H_9 = 9 , |
| MML1_D_GDMA_RXAGC_0_H_10 = 10 , |
| MML1_D_GDMA_RXAGC_0_H_11 = 11 , |
| MML1_D_GDMA_RXAGC_0_H_12 = 12 , |
| MML1_D_GDMA_RXAGC_0_H_13 = 13 , |
| MML1_D_GDMA_RXAGC_0_H_14 = 14 , |
| MML1_D_GDMA_RXAGC_0_H_15 = 15 , |
| MML1_D_GDMA_RXAGC_0_L_0 = 16 , |
| MML1_D_GDMA_RXAGC_0_L_1 = 17 , |
| MML1_D_GDMA_RXAGC_0_L_2 = 18 , |
| MML1_D_GDMA_RXAGC_0_L_3 = 19 , |
| MML1_D_GDMA_RXAGC_0_L_4 = 20 , |
| MML1_D_GDMA_RXAGC_0_L_5 = 21 , |
| MML1_D_GDMA_RXAGC_0_L_6 = 22 , |
| MML1_D_GDMA_RXAGC_0_L_7 = 23 , |
| MML1_D_GDMA_RXAGC_0_L_8 = 24 , |
| MML1_D_GDMA_RXAGC_0_L_9 = 25 , |
| MML1_D_GDMA_RXAGC_0_L_10 = 26 , |
| MML1_D_GDMA_RXAGC_0_L_11 = 27 , |
| MML1_D_GDMA_RXAGC_0_L_12 = 28 , |
| MML1_D_GDMA_RXAGC_0_L_13 = 29 , |
| MML1_D_GDMA_RXAGC_0_L_14 = 30 , |
| MML1_D_GDMA_RXAGC_0_L_15 = 31 , |
| MML1_D_GDMA_RXAGC_0_L_16 = 32 , |
| MML1_D_GDMA_RXAGC_0_L_17 = 33 , |
| MML1_D_GDMA_RXAGC_0_L_18 = 34 , |
| MML1_D_GDMA_RXAGC_0_L_19 = 35 , |
| MML1_D_GDMA_RXAGC_0_L_20 = 36 , |
| MML1_D_GDMA_RXAGC_0_L_21 = 37 , |
| MML1_D_GDMA_RXAGC_0_L_22 = 38 , |
| MML1_D_GDMA_RXAGC_0_L_23 = 39 , |
| MML1_D_GDMA_RXAGC_0_L_24 = 40 , |
| MML1_D_GDMA_RXAGC_0_L_25 = 41 , |
| MML1_D_GDMA_RXAGC_0_L_26 = 42 , |
| MML1_D_GDMA_RXAGC_0_L_27 = 43 , |
| MML1_D_GDMA_RXAGC_0_L_28 = 44 , |
| MML1_D_GDMA_RXAGC_0_L_29 = 45 , |
| MML1_D_GDMA_RXAGC_0_L_30 = 46 , |
| MML1_D_GDMA_RXAGC_0_L_31 = 47 , |
| MML1_D_GDMA_L1RFD_0_L_32 = 48 , |
| MML1_D_GDMA_L1RFD_0_L_33 = 49 , |
| MML1_D_GDMA_L1RFD_0_L_34 = 50 , |
| MML1_D_GDMA_L1RFD_0_L_35 = 51 , |
| MML1_D_GDMA_L1RFD_0_L_36 = 52 , |
| MML1_D_GDMA_L1RFD_0_L_37 = 53 , |
| MML1_D_GDMA_L1RFD_0_L_38 = 54 , |
| MML1_D_GDMA_L1RFD_0_L_39 = 55 , |
| MML1_D_GDMA_RXAGC_0_L_40 = 56 , |
| MML1_D_GDMA_RXAGC_0_L_41 = 57 , |
| MML1_D_GDMA_RXAGC_0_L_42 = 58 , |
| MML1_D_GDMA_RXAGC_0_L_43 = 59 , |
| MML1_D_GDMA_RXAGC_0_L_44 = 60 , |
| MML1_D_GDMA_RXAGC_0_L_45 = 61 , |
| MML1_D_GDMA_RXAGC_0_L_46 = 62 , |
| MML1_D_GDMA_RXAGC_0_L_47 = 63 , |
| MML1_D_GDMA_RXAGC_0_L_48 = 64 , |
| MML1_D_GDMA_RXAGC_0_L_49 = 65 , |
| MML1_D_GDMA_RXAGC_1_H_0 = 66 , |
| MML1_D_GDMA_RXAGC_1_H_1 = 67 , |
| MML1_D_GDMA_RXAGC_1_H_2 = 68 , |
| MML1_D_GDMA_RXAGC_1_H_3 = 69 , |
| MML1_D_GDMA_RXAGC_1_H_4 = 70 , |
| MML1_D_GDMA_RXAGC_1_H_5 = 71 , |
| MML1_D_GDMA_TXTPC_1_H_6 = 72 , |
| MML1_D_GDMA_RXAGC_1_H_7 = 73 , |
| MML1_D_GDMA_RXAGC_1_H_8 = 74 , |
| MML1_D_GDMA_RXAGC_1_L_0 = 75 , |
| MML1_D_GDMA_RXAGC_1_L_1 = 76 , |
| MML1_D_GDMA_RXAGC_1_L_2 = 77 , |
| MML1_D_GDMA_RXAGC_1_L_3 = 78 , |
| MML1_D_GDMA_RXAGC_1_L_4 = 79 , |
| MML1_D_GDMA_RXAGC_1_L_5 = 80 , |
| MML1_D_GDMA_RXAGC_1_L_6 = 81 , |
| MML1_D_GDMA_RXAGC_1_L_7 = 82 , |
| MML1_D_GDMA_RXAGC_1_L_8 = 83 , |
| MML1_D_GDMA_RXAGC_1_L_9 = 84 , |
| MML1_D_GDMA_RXAGC_1_L_10 = 85 , |
| MML1_D_GDMA_RXAGC_1_L_11 = 86 , |
| MML1_D_GDMA_RXAGC_1_L_12 = 87 , |
| MML1_D_GDMA_RXAGC_1_L_13 = 88 , |
| MML1_D_GDMA_RXAGC_1_L_14 = 89 , |
| MML1_D_GDMA_RXAGC_1_L_15 = 90 , |
| MML1_D_GDMA_RXAGC_1_L_16 = 91 , |
| MML1_D_GDMA_RXAGC_1_L_17 = 92 , |
| MML1_D_GDMA_RXAGC_1_L_18 = 93 , |
| MML1_D_GDMA_RXAGC_1_L_19 = 94 , |
| MML1_D_GDMA_RXAGC_1_L_20 = 95 , |
| MML1_D_GDMA_RXAGC_1_L_21 = 96 , |
| MML1_D_GDMA_RXAGC_1_L_22 = 97 , |
| MML1_D_GDMA_RXAGC_1_L_23 = 98 , |
| MML1_D_GDMA_RXAGC_1_L_24 = 99 , |
| MML1_D_GDMA_RXAGC_1_L_25 = 100 , |
| MML1_D_GDMA_RXAGC_1_L_26 = 101 , |
| MML1_D_GDMA_RXAGC_1_L_27 = 102, |
| MML1_D_GDMA_RXAGC_1_L_28 = 103, |
| MML1_D_GDMA_RXAGC_1_L_29 = 104, |
| MML1_D_GDMA_RXAGC_1_L_30 = 105, |
| MML1_D_GDMA_RXAGC_1_L_31 = 106, |
| MML1_D_GDMA_RXAGC_1_L_32 = 107, |
| MML1_D_GDMA_RXAGC_1_L_33 = 108, |
| MML1_D_GDMA_RXAGC_1_L_34 = 109, |
| MML1_D_GDMA_RXAGC_1_L_35 = 110, |
| MML1_D_GDMA_RXAGC_1_L_36 = 111, |
| MML1_D_GDMA_RXAGC_1_L_37 = 112, |
| MML1_D_GDMA_RXAGC_1_L_38 = 113, |
| MML1_D_GDMA_RXAGC_1_L_39 = 114, |
| MML1_D_GDMA_RXAGC_1_L_40 = 115, |
| MML1_D_GDMA_RXAGC_1_L_41 = 116, |
| MML1_D_GDMA_RXAGC_1_L_42 = 117, |
| MML1_D_GDMA_RXAGC_1_L_43 = 118, |
| MML1_D_GDMA_RXAGC_1_L_44 = 119, |
| MML1_D_GDMA_RXAGC_1_L_45 = 120, |
| MML1_D_GDMA_RXAGC_1_L_46 = 121, |
| MML1_D_GDMA_RXAGC_1_L_47 = 122, |
| MML1_D_GDMA_RXAGC_1_L_48 = 123, |
| MML1_D_GDMA_RXAGC_1_L_49 = 124, |
| MML1_D_GDMA_RXAGC_1_L_50 = 125, |
| MML1_D_GDMA_RXAGC_1_L_51 = 126, |
| MML1_D_GDMA_L1RFD_1_L_52 = 127, |
| MML1_D_GDMA_L1RFD_1_L_53 = 128, |
| MML1_D_GDMA_L1RFD_1_L_54 = 129, |
| MML1_D_GDMA_L1RFD_1_L_55 = 130, |
| MML1_D_GDMA_L1RFD_1_L_56 = 131, |
| MML1_D_GDMA_L1RFD_1_L_57 = 132, |
| MML1_D_GDMA_L1RFD_1_L_58 = 133, |
| MML1_D_GDMA_L1RFD_1_L_59 = 134, |
| MML1_D_GDMA_L1RFD_1_L_60 = 135, |
| MML1_D_GDMA_L1RFD_1_L_61 = 136, |
| MML1_D_GDMA_L1RFD_1_L_62 = 137, |
| MML1_D_GDMA_L1RFD_1_L_63 = 138, |
| MML1_D_GDMA_TXTPC_2_H_0 = 139, |
| MML1_D_GDMA_TXTPC_2_H_1 = 140, |
| MML1_D_GDMA_TXTPC_2_L_0 = 141, |
| MML1_D_GDMA_TXDFE_2_L_1 = 142, |
| MML1_D_GDMA_TXDFE_2_L_2 = 143, |
| MML1_D_GDMA_TXDFE_2_L_3 = 144, |
| MML1_D_GDMA_TXDFE_2_L_4 = 145, |
| MML1_D_GDMA_TXDFE_2_L_5 = 146, |
| MML1_D_GDMA_TXTPC_2_L_6 = 147, |
| MML1_D_GDMA_TXTPC_2_L_7 = 148, |
| MML1_D_GDMA_TXTPC_2_L_8 = 149, |
| MML1_D_GDMA_TXTPC_3_H_0 = 150, |
| MML1_D_GDMA_TXTPC_3_H_1 = 151, |
| MML1_D_GDMA_TXTPC_3_H_2 = 152, |
| MML1_D_GDMA_TXTPC_3_H_3 = 153, |
| MML1_D_GDMA_TXTPC_3_H_4 = 154, |
| MML1_D_GDMA_TXTPC_3_H_5 = 155, |
| MML1_D_GDMA_RXDFE_3_L_0 = 156, |
| MML1_D_GDMA_RXDFE_3_L_1 = 157, |
| MML1_D_GDMA_TXTPC_4_H_0 = 158, |
| MML1_D_GDMA_TXTPC_4_H_1 = 159, |
| MML1_D_GDMA_TXTPC_4_H_2 = 160, |
| MML1_D_GDMA_TXTPC_4_H_3 = 161, |
| MML1_D_GDMA_TXTPC_4_L_0 = 162, |
| MML1_D_GDMA_TXTPC_4_L_1 = 163, |
| MML1_D_GDMA_TXTPC_4_L_2 = 164, |
| MML1_D_GDMA_TXTPC_4_L_3 = 165, |
| MML1_D_GDMA_TXDFE_4_L_4 = 166, |
| MML1_D_GDMA_TXDFE_4_L_5 = 167, |
| MML1_D_GDMA_TXDFE_4_L_6 = 168, |
| MML1_D_GDMA_TXDFE_4_L_7 = 169, |
| MML1_D_GDMA_TXDFE_4_L_8 = 170, |
| MML1_D_GDMA_TXDFE_4_L_9 = 171, |
| MML1_D_GDMA_TXDFE_4_L_10 = 172, |
| MML1_D_GDMA_TXDFE_4_L_11 = 173, |
| MML1_D_GDMA_TXDFE_4_L_12 = 174, |
| MML1_D_GDMA_TXDFE_4_L_13 = 175, |
| MML1_D_GDMA_TXDFE_4_L_14 = 176, |
| MML1_D_GDMA_TXDFE_4_L_15 = 177, |
| MML1_D_GDMA_TXET_4_L_16 = 178, |
| MML1_D_GDMA_TXET_4_L_17 = 179, |
| MML1_D_GDMA_TXET_4_L_18 = 180, |
| MML1_D_GDMA_TXET_4_L_19 = 181, |
| MML1_D_GDMA_TXET_4_L_20 = 182, |
| MML1_D_GDMA_TXET_4_L_21 = 183, |
| MML1_D_GDMA_TXKGC_4_L_22 = 184, |
| MML1_D_GDMA_TXTPC_5_H_0 = 185, |
| MML1_D_GDMA_TXTPC_5_H_1 = 186, |
| MML1_D_GDMA_TXTPC_5_H_2 = 187, |
| MML1_D_GDMA_RXDFE_5_H_3 = 188, |
| MML1_D_GDMA_RXDFE_5_H_4 = 189, |
| MML1_D_GDMA_RXDFE_5_H_5 = 190, |
| MML1_D_GDMA_RXDFE_5_H_6 = 191, |
| MML1_D_GDMA_RXDFE_5_H_7 = 192, |
| MML1_D_GDMA_RXDFE_5_H_8 = 193, |
| MML1_D_GDMA_RXDFE_5_H_9 = 194, |
| MML1_D_GDMA_RXDFE_5_H_10 = 195, |
| MML1_D_GDMA_RXDFE_5_H_11 = 196, |
| MML1_D_GDMA_RXDFE_5_H_12 = 197, |
| MML1_D_GDMA_RXDFE_5_H_13 = 198, |
| MML1_D_GDMA_RXDFE_5_H_14 = 199, |
| MML1_D_GDMA_RXDFE_5_H_15 = 200, |
| MML1_D_GDMA_RXDFE_5_H_16 = 201, |
| MML1_D_GDMA_RXDFE_5_H_17 = 202, |
| MML1_D_GDMA_RXDFE_5_H_18 = 203, |
| MML1_D_GDMA_RXDFE_5_H_19 = 204, |
| MML1_D_GDMA_RXDFE_5_H_20 = 205, |
| MML1_D_GDMA_RXDFE_5_H_21 = 206, |
| MML1_D_GDMA_RXDFE_5_H_22 = 207, |
| MML1_D_GDMA_RXDFE_5_H_23 = 208, |
| MML1_D_GDMA_RXDFE_5_H_24 = 209, |
| MML1_D_GDMA_RXDFE_5_H_25 = 210, |
| MML1_D_GDMA_RXDFE_5_H_26 = 211, |
| MML1_D_GDMA_RXDFE_5_H_27 = 212, |
| MML1_D_GDMA_RXDFE_5_H_28 = 213, |
| MML1_D_GDMA_RXDFE_5_H_29 = 214, |
| MML1_D_GDMA_RXDFE_5_H_30 = 215, |
| MML1_D_GDMA_RXDFE_5_H_31 = 216, |
| MML1_D_GDMA_RXDFE_5_H_32 = 217, |
| MML1_D_GDMA_RXDFE_5_H_33 = 218, |
| MML1_D_GDMA_RXDFE_5_H_34 = 219, |
| MML1_D_GDMA_RXDFE_5_H_35 = 220, |
| MML1_D_GDMA_RXDFE_5_H_36 = 221, |
| MML1_D_GDMA_RXDFE_5_H_37 = 222, |
| MML1_D_GDMA_RXDFE_5_H_38 = 223, |
| MML1_D_GDMA_RXDFE_5_H_39 = 224, |
| MML1_D_GDMA_RXDFE_5_H_40 = 225, |
| MML1_D_GDMA_RXDFE_5_H_41 = 226, |
| MML1_D_GDMA_RXDFE_5_H_42 = 227, |
| MML1_D_GDMA_RXDFE_5_H_43 = 228, |
| MML1_D_GDMA_RXDFE_5_H_44 = 229, |
| MML1_D_GDMA_RXDFE_5_H_45 = 230, |
| MML1_D_GDMA_RXDFE_5_H_46 = 231, |
| MML1_D_GDMA_RXDFE_5_H_47 = 232, |
| MML1_D_GDMA_RXDFE_5_H_48 = 233, |
| MML1_D_GDMA_RXDFE_5_H_49 = 234, |
| MML1_D_GDMA_RXDFE_5_H_50 = 235, |
| MML1_D_GDMA_RXDFE_5_H_51 = 236, |
| MML1_D_GDMA_RXDFE_5_H_52 = 237, |
| MML1_D_GDMA_RXDFE_5_H_53 = 238, |
| MML1_D_GDMA_RXDFE_5_H_54 = 239, |
| MML1_D_GDMA_RXDFE_5_H_55 = 240, |
| MML1_D_GDMA_RXDFE_5_H_56 = 241, |
| MML1_D_GDMA_RXDFE_5_H_57 = 242, |
| MML1_D_GDMA_RXDFE_5_H_58 = 243, |
| MML1_D_GDMA_RXDFE_5_H_59 = 244, |
| MML1_D_GDMA_RXDFE_5_H_60 = 245, |
| MML1_D_GDMA_RXDFE_5_H_61 = 246, |
| MML1_D_GDMA_RXDFE_5_H_62 = 247, |
| MML1_D_GDMA_RXDFE_5_H_63 = 248, |
| MML1_D_GDMA_RXDFE_5_H_64 = 249, |
| MML1_D_GDMA_RXDFE_5_H_65 = 250, |
| MML1_D_GDMA_RXDFE_5_H_66 = 251, |
| MML1_D_GDMA_RXAGC_5_H_67 = 252, |
| MML1_D_GDMA_TXTPC_5_L_0 = 253, |
| MML1_D_GDMA_TXTPC_5_L_1 = 254, |
| MML1_D_GDMA_TXTPC_5_L_2 = 255, |
| MML1_D_GDMA_TXTPC_5_L_3 = 256, |
| MML1_D_GDMA_TXTPC_5_L_4 = 257, |
| MML1_D_GDMA_TXTPC_5_L_5 = 258, |
| MML1_D_GDMA_TXTPC_5_L_6 = 259, |
| MML1_D_GDMA_RXAGC_5_L_7 = 260, |
| MML1_D_GDMA_RXAGC_5_L_8 = 261, |
| MML1_D_GDMA_RXAGC_5_L_9 = 262, |
| MML1_D_GDMA_RXAGC_5_L_10 = 263, |
| MML1_D_GDMA_ID_SIZE = 264 |
| }MML1_D_GDMA_ID_E; |
| #endif |
| |
| |
| typedef enum |
| { |
| MML1_D_GDMA_PRIO_H = 0x0, |
| MML1_D_GDMA_PRIO_L = 0x1, |
| }MML1_D_GDMA_PRIO_E; |
| |
| typedef enum |
| { |
| MML1_D_GDMA_PORT_0 = 0x0, |
| MML1_D_GDMA_PORT_1 = 0x1, |
| MML1_D_GDMA_PORT_2 = 0x2, |
| MML1_D_GDMA_PORT_3 = 0x3, |
| MML1_D_GDMA_PORT_4 = 0x4, |
| MML1_D_GDMA_PORT_5 = 0x5, |
| }MML1_D_GDMA_PORT_E; |
| |
| |
| typedef enum |
| { |
| MML1_D_GDMA_MOD_TXTPC = 0x0, |
| MML1_D_GDMA_MOD_RXAGC = 0x1, |
| MML1_D_GDMA_MOD_TXDFE = 0x2, |
| MML1_D_GDMA_MOD_RXDFE = 0x3, |
| MML1_D_GDMA_MOD_L1RFD = 0x4, |
| MML1_D_GDMA_MOD_TXET = 0x5, |
| MML1_D_GDMA_MOD_TXKGC = 0x6, |
| }MML1_D_GDMA_MOD_E; |
| |
| typedef enum |
| { |
| MML1_D_GDMA_TRIG_IDLE = 0x0, |
| MML1_D_GDMA_TRIG_ERR_EMIADDR = 0x1,//emi addr not 128 byte align |
| MML1_D_GDMA_TRIG_ERR_LEN = 0x2, // len should be 2 word align |
| MML1_D_GDMA_TRIG_ERR_MOD = 0x3,//gdmaid and mod is mismatch |
| MML1_D_GDMA_TRIG_DONE_WO_IMMTRIG = 0x4,// config done wo imm trig |
| MML1_D_GDMA_TRIG_DONE = 0x5,// config done w imm trig |
| }MML1_D_GDMA_TRIG_STATUS_E; |
| |
| typedef enum |
| { |
| MML1_D_GDMA_CHK_IDLE = 0x0, |
| MML1_D_GDMA_CHK_ERR = 0x1, |
| MML1_D_GDMA_CHK_WAIT = 0x2, |
| MML1_D_GDMA_CHK_WORK = 0x3, |
| MML1_D_GDMA_CHK_DONE = 0x4, |
| }MML1_D_GDMA_CHK_STATUS_E; |
| |
| //struct |
| |
| typedef volatile struct { |
| MML1_D_GDMA_ID_E gdma_id; |
| MML1_D_GDMA_MOD_E mod; |
| MML1_D_GDMA_PORT_E port; |
| MML1_D_GDMA_PRIO_E prio; |
| kal_uint32 ch_id; |
| } MML1_D_GDMA_CFG_T; |
| /* Cross-Core Shared variable declare */ |
| |
| MML1_D_GDMA_TRIG_STATUS_E MML1_D_Gdma_Trig(kal_uint32 emi_addr, kal_uint32 hw_addr, kal_uint16 len, kal_uint8 trig_en, MML1_D_GDMA_ID_E id_gdma, MML1_D_GDMA_MOD_E mod); |
| MML1_D_GDMA_CHK_STATUS_E MML1_D_Gdma_Check_Status(MML1_D_GDMA_ID_E id_gdma); |
| void MML1_D_Gdma_Clear_Status(MML1_D_GDMA_ID_E id_gdma); |
| void MML1_D_Gdma_Clear_Error(MML1_D_GDMA_ID_E id_gdma); |
| |
| |
| |
| #endif //#ifndef _MML1_D_GDMA_H_ |