| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /***************************************************************************** |
| * |
| * Filename: |
| * --------- |
| * mmrf_common_cid.h |
| * |
| * Project: |
| * -------- |
| * MT6293 |
| * |
| * Description: |
| * ------------ |
| * Multi-Mode RF & BB Chip ID & Compile Option |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *---------------------------------------------------------------------------- |
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| * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| |
| #ifndef _MMRF_COMMON_CID_H_ |
| #define _MMRF_COMMON_CID_H_ |
| |
| /******************************************************************************* |
| ** Define BB chip in use |
| *******************************************************************************/ |
| |
| /* Divide chips into Series+Number */ |
| #define MML1_CHIP_SER(ID) (0xFFFFF000&ID) |
| #define MML1_CHIP_NUM(ID) (0x00000FFF&ID) |
| |
| /*---------------------------------------------------*/ |
| /* Before MML1 RF Central Control : */ |
| /*---------------------------------------------------*/ |
| /* After MML1 RF Central Control : */ |
| /* (1) IS_MML1_CHIP_MT6290 : LTE R9 Modem */ |
| /* (2) IS_MML1_CHIP_MT6595 : */ |
| /* (3) IS_MML1_CHIP_MT6752_MD1 : */ |
| /* (4) IS_MML1_CHIP_MT6752_MD2 : */ |
| /* (5) IS_MML1_CHIP_TK6291 : LTE-A R10 Modem */ |
| /* (6) IS_MML1_CHIP_MT6755 : LTE-A Smart Phone */ |
| /* (7) IS_MML1_CHIP_MT6797 : LTE-A Smart Phone */ |
| /*---------------------------------------------------*/ |
| |
| /*---------------------------------------------*/ |
| /* For Dual Mode Project (2G/3G) */ |
| /*---------------------------------------------*/ |
| |
| /*---------------------------------------------*/ |
| /* For MultiMode MultiRAT Project (2G/3G/LTE) */ |
| /*---------------------------------------------*/ |
| #define _MML1_CHIP_ID_MT6290 0x00001001 // MT6290 LTE Modem |
| #define _MML1_CHIP_ID_MT6595 0x00001002 // ROME LTE Smart Phone |
| #define _MML1_CHIP_ID_MT6752_MD1 0x00001003 // K2 MD1 LTE Smart Phone |
| #define _MML1_CHIP_ID_MT6752_MD2 0x00001004 // K2 MD2 LTE Smart Phone |
| #define _MML1_FPGA_ID_TK6291 0x00002000 // TK6291 LTE-A FPGA |
| #define _MML1_CHIP_ID_TK6291 0x00002001 // TK6291 LTE-A Test Chip |
| #define _MML1_CHIP_ID_MT6755 0x00002002 // Jade LTE-A Smart Phone |
| #define _MML1_CHIP_ID_MT6750 0x00002003 // Jade- LTE-A Smart Phone |
| #define _MML1_CHIP_ID_MT6750S 0x00002004 // Rosa LTE-A Smart Phone |
| #define _MML1_CHIP_ID_MT6797 0x00002005 // Everest LTE-A Smart Phone |
| #define _MML1_CHIP_ID_MT6757 0x00002006 // Olympus LTE-A Smart Phone |
| #define _MML1_CHIP_ID_MT6757P 0x00002007 // Kibo+ LTE-A Smart Phone |
| #define _MML1_FPGA_ID_MT6292 0x00003000 // Elbrus LTE-A FPGA |
| #define _MML1_CHIP_ID_MT6292 0x00003001 // Elbrus LTE-A Modem |
| #define _MML1_CHIP_ID_MT6799 0x00003002 // Whitney LTE-A Smart |
| #define _MML1_CHIP_ID_MT6799E2 0x00003003 // Whitney E2 LTE-A Smart |
| #define _MML1_CHIP_ID_MT6759 0x00003004 // Alaska LTE-A Smart |
| #define _MML1_CHIP_ID_MT6758 0x00003005 // Vinson LTE-A Smart |
| #define _MML1_FPGA_ID_MT6293 0x00004000 // Bianco LTE-A FPGA |
| #define _MML1_CHIP_ID_MT6293 0x00004001 // Bianco LTE-A Modem |
| #define _MML1_CHIP_ID_MT6739 0x00004002 // Zion LTE-A Modem |
| #define _MML1_CHIP_ID_MT6771 0x00004003 // Sylvia LTE-A Modem |
| #define _MML1_CHIP_ID_MT6765 0x00004004 // Cervino LTE-A Modem |
| #define _MML1_CHIP_ID_MT6761 0x00004005 // Merlot LTE-A Modem |
| #define _MML1_CHIP_ID_MT6295 0x00005000 |
| #define _MML1_FPGA_ID_MT6295M 0x00005001 // MT6295M LTE-A FPGA |
| #define _MML1_CHIP_ID_MT6295M 0x00005002 |
| #define _MML1_CHIP_ID_MT3967 0x00005003 // Eiger LTE-A Modem |
| #define _MML1_CHIP_ID_MT6779 0x00005004 // Lafite LTE-A Modem |
| #define _MML1_FPGA_ID_MT6297 0x00006000 // MT6297 LTE-A FPGA |
| #define _MML1_CHIP_ID_MT6297 0x00006001 // MT6297 LTE-A Modem |
| #define _MML1_FPGA_ID_MT6885 0x00006002 // MT6885 LTE-A FPGA |
| #define _MML1_CHIP_ID_MT6885 0x00006003 // MT6885 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6893 0x00006004 // MT6893 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6873 0x00006005 // MARGUAX LTE-A Modem |
| #define _MML1_CHIP_ID_MT6853 0x00006006 // MT6853 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6880 0x00006007 // MT6880 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6890 0x00006008 // MT6890 LTE-A Modem |
| #define _MML1_CHIP_ID_MT2735 0x00006009 // MT2735 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6833 0x0000600A // MT6833 LTE-A Modem |
| #define _MML1_CHIP_ID_MT6877 0x0000600B // MT6877 LTE-A Modem |
| #define _MML1_CHIP_ID_MERCURY 0x00007000 // MERCURY LTE-A Modem |
| |
| |
| /*.......................................................*/ |
| |
| #define IS_MML1_CHIP_SER(ID) ( MML1_CHIP_SER(_MML1_CHIP_ID)==MML1_CHIP_SER(ID) ) |
| #define IS_MML1_CHIP_SER_AND_LATTER(ID) ( MML1_CHIP_NUM(_MML1_CHIP_ID)>=MML1_CHIP_NUM(ID) && IS_MML1_CHIP_SER(ID) ) |
| #define IS_MML1_CHIP_SER_AND_BEFORE(ID) ( MML1_CHIP_NUM(_MML1_CHIP_ID)<=MML1_CHIP_NUM(ID) && IS_MML1_CHIP_SER(ID) ) |
| |
| /*.......................................................*/ |
| |
| #define IS_MML1_CHIP_MT6290_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6290) ) |
| #define IS_MML1_CHIP_TK6291_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_TK6291) ) |
| #define IS_MML1_CHIP_MT6755_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6755) ) |
| #define IS_MML1_CHIP_MT6797_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6797) ) |
| #define IS_MML1_CHIP_MT6750_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6750) ) |
| #define IS_MML1_CHIP_MT6750S_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6750S) ) |
| #define IS_MML1_CHIP_MT6757_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6757) ) |
| #define IS_MML1_CHIP_MT6757P_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6757P) ) |
| #define IS_MML1_CHIP_MT6292_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6292) ) |
| #define IS_MML1_CHIP_MT6799_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6799) ) |
| #define IS_MML1_CHIP_MT6799E2_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6799E2)) |
| #define IS_MML1_CHIP_MT6759_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6759) ) |
| #define IS_MML1_CHIP_MT6758_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6758) ) |
| #define IS_MML1_CHIP_MT6293_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6293) ) |
| #define IS_MML1_CHIP_MT6739_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6739) ) |
| #define IS_MML1_CHIP_MT6771_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6771) ) |
| #define IS_MML1_CHIP_MT6765_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6765) ) |
| #define IS_MML1_CHIP_MT6761_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6761) ) |
| #define IS_MML1_CHIP_MT6295_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6295) ) |
| #define IS_MML1_CHIP_MT3967_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT3967) ) |
| #define IS_MML1_CHIP_MT6779_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6779) ) |
| #define IS_MML1_CHIP_MT6297_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6297) ) |
| #define IS_MML1_CHIP_MT6885_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_FPGA_ID_MT6885) ) |
| #define IS_MML1_CHIP_MT6893_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6893) ) |
| #define IS_MML1_CHIP_MT6873_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6873) ) |
| #define IS_MML1_CHIP_MT6853_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6853) ) |
| #define IS_MML1_CHIP_MT6880_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6880) ) |
| #define IS_MML1_CHIP_MT6833_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6833) ) |
| #define IS_MML1_CHIP_MT6877_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MT6877) ) |
| #define IS_MML1_CHIP_MERCURY_AND_LATTER_VERSION ( IS_MML1_CHIP_SER_AND_LATTER(_MML1_CHIP_ID_MERCURY) ) |
| |
| |
| #define IS_MML1_CHIP_MT6290 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6290 ) |
| #define IS_MML1_CHIP_MT6595 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6595 ) |
| #define IS_MML1_CHIP_MT6752_MD1 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6752_MD1 ) |
| #define IS_MML1_CHIP_MT6752_MD2 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6752_MD2 ) |
| #define IS_MML1_FPGA_TK6291 ( _MML1_CHIP_ID==_MML1_FPGA_ID_TK6291 ) |
| #define IS_MML1_CHIP_TK6291 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_TK6291 )||( _MML1_CHIP_ID==_MML1_FPGA_ID_TK6291 ) ) |
| #define IS_MML1_CHIP_MT6755 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6755 ) |
| #define IS_MML1_CHIP_MT6797 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6797 ) |
| #define IS_MML1_CHIP_MT6750 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6750 ) |
| #define IS_MML1_CHIP_MT6750S ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6750S ) |
| #define IS_MML1_CHIP_MT6757 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6757 ) |
| #define IS_MML1_CHIP_MT6757P ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6757P ) |
| #define IS_MML1_FPGA_MT6292 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6292 ) |
| #define IS_MML1_CHIP_MT6292 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6292 ) |
| #define IS_MML1_CHIP_MT6799 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799E2 ) ) |
| #define IS_MML1_CHIP_MT6799E2 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6799E2 ) |
| #define IS_MML1_CHIP_MT6759 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6759 ) |
| #define IS_MML1_CHIP_MT6758 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6758 ) |
| #define IS_MML1_FPGA_MT6293 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6293 ) |
| #define IS_MML1_CHIP_MT6293 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6293 ) |
| #define IS_MML1_CHIP_MT6739 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6739 ) |
| #define IS_MML1_CHIP_MT6771 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6771 ) |
| #define IS_MML1_CHIP_MT6765 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6765 ) |
| #define IS_MML1_CHIP_MT6761 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6761 ) |
| #define IS_MML1_CHIP_MT6295 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6295 ) |
| #define IS_MML1_FPGA_MT6295M ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6295M ) |
| #define IS_MML1_CHIP_MT6295M ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6295M ) |
| #define IS_MML1_CHIP_MT3967 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT3967 ) |
| #define IS_MML1_CHIP_MT6779 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6779 ) |
| #define IS_MML1_FPGA_MT6297 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6297 ) |
| #define IS_MML1_CHIP_MT6297 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6297 ) |
| #define IS_MML1_FPGA_MT6885 ( _MML1_CHIP_ID==_MML1_FPGA_ID_MT6885 ) |
| #define IS_MML1_CHIP_MT6885 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6885 ) || ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6893 ) |
| #define IS_MML1_CHIP_MT6893 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6893 ) |
| #define IS_MML1_CHIP_MERCURY ( _MML1_CHIP_ID==_MML1_CHIP_ID_MERCURY ) |
| #define IS_MML1_CHIP_MT6873 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6873 ) |
| #define IS_MML1_CHIP_MT6853 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6853 ) |
| #define IS_MML1_CHIP_CHIP10992 ( ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6880 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6890 )||( _MML1_CHIP_ID==_MML1_CHIP_ID_MT2735 ) ) |
| #define IS_MML1_CHIP_MT6880 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6880 ) |
| #define IS_MML1_CHIP_MT6890 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6890 ) |
| #define IS_MML1_CHIP_MT2735 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT2735 ) |
| #define IS_MML1_CHIP_MT6833 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6833 ) |
| #define IS_MML1_CHIP_MT6877 ( _MML1_CHIP_ID==_MML1_CHIP_ID_MT6877 ) |
| |
| |
| |
| |
| |
| /*.......................................................*/ |
| |
| /* real chip use */ |
| #ifndef _MML1_CHIP_ID |
| #if defined(MT6763) |
| #if defined(__FPGA__) |
| #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6293 |
| #elif defined(MT6763_S00) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6293 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6293 |
| #endif |
| #elif defined(MT6739) |
| #if defined(MT6739_S00) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6739 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6739 |
| #endif |
| #elif defined(MT6771) |
| #if defined(MT6771_S00) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6771 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6771 |
| #endif |
| #elif defined(MT6765) |
| #if defined(MT6765_S00) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6765 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6765 |
| #endif |
| #elif defined(MT6761) |
| #if defined(MT6761_S00) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6761 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6761 |
| #endif |
| #elif defined(MT6295M) |
| #if defined(__FPGA__) |
| #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6295M |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6295M |
| #endif |
| #elif defined(MT3967) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT3967 |
| #elif defined(MT6779) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6779 |
| #elif defined(MT6297) |
| #if defined(__FPGA__) |
| #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6297 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6297 |
| #endif |
| #elif defined(MT6893) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6893 |
| #elif defined(MT6885) |
| #if defined(__FPGA__) |
| #define _MML1_CHIP_ID _MML1_FPGA_ID_MT6885 |
| #else |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6885 |
| #endif |
| #elif defined(MERCURY) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MERCURY |
| #elif defined(MT6873) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6873 |
| #elif defined(MT6853) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6853 |
| #elif defined(MT6880) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6880 |
| #elif defined(MT6890) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6890 |
| #elif defined(MT2735) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT2735 |
| #elif defined(MT6833) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6833 |
| #elif defined(MT6877) |
| #define _MML1_CHIP_ID _MML1_CHIP_ID_MT6877 |
| #else |
| #define _MML1_CHIP_ID 0 |
| //#error "please check chip version" |
| #endif |
| #else |
| #error "Unexpected BB Chip was defined" |
| #endif |
| /*.......................................................*/ |
| |
| /******************************************************************************* |
| ** Define RF chip in use |
| *******************************************************************************/ |
| |
| #if (defined(COLUMBUS_RF)||defined(MT6190T_RF)) |
| #define IS_MML1_RF_COLUMBUS (1) |
| #endif |
| |
| #if (defined(COLUMBUSE2_RF)||defined(MT6190_RF)) |
| #define IS_MML1_RF_COLUMBUSE2 (1) |
| #endif |
| |
| #if defined(MT6190M_RF) |
| #define IS_MML1_RF_MT6190M (1) |
| #endif |
| |
| #if defined(MT6195_RF) |
| #define IS_MML1_RF_MT6195 (1) |
| #endif |
| |
| /*.......................................................*/ |
| |
| /******************************************************************************* |
| ** Define PMIC chip in use |
| *******************************************************************************/ |
| |
| /*------------------------------------------*/ |
| /* Use in MML1 : */ |
| /* ( 1) MML1_PMIC_ID_MT6325 */ |
| /* ( 2) MML1_PMIC_ID_MT6351 */ |
| /* (FF) MML1_PMIC_ID_NONE */ |
| /*------------------------------------------*/ |
| |
| #define MML1_PMIC_ID_MT6325 0x00000001 |
| #define MML1_PMIC_ID_MT6351 0x00000002 |
| #define MML1_PMIC_ID_MT6353 0x00000003 |
| #define MML1_PMIC_ID_MT6335 0x00000004 |
| #define MML1_PMIC_ID_MT6356 0x00000005 |
| #define MML1_PMIC_ID_MT6357 0x00000006 |
| #define MML1_PMIC_ID_MT6358 0x00000007 |
| #define MML1_PMIC_ID_MT6359 0x00000008 |
| #define MML1_PMIC_ID_MT6359P 0x00000009 |
| #define MML1_PMIC_ID_MT6330 0x0000000A |
| #define MML1_PMIC_ID_NONE 0xFFFFFFFF //for non-MM RF |
| |
| /*.......................................................*/ |
| |
| #define IS_MML1_PMIC_MT6325 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6325 ) |
| #define IS_MML1_PMIC_MT6351 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6351 ) |
| #define IS_MML1_PMIC_MT6353 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6353 ) |
| #define IS_MML1_PMIC_MT6335 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6335 ) |
| #define IS_MML1_PMIC_MT6356 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6356 ) |
| #define IS_MML1_PMIC_MT6357 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6357 ) |
| #define IS_MML1_PMIC_MT6358 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6358 ) |
| #define IS_MML1_PMIC_MT6359 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6359 ) |
| #define IS_MML1_PMIC_MT6359P ( MML1_PMIC_ID==MML1_PMIC_ID_MT6359P ) |
| #define IS_MML1_PMIC_MT6330 ( MML1_PMIC_ID==MML1_PMIC_ID_MT6330 ) |
| #define IS_MML1_PMIC_NONE ( MML1_PMIC_ID==MML1_PMIC_ID_NONE ) |
| |
| #ifndef MML1_PMIC_ID |
| #if defined(MT6351) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6351 |
| #elif defined(MT6325) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6325 |
| #elif defined(MT6353) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6353 |
| #elif defined(MT6335) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6335 |
| #elif defined(MT6356) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6356 |
| #elif defined(MT6357) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6357 |
| #elif defined(MT6358) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6358 |
| #elif defined(MT6359) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6359 |
| #elif defined(MT6359P) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6359P |
| #elif defined(MT6330) |
| #define MML1_PMIC_ID MML1_PMIC_ID_MT6330 |
| #else |
| #define MML1_PMIC_ID MML1_PMIC_ID_NONE |
| #endif |
| #else |
| #error "Unexpected PMIC Chip was defined" |
| #endif //MML1_PMIC_ID |
| |
| #define IS_MML1_AMSC_CAL_ENABLE (0) |
| |
| #endif /* End of #ifndef _MMRF_COMMON_CID_H_ */ |
| |